dev/ntb/ntb_transport.c

346 	struct ntb_transport_mw *mw;
398 		mw = &nt->mw_vec[i];
400 		rc = ntb_mw_get_range(dev, i, &mw->phys_addr, &mw->vbase,
401 		    &mw->phys_size, &mw->xlat_align, &mw->xlat_align_size,
402 		    &mw->addr_limit);
406 		mw->tx_size = mw->phys_size;
407 		if (max_mw_size != 0 && mw->tx_size > max_mw_size) {
409 			    "%ju to %ju\n", i, (uintmax_t)mw->tx_size,
411 			mw->tx_size = max_mw_size;
413 		if (nt->compact && mw->tx_size > UINT32_MAX) {
415 			    "(%ju)\n", i, (uintmax_t)mw->tx_size);
420 		mw->rx_size = 0;
421 		mw->buff_size = 0;
422 		mw->virt_addr = NULL;
423 		mw->dma_addr = 0;
427 			ntb_printf(0, "Unable to set mw%d caching\n", i);
435 		ntb_set_mw(nt, i, mw->tx_size);
505 		mw = &nt->mw_vec[i];
506 		rc = ntb_mw_set_trans(nt->dev, i, mw->dma_addr, mw->buff_size);
508 			ntb_printf(0, "load time mw%d xlat fails, rc %d\n", i, rc);
597 	struct ntb_transport_mw *mw;
606 	mw = &nt->mw_vec[mw_num];
621 	mw_base = mw->phys_addr;
623 	tx_size = mw->tx_size / num_qps_mw;
626 	qp->tx_mw = mw->vbase + qp_offset;
1136 	struct ntb_transport_mw *mw;
1201 		mw = &nt->mw_vec[i];
1202 		mw->rx_size = val64;
1203 		val64 = roundup(val64, mw->xlat_align_size);
1204 		if (mw->buff_size != val64) {
1208 				ntb_printf(0, "link up set mw%d fails, rc %d\n",
1214 			rc = ntb_mw_set_trans(nt->dev, i, mw->dma_addr,
1215 			    mw->buff_size);
1217 				ntb_printf(0, "link up mw%d xlat fails, rc %d\n",
1264 	struct ntb_transport_mw *mw = &nt->mw_vec[num_mw];
1271 	buff_size = roundup(size, mw->xlat_align_size);
1274 	if (mw->buff_size == buff_size)
1277 	if (mw->buff_size != 0)
1281 	mw->buff_size = buff_size;
1283 	if (bus_dma_tag_create(bus_get_dma_tag(nt->dev), mw->xlat_align, 0,
1284 	    mw->addr_limit, BUS_SPACE_MAXADDR,
1285 	    NULL, NULL, mw->buff_size, 1, mw->buff_size,
1286 	    0, NULL, NULL, &mw->dma_tag)) {
1288 		    mw->buff_size);
1289 		mw->buff_size = 0;
1292 	if (bus_dmamem_alloc(mw->dma_tag, (void **)&mw->virt_addr,
1293 	    BUS_DMA_WAITOK | BUS_DMA_ZERO, &mw->dma_map)) {
1294 		bus_dma_tag_destroy(mw->dma_tag);
1296 		    mw->buff_size);
1297 		mw->buff_size = 0;
1300 	if (bus_dmamap_load(mw->dma_tag, mw->dma_map, mw->virt_addr,
1301 	    mw->buff_size, ntb_load_cb, &cba, BUS_DMA_NOWAIT) || cba.error) {
1302 		bus_dmamem_free(mw->dma_tag, mw->virt_addr, mw->dma_map);
1303 		bus_dma_tag_destroy(mw->dma_tag);
1305 		    mw->buff_size);
1306 		mw->buff_size = 0;
1309 	mw->dma_addr = cba.addr;
1317 	struct ntb_transport_mw *mw = &nt->mw_vec[num_mw];
1319 	if (mw->virt_addr == NULL)
1323 	bus_dmamap_unload(mw->dma_tag, mw->dma_map);
1324 	bus_dmamem_free(mw->dma_tag, mw->virt_addr, mw->dma_map);
1325 	bus_dma_tag_destroy(mw->dma_tag);
1326 	mw->buff_size = 0;
1327 	mw->virt_addr = NULL;
1334 	struct ntb_transport_mw *mw;
1342 	mw = &nt->mw_vec[mw_num];
1344 	if (mw->virt_addr == NULL)
1352 	rx_size = mw->rx_size / num_qps_mw;
1353 	qp->rx_buff = mw->virt_addr + rx_size * (qp_num / mw_count);