Lines Matching defs:BIT_3
189 #define BIT_3 (1 << 3)
290 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
307 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
338 #define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
371 #define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
401 #define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */
801 #define CS_MRST_CLR BIT_3 /* Clear Master Reset */
814 #define PC_VAUX_ON BIT_3 /* Switch VAUX On */
844 #define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
877 #define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
938 #define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */
992 #define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */
1077 #define TXA_START_RC BIT_3 /* Start sync Rate Control */
1085 #define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */
1113 #define BMU_OP_ON BIT_3 /* BMU Operational On */
1143 #define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
1162 #define RB_PC_DEC BIT_3 /* Packet Counter Decrement */
1178 #define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */
1235 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3
1386 #define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */
1434 #define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */
1480 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
1553 #define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */
1620 #define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */
1822 #define GM_GPSR_PART_MODE BIT_3 /* Partition mode */
1837 #define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */
1899 #define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */
1920 #define GMR_FS_FRAGMENT BIT_3 /* Fragment */
1978 #define GMF_OPER_ON BIT_3 /* Operational Mode On */
2013 #define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
2021 #define Y2_ASF_RESET BIT_3 /* ASF system in reset state */
2040 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3
2041 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
2042 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
2058 #define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
2076 #define GMC_PAUSE_ON BIT_3 /* Pause On */
2110 #define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */