Lines Matching defs:BIT_2
190 #define BIT_2 (1 << 2)
308 #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
339 #define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
372 #define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
402 #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */
802 #define CS_MRST_SET BIT_2 /* Set Master Reset */
815 #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
845 #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
878 #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
939 #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */
968 #define TIM_START BIT_2 /* Start Timer */
975 #define TIM_T_ON BIT_2 /* Test mode on */
993 #define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */
1029 #define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */
1045 #define BSC_T_ON BIT_2 /* Test mode on */
1078 #define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */
1086 #define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */
1114 #define BMU_OP_OFF BIT_2 /* BMU Operational Off */
1144 #define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
1163 #define RB_PC_T_ON BIT_2 /* Packet Counter Test On */
1171 #define RB_RP_T_ON BIT_2 /* Read Pointer Test On */
1179 #define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */
1236 #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2
1387 #define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */
1435 #define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */
1459 #define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */
1481 #define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */
1510 #define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */
1511 #define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */
1612 #define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */
1823 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
1838 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
1979 #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
2006 #define GMT_ST_START BIT_2 /* Start Time Stamp Timer */
2014 #define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
2022 #define Y2_ASF_RUNNING BIT_2 /* ASF system operational */
2043 #define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */
2059 #define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
2077 #define GMC_PAUSE_OFF BIT_2 /* Pause Off */
2111 #define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */