Lines Matching refs:setbit
1639 setbit(&ivar->timings, bus_timing_normal);
1710 setbit(&ivar->timings, bus_timing_hs);
1811 setbit(&ivar->timings, bus_timing_hs);
1814 setbit(&ivar->timings, bus_timing_hs);
1819 setbit(&ivar->timings, bus_timing_mmc_ddr52);
1820 setbit(&ivar->vccq_120, bus_timing_mmc_ddr52);
1824 setbit(&ivar->timings, bus_timing_mmc_ddr52);
1825 setbit(&ivar->vccq_180, bus_timing_mmc_ddr52);
1829 setbit(&ivar->timings, bus_timing_mmc_hs200);
1830 setbit(&ivar->vccq_120, bus_timing_mmc_hs200);
1834 setbit(&ivar->timings, bus_timing_mmc_hs200);
1835 setbit(&ivar->vccq_180, bus_timing_mmc_hs200);
1840 setbit(&ivar->timings, bus_timing_mmc_hs400);
1841 setbit(&ivar->vccq_120, bus_timing_mmc_hs400);
1846 setbit(&ivar->timings, bus_timing_mmc_hs400);
1847 setbit(&ivar->vccq_180, bus_timing_mmc_hs400);
1854 setbit(&ivar->timings, bus_timing_mmc_hs400es);
1855 setbit(&ivar->vccq_120, bus_timing_mmc_hs400es);
1862 setbit(&ivar->timings, bus_timing_mmc_hs400es);
1863 setbit(&ivar->vccq_180, bus_timing_mmc_hs400es);