Lines Matching refs:host_caps
1520 int host_caps;
1522 host_caps = mmcbr_get_caps(dev);
1524 #define HOST_TIMING_CAP(host_caps, cap) ({ \
1526 if (((host_caps) & (cap)) == (cap)) \
1537 return (HOST_TIMING_CAP(host_caps, MMC_CAP_HSPEED));
1539 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR12));
1541 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR25));
1543 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_DDR50));
1545 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR50));
1547 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR104));
1549 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_DDR52));
1551 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS200));
1553 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400));
1555 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400 |
1596 int err, host_caps, i, newcard;
1602 host_caps = mmcbr_get_caps(sc->dev);
1738 if ((host_caps & MMC_CAP_4_BIT_DATA) &&
1818 (host_caps & MMC_CAP_SIGNALING_120) != 0) {
1823 (host_caps & MMC_CAP_SIGNALING_180) != 0) {
1828 (host_caps & MMC_CAP_SIGNALING_120) != 0) {
1833 (host_caps & MMC_CAP_SIGNALING_180) != 0) {
1838 (host_caps & MMC_CAP_SIGNALING_120) != 0 &&
1844 (host_caps & MMC_CAP_SIGNALING_180) != 0 &&
1852 (host_caps & MMC_CAP_SIGNALING_120) != 0 &&
1860 (host_caps & MMC_CAP_SIGNALING_180) != 0 &&