Lines Matching defs:reg_val
460 uint32_t reg_idx, reg_off, reg_val, i;
465 reg_val = (1 | (queue << 1)) << reg_off;
469 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
479 uint32_t reg_val, i;
487 reg_val = ((1 | (queue << 1)) | (1 | (queue << 1)) << 8 |
491 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), reg_val);
492 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), reg_val);
496 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
1093 volatile uint32_t reg_val;
1148 reg_val = mge_set_port_serial_control(media_status);
1149 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
1182 reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
1183 reg_val |= PORT_SERIAL_ENABLE;
1184 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
1187 reg_val = MGE_READ(sc, MGE_PORT_STATUS);
1188 if (reg_val & MGE_STATUS_LINKUP)
1764 uint32_t reg_val, queued = 0;
1813 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
1814 MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_ENABLE_TXQ);
1823 volatile uint32_t reg_val, status;
1844 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
1845 MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_DISABLE_TXQ);
1878 reg_val = MGE_READ(sc, MGE_PORT_STATUS);
1879 if ( !(reg_val & MGE_STATUS_TX_IN_PROG) &&
1880 (reg_val & MGE_STATUS_TX_FIFO_EMPTY))
1890 reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
1891 reg_val &= ~(PORT_SERIAL_ENABLE);
1892 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL ,reg_val);