Lines Matching defs:reg_val
143 uint64_t reg_val;
151 reg_val =
155 reg_val = pf_num * LIO_CN23XX_PF_MAX_RINGS;
158 reg_val = reg_val |
163 reg_val);
198 volatile uint64_t reg_val =
201 while ((reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) &&
202 !(reg_val & LIO_CN23XX_PKT_INPUT_CTL_QUIET) &&
204 reg_val = lio_read_csr64(oct,
216 reg_val &= ~LIO_CN23XX_PKT_INPUT_CTL_RST;
218 reg_val);
220 reg_val = lio_read_csr64(oct,
222 if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
238 uint64_t pf_num, reg_val;
256 reg_val = oct->pcie_port <<
259 reg_val |= pf_num << LIO_CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
262 reg_val);
278 reg_val =
281 reg_val |= LIO_CN23XX_PKT_INPUT_CTL_MASK;
284 reg_val);
306 uint32_t ern, q_no, reg_val, srn;
319 reg_val = lio_read_csr32(oct,
323 reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_DPTR;
326 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_BMODE);
332 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P);
333 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P);
336 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ES_P);
338 reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES_P);
345 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR);
346 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR);
348 reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES);
352 reg_val);
457 uint32_t reg_val;
477 reg_val =
479 reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_TENB;
481 reg_val);
487 reg_val =
489 reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_CENB;
491 reg_val);
506 uint64_t reg_val;
516 reg_val = lio_read_csr64(oct,
518 reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_IS_64B;
521 reg_val);
529 reg_val = lio_read_csr64(oct,
532 if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
533 while ((reg_val &
535 !(reg_val &
538 reg_val = lio_read_csr64(oct,
547 reg_val = reg_val &
551 reg_val);
553 reg_val = lio_read_csr64(oct,
555 if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
561 reg_val = lio_read_csr64(oct,
563 reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_RING_ENB;
566 reg_val);
570 uint32_t reg_val;
573 reg_val = lio_read_csr32(oct,
575 reg_val = reg_val | LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB;
578 reg_val);