Lines Matching refs:phy
117 u32 swfw_mask = hw->phy.phy_semaphore_mask;
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
255 struct ixgbe_phy_info *phy = &hw->phy;
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
305 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
307 if (hw->phy.type == ixgbe_phy_unknown) {
308 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
313 hw->phy.type = ixgbe_phy_cu_unknown;
315 hw->phy.type = ixgbe_phy_generic;
334 if (!hw->phy.phy_semaphore_mask) {
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
341 if (hw->phy.type != ixgbe_phy_unknown)
344 if (hw->phy.nw_mng_if_sel) {
345 phy_addr = (hw->phy.nw_mng_if_sel &
361 /* Certain media types do not have a phy so an address will not
366 hw->phy.addr = 0;
401 * ixgbe_validate_phy_addr - Determines phy address is valid
413 hw->phy.addr = phy_addr;
414 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
426 * ixgbe_get_phy_id - Get the phy type
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
443 hw->phy.id = (u32)(phy_id_high << 16);
444 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
447 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
448 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
457 * ixgbe_get_phy_type_from_id - Get the phy type
509 if (hw->phy.type == ixgbe_phy_unknown)
512 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
516 if (!hw->phy.reset_if_overtemp &&
517 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
528 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
539 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
540 status = hw->phy.ops.read_reg(hw,
552 status = hw->phy.ops.read_reg(hw,
592 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
623 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
670 u32 gssr = hw->phy.phy_semaphore_mask;
677 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
703 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
732 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
770 u32 gssr = hw->phy.phy_semaphore_mask;
775 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
803 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
808 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
812 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
816 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
829 if ((hw->phy.autoneg_advertised &
837 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
841 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
846 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
865 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
870 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
894 hw->phy.autoneg_advertised = 0;
897 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
921 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
932 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
947 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
952 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
976 if (!hw->phy.speeds_supported)
979 *speed = hw->phy.speeds_supported;
1015 status = hw->phy.ops.read_reg(hw,
1053 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1058 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1061 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1068 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1073 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1076 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1083 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1088 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1091 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1101 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1106 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1124 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1143 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1173 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1178 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1228 hw->phy.ops.write_reg(hw, phy_offset,
1288 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1306 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1318 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1326 status = hw->phy.ops.read_i2c_eeprom(hw,
1334 hw->phy.type = ixgbe_phy_sfp_unsupported;
1337 status = hw->phy.ops.read_i2c_eeprom(hw,
1344 status = hw->phy.ops.read_i2c_eeprom(hw,
1350 status = hw->phy.ops.read_i2c_eeprom(hw,
1375 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1377 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1379 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1381 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1385 hw->phy.sfp_type =
1388 hw->phy.sfp_type =
1391 hw->phy.ops.read_i2c_eeprom(
1397 hw->phy.sfp_type =
1400 hw->phy.sfp_type =
1403 hw->phy.sfp_type =
1410 hw->phy.sfp_type =
1413 hw->phy.sfp_type =
1417 hw->phy.sfp_type =
1420 hw->phy.sfp_type =
1424 hw->phy.sfp_type =
1427 hw->phy.sfp_type =
1431 hw->phy.sfp_type =
1434 hw->phy.sfp_type =
1437 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1441 if (hw->phy.sfp_type != stored_sfp_type)
1442 hw->phy.sfp_setup_needed = TRUE;
1445 hw->phy.multispeed_fiber = FALSE;
1450 hw->phy.multispeed_fiber = TRUE;
1453 if (hw->phy.type != ixgbe_phy_nl) {
1454 hw->phy.id = identifier;
1455 status = hw->phy.ops.read_i2c_eeprom(hw,
1462 status = hw->phy.ops.read_i2c_eeprom(hw,
1469 status = hw->phy.ops.read_i2c_eeprom(hw,
1484 hw->phy.type =
1489 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1491 hw->phy.type = ixgbe_phy_sfp_ftl;
1494 hw->phy.type = ixgbe_phy_sfp_avago;
1497 hw->phy.type = ixgbe_phy_sfp_intel;
1500 hw->phy.type = ixgbe_phy_sfp_unknown;
1509 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1511 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1518 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1524 hw->phy.type = ixgbe_phy_sfp_unsupported;
1537 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1544 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1552 hw->phy.type =
1566 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1567 if (hw->phy.type != ixgbe_phy_nl) {
1568 hw->phy.id = 0;
1569 hw->phy.type = ixgbe_phy_unknown;
1588 hw->phy.ops.identify_sfp(hw);
1589 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1592 switch (hw->phy.type) {
1607 hw->phy.ops.read_i2c_eeprom(hw,
1609 hw->phy.ops.read_i2c_eeprom(hw,
1622 hw->phy.ops.read_i2c_eeprom(hw,
1646 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1660 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1668 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1675 hw->phy.type = ixgbe_phy_sfp_unsupported;
1680 hw->phy.id = identifier;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1695 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1705 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1713 hw->phy.ops.read_i2c_eeprom(hw,
1717 hw->phy.ops.read_i2c_eeprom(hw,
1721 hw->phy.ops.read_i2c_eeprom(hw,
1734 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1736 hw->phy.sfp_type =
1739 hw->phy.sfp_type =
1743 hw->phy.type = ixgbe_phy_sfp_unsupported;
1749 if (hw->phy.sfp_type != stored_sfp_type)
1750 hw->phy.sfp_setup_needed = TRUE;
1753 hw->phy.multispeed_fiber = FALSE;
1758 hw->phy.multispeed_fiber = TRUE;
1763 status = hw->phy.ops.read_i2c_eeprom(hw,
1770 status = hw->phy.ops.read_i2c_eeprom(hw,
1777 status = hw->phy.ops.read_i2c_eeprom(hw,
1790 hw->phy.type = ixgbe_phy_qsfp_intel;
1792 hw->phy.type = ixgbe_phy_qsfp_unknown;
1797 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1805 hw->phy.type =
1819 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1820 hw->phy.id = 0;
1821 hw->phy.type = ixgbe_phy_unknown;
1833 * so it returns the offsets to the phy init sequence block.
1840 u16 sfp_type = hw->phy.sfp_type;
1844 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1847 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1851 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1934 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1950 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1968 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1983 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2005 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2131 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2663 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2676 * ixgbe_set_copper_phy_power - Control power for copper phy
2688 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2702 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,