Lines Matching defs:this_controller
189 SCIC_SDS_CONTROLLER_T *this_controller;
190 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
192 this_controller->phy_startup_timer_pending = FALSE;
198 status = scic_sds_controller_start_next_phy(this_controller);
205 * @param this_controller
209 SCIC_SDS_CONTROLLER_T *this_controller
212 this_controller->phy_startup_timer = scic_cb_timer_create(
213 this_controller,
215 this_controller
218 if (this_controller->phy_startup_timer == NULL)
224 this_controller->next_phy_to_start = 0;
225 this_controller->phy_startup_timer_pending = FALSE;
235 * @param this_controller
238 SCIC_SDS_CONTROLLER_T *this_controller
241 this_controller->power_control.timer = scic_cb_timer_create(
242 this_controller,
244 this_controller
248 this_controller->power_control.requesters,
250 sizeof(this_controller->power_control.requesters)
253 this_controller->power_control.phys_waiting = 0;
254 this_controller->power_control.remote_devices_granted_power = 0;
271 * @param[in] this_controller This parameter specifies the controller
277 SCIC_SDS_CONTROLLER_T *this_controller
281 &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
283 (sizeof(U32) * this_controller->completion_queue_entries),
288 &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
290 this_controller->remote_node_entries * sizeof(SCU_REMOTE_NODE_CONTEXT_T),
295 &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
297 this_controller->task_context_entries * sizeof(SCU_TASK_CONTEXT_T),
305 &this_controller->uf_control
309 &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
311 scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
320 * @param[in] this_controller
325 SCIC_SDS_CONTROLLER_T *this_controller
331 &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
333 (sizeof(U32) * this_controller->completion_queue_entries),
341 &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
343 this_controller->remote_node_entries * sizeof(SCU_REMOTE_NODE_CONTEXT_T),
351 &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
353 this_controller->task_context_entries * sizeof(SCU_TASK_CONTEXT_T),
361 &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
363 scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
377 * @param[in] this_controller
382 SCIC_SDS_CONTROLLER_T *this_controller
389 mde = &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE];
390 this_controller->completion_queue = (U32*) mde->virtual_address;
391 SMU_CQBAR_WRITE(this_controller, mde->physical_address);
395 mde = &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT];
396 this_controller->remote_node_context_table = (SCU_REMOTE_NODE_CONTEXT_T *)
398 SMU_RNCBAR_WRITE(this_controller, mde->physical_address);
401 mde = &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT];
402 this_controller->task_context_table = (SCU_TASK_CONTEXT_T *)
404 SMU_HTTBAR_WRITE(this_controller, mde->physical_address);
406 mde = &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER];
408 &this_controller->uf_control, mde, this_controller
414 this_controller,
415 this_controller->uf_control.headers.physical_address);
417 this_controller,
418 this_controller->uf_control.address_table.physical_address);
422 this_controller,
427 this_controller,
436 * @param[in] this_controller
441 SCIC_SDS_CONTROLLER_T *this_controller
448 task_assignment = SMU_TCA_READ(this_controller, 0);
454 | (SMU_TCA_GEN_VAL(ENDING, this_controller->task_context_entries - 1))
458 SMU_TCA_WRITE(this_controller, 0, task_assignment);
464 * @param[in] this_controller
467 SCIC_SDS_CONTROLLER_T *this_controller
475 this_controller->completion_queue_get = 0;
478 SMU_CQC_QUEUE_LIMIT_SET(this_controller->completion_queue_entries - 1)
479 | SMU_CQC_EVENT_LIMIT_SET(this_controller->completion_event_entries - 1)
482 SMU_CQC_WRITE(this_controller, completion_queue_control_value);
492 SMU_CQGR_WRITE(this_controller, completion_queue_get_value);
494 this_controller->completion_queue_get = completion_queue_get_value;
502 SMU_CQPR_WRITE(this_controller, completion_queue_put_value);
505 for (index = 0; index < this_controller->completion_queue_entries; index++)
510 this_controller->completion_queue[index] = 0x80000000;
517 * @param[in] this_controller
520 SCIC_SDS_CONTROLLER_T *this_controller
529 SCU_UFQC_GEN_VAL(QUEUE_SIZE, this_controller->uf_control.address_table.count);
531 SCU_UFQC_WRITE(this_controller, frame_queue_control_value);
539 SCU_UFQGP_WRITE(this_controller, frame_queue_get_value);
544 SCU_UFQPP_WRITE(this_controller, frame_queue_put_value);
550 * @param[in] this_controller
553 SCIC_SDS_CONTROLLER_T *this_controller
558 port_task_scheduler_value = SCU_PTSGCR_READ(this_controller);
563 SCU_PTSGCR_WRITE(this_controller, port_task_scheduler_value);
573 * @param this_controller
576 SCIC_SDS_CONTROLLER_T *this_controller
583 this_controller, this_controller->lex_registers + 0xC4);
586 sci_base_object_get_logger(this_controller),
589 this_controller, lex_status
596 * @param this_controller
599 SCIC_SDS_CONTROLLER_T *this_controller
604 this_controller, this_controller->lex_registers + 0x28, 0x0020FFFF) ;
608 this_controller, this_controller->lex_registers + 0xC0, 0x00000700);
610 scic_sds_controller_lex_status_read_fence(this_controller);
614 this_controller, this_controller->lex_registers + 0x70, 0x00000002);
618 this_controller, this_controller->lex_registers + 0xC0, 0x00000300);
620 scic_sds_controller_lex_status_read_fence(this_controller);
624 this_controller, this_controller->lex_registers + 0x28, 0x0000FFFF);
627 scic_sds_controller_afe_initialization(this_controller);
629 scic_sds_controller_lex_status_read_fence(this_controller);
634 this_controller, this_controller->lex_registers + 0x28, 0x0000FFFF);
639 this_controller, this_controller->lex_registers + 0x28, 0x0040FFFF) ;
642 scic_sds_controller_afe_initialization(this_controller);
644 scic_sds_controller_lex_status_read_fence(this_controller);
649 this_controller, this_controller->lex_registers + 0x28, 0x0040FFFF) ;
654 this_controller, this_controller->lex_registers + 0xC0, 0x00000100);
656 scic_sds_controller_lex_status_read_fence(this_controller);
660 this_controller, this_controller->lex_registers + 0xC0, 0x00000000);
662 scic_sds_controller_lex_status_read_fence(this_controller);
667 this_controller, this_controller->lex_registers + 0xC0, 0x00000800);
669 scic_sds_controller_lex_status_read_fence(this_controller);
676 this_controller, this_controller->lex_registers + 0xC0, 0x27800000);
681 this_controller, this_controller->lex_registers + 0x28, 0x0000FF77);
684 this_controller, this_controller->lex_registers + 0x28, 0x0000FF55);
687 this_controller, this_controller->lex_registers + 0x28, 0x0000FF11);
690 this_controller, this_controller->lex_registers + 0x28, 0x0000FF00);
693 this_controller, this_controller->lex_registers + 0x28, 0x0003FF00);
703 * @param[in] this_controller
706 SCIC_SDS_CONTROLLER_T *this_controller
710 this_controller, this_controller->lex_registers + 0x88, 0x09090909);
713 this_controller, this_controller->lex_registers + 0x8C, 0xcac9c862);
728 * @param[in] this_controller
734 SCIC_SDS_CONTROLLER_T *this_controller
748 this_controller, afe_pll_control, 0x00247506);
752 this_controller, afe_dfx_transceiver_status_clear, 0x00000000);
764 this_controller, afe_transceiver_control0[0], 0x0700141e);
768 scu_afe_register_write(this_controller, afe_pll_control, 0x00200506);
769 scu_afe_register_write(this_controller, afe_pll_dfx_control, 0x10000080);
772 scu_afe_register_write(this_controller, afe_bias_control[0], 0x00124814);
773 scu_afe_register_write(this_controller, afe_bias_control[1], 0x24900000);
777 this_controller, afe_transceiver_control0[0], 0x0702941e);
780 this_controller, afe_transceiver_control1[0], 0x0000000a);
784 this_controller, afe_transceiver_equalization_control[0], 0x00ba2223);
787 this_controller, reserved_0028_003c[2], 0x00000000);
791 this_controller, afe_dfx_transmit_control_register[0], 0x03815428);
795 this_controller, afe_dfx_transceiver_status_clear, 0x00000010);
798 scu_afe_register_write(this_controller, afe_pll_control, 0x00200504);
801 scu_afe_register_write(this_controller, afe_pll_control, 0x00200505);
806 scu_afe_register_write(this_controller, afe_pll_control, 0x00200501);
808 while ((scu_afe_register_read(this_controller, afe_common_status) & 0x03) != 0x03)
819 this_controller, afe_transceiver_control0[0], 0x07028c11);
825 SCIC_SDS_CONTROLLER_T *this_controller
834 this_controller, afe_dfx_master_control0, 0x0000000f);
837 this_controller, afe_bias_control, 0x0000aa00);
840 this_controller, afe_pll_control0, 0x80000908);
847 this_controller, afe_common_block_status);
855 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000157);
858 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016d1a);
861 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01501014);
864 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00000000);
867 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0, 0x000bdd08);
869 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1, 0x000ffc00);
871 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2, 0x000b7c09);
873 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3, 0x000afc6e);
876 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00000000);
879 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x3208903f);
884 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000154);
888 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x3801611a);
892 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x3801631a);
896 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016318);
900 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016319);
904 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016319);
910 this_controller, afe_dfx_master_control0, 0x00010f00);
915 this_controller, afe_dfx_master_control0, 0x0081000f);
918 this_controller, afe_bias_control, 0x0000aa00);
921 this_controller, afe_pll_control0, 0x80000908);
930 this_controller, afe_common_block_status);
936 this_controller, afe_dfx_master_control1, 0x00000000);
939 this_controller, afe_pmsn_master_control0, 0x7bd316ad);
945 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000174);
948 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00030000);
951 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0000651a);
954 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006518);
957 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006518);
962 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00000000);
965 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0, 0x000bdd08);
967 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1, 0x000ffc00);
969 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2, 0x000b7c09);
971 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3, 0x000afc6e);
976 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000154);
981 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x00000080);
984 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x01041042);
987 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x320891bf);
991 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006118);
995 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006108);
1000 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x0317108f);
1004 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01e00021);
1008 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006109);
1012 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006009);
1016 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006209);
1022 this_controller, afe_dfx_master_control0, 0x00010f00);
1029 SCIC_SDS_CONTROLLER_T *this_controller
1037 (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_A0)
1038 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_A2)
1039 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_B0)
1040 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_C0)
1041 && (this_controller->pci_revision != SCIC_SDS_PCI_REVISION_C1)
1048 this_controller->pci_revision = SCIC_SDS_PCI_REVISION_C1;
1052 this_controller->oem_parameters.sds1.controller.cable_selection_mask;
1057 this_controller, afe_dfx_master_control0, 0x0081000f);
1061 (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1062 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1063 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1068 this_controller, afe_pmsn_master_control2, 0x0007FFFF);
1073 if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1074 scu_afe_register_write(this_controller, afe_bias_control, 0x00005500);
1075 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1076 scu_afe_register_write(this_controller, afe_bias_control, 0x00005A00);
1077 else if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1078 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0) )
1079 scu_afe_register_write(this_controller, afe_bias_control, 0x00005F00);
1080 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1081 scu_afe_register_write(this_controller, afe_bias_control, 0x00005500);
1087 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1088 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1090 scu_afe_register_write(this_controller, afe_pll_control0, 0x80040908);
1092 else if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1093 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0) )
1095 scu_afe_register_write(this_controller, afe_pll_control0, 0x80040A08);
1097 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1099 scu_afe_register_write(this_controller, afe_pll_control0, 0x80000b08);
1101 scu_afe_register_write(this_controller, afe_pll_control0, 0x00000b08);
1103 scu_afe_register_write(this_controller, afe_pll_control0, 0x80000b08);
1114 this_controller, afe_common_block_status);
1119 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1120 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1124 this_controller, afe_pmsn_master_control0, 0x7bcc96ad);
1133 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1134 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1139 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00004512
1144 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x0050100F
1148 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1152 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00030000
1156 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1160 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00010202
1167 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00014500
1171 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1175 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00010202
1182 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0001C500
1188 if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1191 this_controller,
1196 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1199 this_controller,
1204 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1208 this_controller,
1218 this_controller,
1223 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1226 this_controller,
1236 this_controller,
1241 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1244 this_controller,
1255 this_controller,
1264 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1265 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2) )
1269 this_controller,
1276 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1277 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1278 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0) )
1283 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00004100);
1286 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1289 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00014100);
1292 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1295 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0001c100);
1300 if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
1303 this_controller,
1308 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
1311 this_controller,
1316 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0)
1319 this_controller,
1327 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000);
1329 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C0)
1332 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01400c0f);
1336 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x3f6f103f);
1341 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000);
1343 else if (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_C1)
1346 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1,
1353 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x000003e0);
1357 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0,
1365 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000);
1371 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0,
1372 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control0
1377 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1,
1378 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control1
1383 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2,
1384 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control2
1389 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3,
1390 this_controller->oem_parameters.sds1.phys[phy_id].afe_tx_amp_control3
1397 this_controller, afe_dfx_master_control0, 0x00010f00);
1414 * @param[in,out] this_controller This parameter indicates the controller
1423 SCIC_SDS_CONTROLLER_T *this_controller,
1428 sci_base_object_get_logger(this_controller),
1431 this_controller, status
1434 if (this_controller->parent.state_machine.current_state_id
1440 scic_sds_controller_get_base_state_machine(this_controller),
1444 scic_cb_controller_start_complete(this_controller, status);
1463 SCIC_SDS_CONTROLLER_T *this_controller;
1464 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
1467 scic_sds_controller_get_base_state_machine(this_controller)
1473 this_controller, SCI_FAILURE_TIMEOUT
1479 scic_sds_controller_get_base_state_machine(this_controller),
1489 sci_base_object_get_logger(this_controller),
1499 * @param[in] this_controller
1504 SCIC_SDS_CONTROLLER_T *this_controller
1513 for (index = 0; index < this_controller->logical_port_entries; index++)
1515 port_status = this_controller->port_table[index].
1516 state_handlers->parent.stop_handler(&this_controller->port_table[index].parent);
1525 sci_base_object_get_logger(this_controller),
1528 this_controller->port_table[index].logical_port_index, port_status
1539 * @param[in] this_controller
1543 SCIC_SDS_CONTROLLER_T *this_controller
1547 this_controller,
1548 this_controller->phy_startup_timer,
1552 this_controller->phy_startup_timer_pending = TRUE;
1558 * @param[in] this_controller
1561 SCIC_SDS_CONTROLLER_T *this_controller
1565 this_controller,
1566 this_controller->phy_startup_timer
1569 this_controller->phy_startup_timer_pending = FALSE;
1580 * @param[in] this_controller This parameter specifies the controller
1586 SCIC_SDS_CONTROLLER_T *this_controller
1593 SCIC_SDS_PHY_T *the_phy = & this_controller->phy_table[index];
1597 this_controller->oem_parameters.sds1.controller.mode_type
1602 this_controller->oem_parameters.sds1.controller.mode_type
1634 this_controller->port_agent.phy_ready_mask
1635 != this_controller->port_agent.phy_configured_mask
1654 * @param[in] this_controller This parameter specifies the controller
1660 SCIC_SDS_CONTROLLER_T *this_controller
1667 if (this_controller->phy_startup_timer_pending == FALSE)
1669 if (this_controller->next_phy_to_start == SCI_MAX_PHYS)
1673 if (scic_sds_controller_is_start_complete(this_controller) == TRUE)
1676 this_controller, SCI_SUCCESS
1684 the_phy = &this_controller->phy_table[this_controller->next_phy_to_start];
1687 this_controller->oem_parameters.sds1.controller.mode_type
1693 this_controller->next_phy_to_start++;
1700 return scic_sds_controller_start_next_phy(this_controller);
1708 scic_sds_controller_phy_timer_start(this_controller);
1713 sci_base_object_get_logger(this_controller),
1716 this_controller->phy_table[this_controller->next_phy_to_start].phy_index,
1721 this_controller->next_phy_to_start++;
1731 * @param[in] this_controller
1736 SCIC_SDS_CONTROLLER_T *this_controller
1747 phy_status = scic_phy_stop(&this_controller->phy_table[index]);
1757 sci_base_object_get_logger(this_controller),
1760 this_controller->phy_table[index].phy_index, phy_status
1771 * @param[in] this_controller
1776 SCIC_SDS_CONTROLLER_T *this_controller
1785 for (index = 0; index < this_controller->remote_node_entries; index++)
1787 if (this_controller->device_table[index] != SCI_INVALID_HANDLE)
1790 device_status = scic_remote_device_stop(this_controller->device_table[index], 0);
1798 sci_base_object_get_logger(this_controller),
1801 this_controller->device_table[index], device_status
1817 * @param this_controller
1821 SCIC_SDS_CONTROLLER_T *this_controller
1825 this_controller, this_controller->power_control.timer,
1829 this_controller->power_control.timer_started = TRUE;
1835 * @param this_controller
1839 SCIC_SDS_CONTROLLER_T *this_controller
1842 if (this_controller->power_control.timer_started)
1845 this_controller, this_controller->power_control.timer
1848 this_controller->power_control.timer_started = FALSE;
1855 * @param this_controller
1859 SCIC_SDS_CONTROLLER_T *this_controller
1862 scic_sds_controller_power_control_timer_stop(this_controller);
1863 scic_sds_controller_power_control_timer_start(this_controller);
1876 SCIC_SDS_CONTROLLER_T *this_controller;
1877 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
1879 this_controller->power_control.remote_devices_granted_power = 0;
1881 if (this_controller->power_control.phys_waiting == 0)
1883 this_controller->power_control.timer_started = FALSE;
1892 && (this_controller->power_control.phys_waiting != 0);
1895 if (this_controller->power_control.requesters[i] != NULL)
1897 if ( this_controller->power_control.remote_devices_granted_power <
1898 this_controller->oem_parameters.sds1.controller.max_number_concurrent_device_spin_up
1901 the_phy = this_controller->power_control.requesters[i];
1902 this_controller->power_control.requesters[i] = NULL;
1903 this_controller->power_control.phys_waiting--;
1904 this_controller->power_control.remote_devices_granted_power ++;
1914 current_requester_phy = this_controller->power_control.requesters[j];
1925 this_controller->power_control.requesters[j] = NULL;
1926 this_controller->power_control.phys_waiting--;
1941 scic_sds_controller_power_control_timer_start(this_controller);
1948 * @param[in] this_controller
1952 SCIC_SDS_CONTROLLER_T *this_controller,
1958 if( this_controller->power_control.remote_devices_granted_power <
1959 this_controller->oem_parameters.sds1.controller.max_number_concurrent_device_spin_up
1962 this_controller->power_control.remote_devices_granted_power ++;
1967 scic_sds_controller_power_control_timer_restart (this_controller);
1977 current_phy = &this_controller->phy_table[i];
1994 this_controller->power_control.requesters[the_phy->phy_index] = the_phy;
1995 this_controller->power_control.phys_waiting++;
2004 * @param[in] this_controller
2008 SCIC_SDS_CONTROLLER_T *this_controller,
2014 if (this_controller->power_control.requesters[the_phy->phy_index] != NULL)
2016 this_controller->power_control.phys_waiting--;
2019 this_controller->power_control.requesters[the_phy->phy_index] = NULL;
2030 * @param[in] this_controller
2038 SCIC_SDS_CONTROLLER_T *this_controller
2041 U32 get_value = this_controller->completion_queue_get;
2045 == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
2060 * @param[in] this_controller
2067 SCIC_SDS_CONTROLLER_T *this_controller,
2075 io_request = this_controller->io_request_table[index];
2083 == this_controller->io_request_sequence[index]
2096 * @param[in] this_controller
2103 SCIC_SDS_CONTROLLER_T *this_controller,
2117 io_request = this_controller->io_request_table[index];
2119 sci_base_object_get_logger(this_controller),
2134 device = this_controller->device_table[index];
2136 sci_base_object_get_logger(this_controller),
2150 sci_base_object_get_logger(this_controller),
2161 scic_sds_controller_get_base_state_machine(this_controller),
2170 * @param[in] this_controller
2177 SCIC_SDS_CONTROLLER_T *this_controller,
2193 = this_controller->uf_control.buffers.array[frame_index].header;
2194 this_controller->uf_control.buffers.array[frame_index].state
2202 scic_sds_controller_release_frame(this_controller, frame_index);
2209 phy = &this_controller->phy_table[index];
2226 phy = &this_controller->phy_table[index];
2231 if (index < this_controller->remote_node_entries)
2232 device = this_controller->device_table[index];
2239 scic_sds_controller_release_frame(this_controller, frame_index);
2254 * @param[in] this_controller
2261 SCIC_SDS_CONTROLLER_T *this_controller,
2277 sci_base_object_get_logger(this_controller),
2280 this_controller, completion_entry
2286 this_controller->parent.error = SCI_CONTROLLER_FATAL_MEMORY_ERROR;
2289 scic_sds_controller_get_base_state_machine(this_controller),
2297 sci_base_object_get_logger(this_controller),
2300 this_controller, completion_entry
2305 io_request = this_controller->io_request_table[index];
2314 io_request = this_controller->io_request_table[index];
2322 sci_base_object_get_logger(this_controller),
2328 this_controller, completion_entry
2334 device = this_controller->device_table[index];
2342 sci_base_object_get_logger(this_controller),
2348 this_controller, completion_entry
2363 phy = &this_controller->phy_table[index];
2370 if (index < this_controller->remote_node_entries)
2372 device = this_controller->device_table[index];
2382 sci_base_object_get_logger(this_controller),
2388 this_controller, completion_entry, index
2395 sci_base_object_get_logger(this_controller),
2408 * @param[in] this_controller
2414 SCIC_SDS_CONTROLLER_T *this_controller
2425 sci_base_object_get_logger(this_controller),
2428 this_controller
2432 sci_base_object_get_logger(this_controller),
2435 this_controller->completion_queue_get
2439 get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
2440 get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
2442 event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
2443 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
2447 == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
2452 completion_entry = this_controller->completion_queue[get_index];
2453 INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
2456 sci_base_object_get_logger(this_controller),
2465 scic_sds_controller_task_completion(this_controller, completion_entry);
2469 scic_sds_controller_sdma_completion(this_controller, completion_entry);
2473 scic_sds_controller_unsolicited_frame(this_controller, completion_entry);
2477 scic_sds_controller_event_completion(this_controller, completion_entry);
2483 INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
2484 scic_sds_controller_event_completion(this_controller, completion_entry);
2489 sci_base_object_get_logger(this_controller),
2501 this_controller->completion_queue_get =
2507 SMU_CQGR_WRITE(this_controller, this_controller->completion_queue_get);
2511 sci_base_object_get_logger(this_controller),
2514 this_controller->completion_queue_get
2523 * @param[in] this_controller
2529 SCIC_SDS_CONTROLLER_T * this_controller
2540 sci_base_object_get_logger(this_controller),
2543 this_controller
2547 sci_base_object_get_logger(this_controller),
2550 this_controller->completion_queue_get
2554 get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
2555 get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
2557 event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
2558 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
2563 this_controller->completion_queue[get_index])
2568 completion_entry = this_controller->completion_queue[get_index];
2569 INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
2572 sci_base_object_get_logger(this_controller),
2581 scic_sds_controller_task_completion(this_controller, completion_entry);
2585 INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
2593 sci_base_object_get_logger(this_controller),
2605 this_controller->completion_queue_get =
2611 SMU_CQGR_WRITE(this_controller, this_controller->completion_queue_get);
2615 sci_base_object_get_logger(this_controller),
2618 this_controller->completion_queue_get
2640 SCIC_SDS_CONTROLLER_T *this_controller,
2647 sci_base_object_get_logger(this_controller),
2650 this_controller, interrupt_status
2657 && (!scic_sds_controller_completion_queue_has_entries(this_controller))
2667 this_controller->encountered_fatal_error = TRUE;
2670 if (scic_sds_controller_completion_queue_has_entries(this_controller))
2694 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
2710 interrupt_status = SMU_ISR_READ(this_controller);
2737 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2746 if (this_controller->encountered_fatal_error == TRUE)
2749 sci_base_object_get_logger(this_controller),
2755 scic_sds_controller_get_base_state_machine(this_controller),
2759 else if (scic_sds_controller_completion_queue_has_entries(this_controller))
2761 if (this_controller->restrict_completions == FALSE)
2762 scic_sds_controller_process_completions(this_controller);
2764 scic_sds_controller_transitioned_process_completions(this_controller);
2777 this_controller,
2800 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
2802 interrupt_status = SMU_ISR_READ(this_controller);
2804 this_controller, interrupt_status
2826 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2837 SMU_IMR_WRITE(this_controller, 0x00000000);
2884 SCIC_SDS_CONTROLLER_T *this_controller;
2885 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2891 SMU_IMR_WRITE(this_controller, 0xFFFFFFFF);
2893 interrupt_status = SMU_ISR_READ(this_controller);
2898 && scic_sds_controller_completion_queue_has_entries(this_controller)
2903 SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
2918 SMU_ISR_WRITE(this_controller, 0x00000000);
2919 SMU_IMR_WRITE(this_controller, 0x00000000);
2936 SCIC_SDS_CONTROLLER_T *this_controller;
2937 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
2946 interrupt_status = SMU_ISR_READ(this_controller);
2952 sci_base_object_get_logger(this_controller),
2960 scic_sds_controller_get_base_state_machine(this_controller),
2968 && !scic_sds_controller_completion_queue_has_entries(this_controller)
2972 sci_base_object_get_logger(this_controller),
2980 scic_sds_controller_get_base_state_machine(this_controller),
2986 if (scic_sds_controller_completion_queue_has_entries(this_controller))
2988 scic_sds_controller_process_completions(this_controller);
2993 this_controller,
2998 SMU_IMR_WRITE(this_controller, 0x00000000);
3016 SCIC_SDS_CONTROLLER_T *this_controller;
3017 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3019 if (scic_sds_controller_completion_queue_has_entries(this_controller))
3027 SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
3033 SMU_IMR_WRITE(this_controller, 0xFF000000);
3034 SMU_IMR_WRITE(this_controller, 0x00000000);
3051 SCIC_SDS_CONTROLLER_T *this_controller;
3052 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3062 if (scic_sds_controller_completion_queue_has_entries(this_controller))
3064 scic_sds_controller_process_completions(this_controller);
3068 SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
3070 SMU_IMR_WRITE(this_controller, 0xFF000000);
3071 SMU_IMR_WRITE(this_controller, 0x00000000);
3091 SCIC_SDS_CONTROLLER_T *this_controller;
3092 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3095 interrupt_status = SMU_ISR_READ(this_controller);
3110 SMU_IMR_WRITE(this_controller, 0x000000FF);
3111 SMU_IMR_WRITE(this_controller, 0x00000000);
3128 SCIC_SDS_CONTROLLER_T *this_controller;
3129 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3138 interrupt_status = SMU_ISR_READ(this_controller);
3142 && scic_sds_controller_completion_queue_has_entries(this_controller)
3145 scic_sds_controller_process_completions(this_controller);
3147 SMU_ISR_WRITE(this_controller, SMU_ISR_QUEUE_SUSPEND);
3152 sci_base_object_get_logger(this_controller),
3159 scic_sds_controller_get_base_state_machine(this_controller),
3168 SMU_IMR_WRITE(this_controller, 0x00000000);
3220 * @param[in] this_controller
3227 SCIC_SDS_CONTROLLER_T *this_controller,
3232 if (this_controller->state_handlers->link_up_handler != NULL)
3234 this_controller->state_handlers->link_up_handler(
3235 this_controller, the_port, the_phy);
3240 sci_base_object_get_logger(this_controller),
3245 scic_sds_controller_get_base_state_machine(this_controller))
3253 * @param[in] this_controller
3258 SCIC_SDS_CONTROLLER_T *this_controller,
3263 if (this_controller->state_handlers->link_down_handler != NULL)
3265 this_controller->state_handlers->link_down_handler(
3266 this_controller, the_port, the_phy);
3271 sci_base_object_get_logger(this_controller),
3276 scic_sds_controller_get_base_state_machine(this_controller))
3285 * @param[in] this_controller
3289 SCIC_SDS_CONTROLLER_T * this_controller,
3293 if (this_controller->state_handlers->remote_device_started_handler != NULL)
3295 this_controller->state_handlers->remote_device_started_handler(
3296 this_controller, the_device
3302 sci_base_object_get_logger(this_controller),
3305 this_controller,
3308 scic_sds_controller_get_base_state_machine(this_controller))
3317 * @param[in] this_controller
3320 SCIC_SDS_CONTROLLER_T * this_controller
3325 for (index = 0; index < this_controller->remote_node_entries; index++)
3328 (this_controller->device_table[index] != NULL)
3330 this_controller->device_table[index]->parent.state_machine.current_state_id
3346 * @param[in] this_controller
3350 SCIC_SDS_CONTROLLER_T * this_controller,
3354 if (this_controller->state_handlers->remote_device_stopped_handler != NULL)
3356 this_controller->state_handlers->remote_device_stopped_handler(
3357 this_controller, the_device
3363 sci_base_object_get_logger(this_controller),
3366 this_controller,
3369 scic_sds_controller_get_base_state_machine(this_controller))
3378 * @param[in] this_controller
3382 SCIC_SDS_CONTROLLER_T *this_controller,
3387 sci_base_object_get_logger(this_controller),
3390 this_controller, request
3393 SMU_PCP_WRITE(this_controller, request);
3405 * @param[in] this_controller This parameter specifies the controller for
3413 SCIC_SDS_CONTROLLER_T *this_controller,
3420 this_controller, this_request->io_tag
3438 * @param[in] this_controller
3444 SCIC_SDS_CONTROLLER_T * this_controller,
3450 if (task_index < this_controller->task_context_entries)
3452 return &this_controller->task_context_table[task_index];
3461 * @param[in] this_controller
3467 SCIC_SDS_CONTROLLER_T *this_controller,
3477 * @param[in] this_controller
3484 SCIC_SDS_CONTROLLER_T *this_controller,
3493 if (task_index < this_controller->task_context_entries)
3495 if (this_controller->io_request_table[task_index] != SCI_INVALID_HANDLE)
3499 if (task_sequence == this_controller->io_request_sequence[task_index])
3501 return this_controller->io_request_table[task_index];
3514 * @param[in] this_controller This is the controller object which contains
3526 SCIC_SDS_CONTROLLER_T * this_controller,
3535 &this_controller->available_remote_nodes, remote_node_count
3540 this_controller->device_table[node_index] = the_device;
3555 * @param[in] this_controller
3562 SCIC_SDS_CONTROLLER_T * this_controller,
3569 if (this_controller->device_table[node_id] == the_device)
3571 this_controller->device_table[node_id] = SCI_INVALID_HANDLE;
3574 &this_controller->available_remote_nodes, remote_node_count, node_id
3583 * @param[in] this_controller
3589 SCIC_SDS_CONTROLLER_T *this_controller,
3594 (node_id < this_controller->remote_node_entries)
3595 && (this_controller->device_table[node_id] != SCI_INVALID_HANDLE)
3598 return &this_controller->remote_node_context_table[node_id];
3641 * @param[in] this_controller
3647 SCIC_SDS_CONTROLLER_T *this_controller,
3652 &this_controller->uf_control, frame_index) == TRUE)
3653 SCU_UFQGP_WRITE(this_controller, this_controller->uf_control.get);
3658 SCIC_SDS_CONTROLLER_T *this_controller
3662 &this_controller->parent.state_machine_logger,
3663 &this_controller->parent.state_machine,
3664 &this_controller->parent.parent,
3672 SCIC_SDS_CONTROLLER_T *this_controller
3676 &this_controller->parent.state_machine_logger,
3677 &this_controller->parent.state_machine
3696 SCIC_SDS_CONTROLLER_T *this_controller
3702 this_controller->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
3705 this_controller->oem_parameters.sds1.controller.max_number_concurrent_device_spin_up = 1;
3708 this_controller->oem_parameters.sds1.controller.ssc_sata_tx_spread_level = 0;
3709 this_controller->oem_parameters.sds1.controller.ssc_sas_tx_spread_level = 0;
3710 this_controller->oem_parameters.sds1.controller.ssc_sas_tx_type = 0;
3713 this_controller->oem_parameters.sds1.controller.cable_selection_mask = 0;
3718 this_controller->oem_parameters.sds1.ports[index].phy_mask = 0;
3726 this_controller->user_parameters.sds1.phys[index].max_speed_generation = 2;
3729 this_controller->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
3730 this_controller->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
3731 this_controller->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
3737 this_controller->oem_parameters.sds1.phys[index].sas_address.sci_format.high
3741 this_controller->oem_parameters.sds1.phys[index].sas_address.sci_format.low
3742 = 0x00000001 + this_controller->controller_index;
3744 if ( (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A0)
3745 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_A2)
3746 || (this_controller->pci_revision == SCIC_SDS_PCI_REVISION_B0) )
3748 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control0 = 0x000E7C03;
3749 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control1 = 0x000E7C03;
3750 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control2 = 0x000E7C03;
3751 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control3 = 0x000E7C03;
3755 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control0 = 0x000BDD08;
3756 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control1 = 0x000B7069;
3757 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control2 = 0x000B7C09;
3758 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control3 = 0x000AFC6E;
3762 this_controller->user_parameters.sds1.stp_inactivity_timeout = 5;
3763 this_controller->user_parameters.sds1.ssp_inactivity_timeout = 5;
3764 this_controller->user_parameters.sds1.stp_max_occupancy_timeout = 5;
3765 this_controller->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
3766 this_controller->user_parameters.sds1.no_outbound_task_timeout = 20;
3774 * @param[in] this_controller This parameter specifies the core
3785 SCIC_SDS_CONTROLLER_T * this_controller
3793 sci_base_object_get_logger(this_controller),
3796 this_controller
3799 if(this_controller->phy_startup_timer != NULL)
3801 scic_cb_timer_destroy(this_controller, this_controller->phy_startup_timer);
3802 this_controller->phy_startup_timer = NULL;
3805 if(this_controller->power_control.timer != NULL)
3807 scic_cb_timer_destroy(this_controller, this_controller->power_control.timer);
3808 this_controller->power_control.timer = NULL;
3811 if(this_controller->timeout_timer != NULL)
3813 scic_cb_timer_destroy(this_controller, this_controller->timeout_timer);
3814 this_controller->timeout_timer = NULL;
3818 this_controller,
3819 &this_controller->port_agent);
3823 port = &this_controller->port_table[index];
3824 scic_sds_port_release_resource(this_controller, port);
3829 phy = &this_controller->phy_table[index];
3830 scic_sds_phy_release_resource(this_controller, phy);
3841 * @param[in] this_controller This parameter specifies the core
3847 SCIC_SDS_CONTROLLER_T * this_controller
3852 this_controller, SCI_SUCCESS
3868 SCIC_SDS_CONTROLLER_T *this_controller;
3871 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3881 memset(this_controller, 0, sizeof(SCIC_SDS_CONTROLLER_T));
3887 this_controller->controller_index =
3888 scic_sds_library_get_controller_index(my_library, this_controller);
3890 this_controller->pci_revision = my_library->pci_revision;
3893 &this_controller->parent,
3896 this_controller->memory_descriptors,
3897 ARRAY_SIZE(this_controller->memory_descriptors),
3903 scic_sds_controller_initialize_state_logging(this_controller);
3905 scic_sds_pci_bar_initialization(this_controller);
3917 SCIC_SDS_CONTROLLER_T *this_controller;
3918 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3927 if (this_controller->state_handlers->parent.initialize_handler != NULL)
3929 status = this_controller->state_handlers->parent.initialize_handler(
3936 sci_base_object_get_logger(this_controller),
3940 scic_sds_controller_get_base_state_machine(this_controller))
3983 SCIC_SDS_CONTROLLER_T *this_controller;
3984 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
3993 if (this_controller->state_handlers->parent.start_handler != NULL)
3995 status = this_controller->state_handlers->parent.start_handler(
4002 sci_base_object_get_logger(this_controller),
4006 scic_sds_controller_get_base_state_machine(this_controller))
4021 SCIC_SDS_CONTROLLER_T *this_controller;
4022 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4031 if (this_controller->state_handlers->parent.stop_handler != NULL)
4033 status = this_controller->state_handlers->parent.stop_handler(
4040 sci_base_object_get_logger(this_controller),
4044 scic_sds_controller_get_base_state_machine(this_controller))
4058 SCIC_SDS_CONTROLLER_T *this_controller;
4059 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4068 if (this_controller->state_handlers->parent.reset_handler != NULL)
4070 status = this_controller->state_handlers->parent.reset_handler(
4077 sci_base_object_get_logger(this_controller),
4081 scic_sds_controller_get_base_state_machine(this_controller))
4171 SCIC_SDS_CONTROLLER_T *this_controller;
4172 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4181 status = this_controller->state_handlers->parent.start_io_handler(
4182 &this_controller->parent,
4200 SCIC_SDS_CONTROLLER_T *this_controller;
4201 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4210 status = this_controller->state_handlers->terminate_request_handler(
4211 &this_controller->parent,
4228 SCIC_SDS_CONTROLLER_T *this_controller;
4229 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4238 status = this_controller->state_handlers->parent.complete_io_handler(
4239 &this_controller->parent,
4259 SCIC_SDS_CONTROLLER_T *this_controller;
4260 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4269 if (this_controller->state_handlers->parent.start_task_handler != NULL)
4271 status = this_controller->state_handlers->parent.start_task_handler(
4272 &this_controller->parent,
4299 SCIC_SDS_CONTROLLER_T *this_controller;
4300 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4309 if (this_controller->state_handlers->parent.complete_task_handler != NULL)
4311 status = this_controller->state_handlers->parent.complete_task_handler(
4312 &this_controller->parent,
4339 SCIC_SDS_CONTROLLER_T *this_controller;
4340 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4349 if (port_index < this_controller->logical_port_entries)
4351 *port_handle = &this_controller->port_table[port_index];
4367 SCIC_SDS_CONTROLLER_T *this_controller;
4368 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4377 if (phy_index < ARRAY_SIZE(this_controller->phy_table))
4379 *phy_handle = &this_controller->phy_table[phy_index];
4385 sci_base_object_get_logger(this_controller),
4388 this_controller, phy_index
4402 SCIC_SDS_CONTROLLER_T *this_controller;
4403 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4412 if (!sci_pool_empty(this_controller->tci_pool))
4414 sci_pool_get(this_controller->tci_pool, task_context);
4416 sequence_count = this_controller->io_request_sequence[task_context];
4434 SCIC_SDS_CONTROLLER_T *this_controller;
4435 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4449 if (!sci_pool_full(this_controller->tci_pool))
4451 if (sequence == this_controller->io_request_sequence[index])
4454 this_controller->io_request_sequence[index]);
4456 sci_pool_put(this_controller->tci_pool, index);
4471 SCIC_SDS_CONTROLLER_T *this_controller;
4472 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4474 ASSERT(this_controller->smu_registers != NULL);
4476 SMU_IMR_WRITE(this_controller, 0x00000000);
4485 SCIC_SDS_CONTROLLER_T *this_controller;
4486 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
4488 ASSERT(this_controller->smu_registers != NULL);
4490 SMU_IMR_WRITE(this_controller, 0xffffffff);
4500 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4511 (this_controller->parent.state_machine.current_state_id
4513 || (this_controller->parent.state_machine.current_state_id
4520 this_controller->remote_node_entries =
4521 MIN(this_controller->remote_node_entries, SCI_MAX_REMOTE_DEVICES);
4522 this_controller->task_context_entries =
4523 MIN(this_controller->task_context_entries, SCU_IO_REQUEST_COUNT);
4524 this_controller->uf_control.buffers.count =
4525 MIN(this_controller->uf_control.buffers.count, SCU_UNSOLICITED_FRAME_COUNT);
4526 this_controller->completion_event_entries =
4527 MIN(this_controller->completion_event_entries, SCU_EVENT_COUNT);
4528 this_controller->completion_queue_entries =
4529 MIN(this_controller->completion_queue_entries, SCU_COMPLETION_QUEUE_COUNT);
4531 scic_sds_controller_build_memory_descriptor_table(this_controller);
4535 this_controller->remote_node_entries =
4536 MIN(this_controller->remote_node_entries, SCI_MIN_REMOTE_DEVICES);
4537 this_controller->task_context_entries =
4538 MIN(this_controller->task_context_entries, SCI_MIN_IO_REQUESTS);
4539 this_controller->uf_control.buffers.count =
4540 MIN(this_controller->uf_control.buffers.count, SCU_MIN_UNSOLICITED_FRAMES);
4541 this_controller->completion_event_entries =
4542 MIN(this_controller->completion_event_entries, SCU_MIN_EVENTS);
4543 this_controller->completion_queue_entries =
4544 MIN(this_controller->completion_queue_entries, SCU_MIN_COMPLETION_QUEUE_ENTRIES);
4546 scic_sds_controller_build_memory_descriptor_table(this_controller);
4563 * @param[in] this_controller The controller that is to be reset.
4566 SCIC_SDS_CONTROLLER_T * this_controller
4570 scic_controller_disable_interrupts(this_controller);
4573 SMU_SMUSRCR_WRITE(this_controller, 0xFFFFFFFF);
4579 SMU_CQGR_WRITE(this_controller, 0x00000000);
4582 SCU_UFQGP_WRITE(this_controller, 0x00000000);
4592 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4595 (this_controller->parent.state_machine.current_state_id
4597 || (this_controller->parent.state_machine.current_state_id
4599 || (this_controller->parent.state_machine.current_state_id
4640 (&this_controller->user_parameters), scic_parms, sizeof(*scic_parms));
4655 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4657 memcpy(scic_parms, (&this_controller->user_parameters), sizeof(*scic_parms));
4667 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4673 (this_controller->parent.state_machine.current_state_id
4675 || (this_controller->parent.state_machine.current_state_id
4677 || (this_controller->parent.state_machine.current_state_id
4689 this_controller->oem_parameters_version = scic_parms_version;
4788 (&this_controller->oem_parameters), scic_parms, sizeof(*scic_parms));
4802 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
4804 memcpy(scic_parms, (&this_controller->oem_parameters), sizeof(*scic_parms));
5032 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
5047 &(this_controller->port_table[index]));
5051 SMU_CQGR_WRITE(this_controller, 0x00000000);
5052 SCU_UFQGP_WRITE(this_controller, 0x00000000);
5056 SMU_ISR_WRITE(this_controller, 0xFFFFFFFF);
5059 this_controller->completion_queue_get = 0;
5070 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
5074 scic_sds_controller_initialize_completion_queue(this_controller);
5075 scic_sds_controller_initialize_unsolicited_frame_queue(this_controller);
5077 this_controller->restrict_completions = FALSE;
5083 &(this_controller->port_table[index]));
5090 SCIC_SDS_PHY_T * curr_phy = &this_controller->phy_table[index];
5112 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
5122 if (this_controller->parent.state_machine.current_state_id
5129 if (this_controller->port_table[index].started_request_count != 0)
5138 this_controller);
5141 scic_sds_controller_ram_initialization(this_controller);
5142 this_controller->restrict_completions = restrict_completions;
5243 SCIC_SDS_CONTROLLER_T *this_controller;
5244 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5247 sci_base_object_get_logger(this_controller),
5251 scic_sds_controller_get_base_state_machine(this_controller))
5279 SCIC_SDS_CONTROLLER_T *this_controller;
5280 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5283 sci_base_object_get_logger(this_controller),
5287 scic_sds_controller_get_base_state_machine(this_controller))
5313 SCIC_SDS_CONTROLLER_T *this_controller;
5314 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5324 scic_sds_controller_release_resource(this_controller);
5329 scic_sds_controller_get_base_state_machine(this_controller),
5361 SCIC_SDS_CONTROLLER_T *this_controller;
5363 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5373 scic_sds_controller_get_base_state_machine(this_controller),
5377 this_controller->timeout_timer = scic_cb_timer_create(
5383 scic_sds_controller_initialize_power_control(this_controller);
5388 scic_sds_controller_reset_hardware(this_controller);
5391 scic_sds_controller_lex_atux_initialization(this_controller);
5395 scic_sds_controller_afe_initialization(this_controller);
5401 scic_sds_controller_afe_initialization(this_controller);
5412 SMU_SMUSRCR_WRITE(this_controller, 0x00000000);
5423 status = SMU_SMUCSR_READ(this_controller);
5433 scic_sds_controller_enable_chipwatch(this_controller);
5445 device_context_capacity = SMU_DCC_READ(this_controller);
5458 this_controller,
5459 this_controller->scu_registers->peg0.ptsg.protocol_engine[index],
5467 scic_controller_set_mode(this_controller, SCI_MODE_SPEED);
5470 this_controller->logical_port_entries =
5471 MIN(max_supported_ports, this_controller->logical_port_entries);
5473 this_controller->task_context_entries =
5474 MIN(max_supported_io_requests, this_controller->task_context_entries);
5476 this_controller->remote_node_entries =
5477 MIN(max_supported_devices, this_controller->remote_node_entries);
5486 dma_configuration = SCU_PDMACR_READ(this_controller);
5488 SCU_PDMACR_WRITE(this_controller, dma_configuration);
5491 dma_configuration = SCU_CDMACR_READ(this_controller);
5493 SCU_CDMACR_WRITE(this_controller, dma_configuration);
5506 &this_controller->phy_table[index],
5507 &this_controller->scu_registers->peg0.pe[index].tl,
5508 &this_controller->scu_registers->peg0.pe[index].ll
5516 scic_sgpio_hardware_initialize(this_controller);
5523 (index < this_controller->logical_port_entries)
5528 &this_controller->port_table[index],
5529 &this_controller->scu_registers->peg0.ptsg.port[index],
5530 &this_controller->scu_registers->peg0.ptsg.protocol_engine,
5531 &this_controller->scu_registers->peg0.viit[index]
5539 this_controller,
5540 &this_controller->port_agent
5548 scic_sds_controller_get_base_state_machine(this_controller),
5555 scic_sds_controller_release_resource(this_controller);
5606 SCIC_SDS_CONTROLLER_T * this_controller;
5608 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5611 result = scic_sds_controller_validate_memory_descriptor_table(this_controller);
5616 scic_sds_controller_ram_initialization(this_controller);
5622 sci_pool_initialize(this_controller->tci_pool);
5623 for (index = 0; index < this_controller->task_context_entries; index++)
5625 sci_pool_put(this_controller->tci_pool, index);
5630 &this_controller->available_remote_nodes,
5631 this_controller->remote_node_entries
5642 scic_sds_controller_enable_port_task_scheduler(this_controller);
5645 scic_sds_controller_assign_task_entries(this_controller);
5648 scic_sds_controller_initialize_completion_queue(this_controller);
5651 scic_sds_controller_initialize_unsolicited_frame_queue(this_controller);
5654 result = scic_sds_controller_initialize_phy_startup(this_controller);
5660 (index < this_controller->logical_port_entries) && (result == SCI_SUCCESS);
5664 result = this_controller->port_table[index].
5665 state_handlers->parent.start_handler(&this_controller->port_table[index].parent);
5670 scic_sds_controller_start_next_phy(this_controller);
5674 scic_cb_timer_start(controller, this_controller->timeout_timer, timeout);
5677 scic_sds_controller_get_base_state_machine(this_controller),
5705 SCIC_SDS_CONTROLLER_T *this_controller,
5710 scic_sds_controller_phy_timer_stop(this_controller);
5712 this_controller->port_agent.link_up_handler(
5713 this_controller, &this_controller->port_agent, port, phy
5717 scic_sds_controller_start_next_phy(this_controller);
5734 SCIC_SDS_CONTROLLER_T *this_controller,
5739 this_controller->port_agent.link_down_handler(
5740 this_controller, &this_controller->port_agent, port, phy
5769 SCIC_SDS_CONTROLLER_T *this_controller;
5770 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5774 scic_cb_timer_start(controller, this_controller->timeout_timer, timeout);
5777 scic_sds_controller_get_base_state_machine(this_controller),
5820 SCIC_SDS_CONTROLLER_T *this_controller;
5824 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5828 status = scic_sds_remote_device_start_io(this_controller, the_device, the_request);
5832 this_controller->io_request_table[
5836 this_controller,
5872 SCIC_SDS_CONTROLLER_T *this_controller;
5876 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5881 this_controller, the_device, the_request);
5886 this_controller->io_request_table[index] = SCI_INVALID_HANDLE;
5912 SCIC_SDS_CONTROLLER_T *this_controller;
5916 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
5918 this_controller->io_request_table[
5922 this_controller,
5963 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)
5972 this_controller, the_device, the_request
5977 this_controller->io_request_table[
5981 this_controller,
5987 this_controller->io_request_table[
6024 SCIC_SDS_CONTROLLER_T *this_controller = (SCIC_SDS_CONTROLLER_T *)
6036 this_controller,
6061 SCIC_SDS_CONTROLLER_T *this_controller,
6066 this_controller->port_agent.link_up_handler(
6067 this_controller, &this_controller->port_agent, port, phy
6085 SCIC_SDS_CONTROLLER_T *this_controller,
6090 this_controller->port_agent.link_down_handler(
6091 this_controller, &this_controller->port_agent, port, phy
6121 SCIC_SDS_CONTROLLER_T *this_controller;
6122 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
6187 SCIC_SDS_CONTROLLER_T *this_controller;
6188 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
6191 sci_base_object_get_logger(this_controller),
6195 scic_sds_controller_get_base_state_machine(this_controller))
6217 SCIC_SDS_CONTROLLER_T *this_controller;
6218 this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
6220 if (this_controller->parent.error == SCI_CONTROLLER_FATAL_MEMORY_ERROR) {
6497 SCIC_SDS_CONTROLLER_T *this_controller;
6498 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6501 this_controller, SCI_BASE_CONTROLLER_STATE_INITIAL);
6504 &this_controller->parent.state_machine, SCI_BASE_CONTROLLER_STATE_RESET);
6523 SCIC_SDS_CONTROLLER_T *this_controller;
6524 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6527 this_controller, SCI_BASE_CONTROLLER_STATE_RESET);
6529 scic_sds_port_configuration_agent_construct(&this_controller->port_agent);
6535 &this_controller->port_table[index],
6537 this_controller
6546 &this_controller->phy_table[index],
6547 &this_controller->port_table[SCI_MAX_PORTS],
6552 this_controller->invalid_phy_mask = 0;
6555 this_controller->completion_event_entries = SCU_EVENT_COUNT;
6556 this_controller->completion_queue_entries = SCU_COMPLETION_QUEUE_COUNT;
6557 this_controller->remote_node_entries = SCI_MAX_REMOTE_DEVICES;
6558 this_controller->logical_port_entries = SCI_MAX_PORTS;
6559 this_controller->task_context_entries = SCU_IO_REQUEST_COUNT;
6560 this_controller->uf_control.buffers.count = SCU_UNSOLICITED_FRAME_COUNT;
6561 this_controller->uf_control.address_table.count= SCU_UNSOLICITED_FRAME_COUNT;
6564 scic_sds_controller_set_default_config_parameters(this_controller);
6582 SCIC_SDS_CONTROLLER_T *this_controller;
6583 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6586 this_controller, SCI_BASE_CONTROLLER_STATE_INITIALIZING);
6604 SCIC_SDS_CONTROLLER_T *this_controller;
6605 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6608 this_controller, SCI_BASE_CONTROLLER_STATE_INITIALIZED);
6626 SCIC_SDS_CONTROLLER_T *this_controller;
6627 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6630 this_controller, SCI_BASE_CONTROLLER_STATE_STARTING);
6649 SCIC_SDS_CONTROLLER_T *this_controller;
6650 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6652 scic_cb_timer_stop(object, this_controller->timeout_timer);
6657 this_controller,
6658 this_controller->phy_startup_timer
6661 this_controller->phy_startup_timer = NULL;
6680 SCIC_SDS_CONTROLLER_T *this_controller;
6681 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6684 this_controller, SCI_BASE_CONTROLLER_STATE_READY);
6689 clock_gating_unit_value = SMU_CGUCR_READ(this_controller);
6696 SMU_CGUCR_WRITE(this_controller, clock_gating_unit_value);
6700 this_controller, 0x10, 250);
6719 SCIC_SDS_CONTROLLER_T *this_controller;
6720 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6725 clock_gating_unit_value = SMU_CGUCR_READ(this_controller);
6732 SMU_CGUCR_WRITE(this_controller, clock_gating_unit_value);
6735 scic_controller_set_interrupt_coalescence(this_controller, 0, 0);
6756 SCIC_SDS_CONTROLLER_T *this_controller;
6757 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6760 this_controller, SCI_BASE_CONTROLLER_STATE_STOPPING);
6764 scic_sds_controller_stop_devices(this_controller);
6765 scic_sds_controller_stop_ports(this_controller);
6767 if (!scic_sds_controller_has_remote_devices_stopping(this_controller))
6770 &this_controller->parent.state_machine,
6791 SCIC_SDS_CONTROLLER_T *this_controller;
6792 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6794 scic_cb_timer_stop(this_controller, this_controller->timeout_timer);
6812 SCIC_SDS_CONTROLLER_T *this_controller;
6813 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6816 this_controller, SCI_BASE_CONTROLLER_STATE_STOPPED);
6820 this_controller,
6821 this_controller->timeout_timer
6823 this_controller->timeout_timer = NULL;
6826 scic_sds_controller_stop_phys(this_controller);
6829 this_controller,
6830 &this_controller->port_agent
6833 scic_cb_controller_stop_complete(this_controller, SCI_SUCCESS);
6853 SCIC_SDS_CONTROLLER_T *this_controller;
6854 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6857 sci_base_object_get_logger(this_controller),
6860 this_controller
6864 this_controller, SCI_BASE_CONTROLLER_STATE_RESETTING);
6866 scic_sds_controller_reset_hardware(this_controller);
6869 scic_sds_controller_get_base_state_machine(this_controller),
6925 SCIC_SDS_CONTROLLER_T *this_controller,
6934 abort_status = scic_sds_abort_reqests(this_controller, this_remote_device, this_port);
6940 if (this_controller->parent.error == SCI_CONTROLLER_FATAL_MEMORY_ERROR)
6941 abort_status = scic_sds_abort_reqests(this_controller, this_remote_device, this_port);
6972 SCIC_SDS_CONTROLLER_T *this_controller;
6973 this_controller= (SCIC_SDS_CONTROLLER_T *)object;
6976 this_controller, SCI_BASE_CONTROLLER_STATE_FAILED);
6978 if (this_controller->parent.error == SCI_CONTROLLER_FATAL_MEMORY_ERROR)
6979 scic_sds_terminate_all_requests(this_controller);
6981 scic_sds_controller_release_resource(this_controller);
6984 scic_cb_controller_error(this_controller,
6985 this_controller->parent.error);