dev/fb/vga.c

806 	outb(adp->va_crtc_addr, 7);
1077     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr, 12);
1078     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr + 1, 0);
1079     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr, 13);
1080     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr + 1, 0);
1314     outb(adp->va_crtc_addr, 0x13);
1315     outb(adp->va_crtc_addr + 1, count);
1338 	    outb(TSIDX, 1);
1356     outb(adp->va_crtc_addr, 0xc);		/* high */
1357     outb(adp->va_crtc_addr + 1, off >> 8);
1358     outb(adp->va_crtc_addr, 0xd);		/* low */
1359     outb(adp->va_crtc_addr + 1, off & 0xff);
1364 	outb(ATC, 0x13 | 0x20);
1365 	outb(ATC, poff);
1367 	outb(ATC, 0x20);
1371     outb(adp->va_crtc_addr, 8);
1372     outb(adp->va_crtc_addr + 1, roff);
1726 	outb(TSIDX, 0x02); buf[0] = inb(TSREG);
1727 	outb(TSIDX, 0x04); buf[1] = inb(TSREG);
1728 	outb(GDCIDX, 0x04); buf[2] = inb(GDCREG);
1729 	outb(GDCIDX, 0x05); buf[3] = inb(GDCREG);
1730 	outb(GDCIDX, 0x06); buf[4] = inb(GDCREG);
1732 	outb(ATC, 0x10); buf[5] = inb(ATC + 1);
1749     outb(ATC, 0x10); outb(ATC, buf[5] & ~0x01);
1751     outb(ATC, 0x20);				/* enable palette */
1755     outb(TSIDX, 0x00); outb(TSREG, 0x01);
1757     outb(TSIDX, 0x02); outb(TSREG, 0x04);
1758     outb(TSIDX, 0x04); outb(TSREG, 0x07);
1760     outb(TSIDX, 0x00); outb(TSREG, 0x03);
1762     outb(GDCIDX, 0x04); outb(GDCREG, 0x02);
1763     outb(GDCIDX, 0x05); outb(GDCREG, 0x00);
1764     outb(GDCIDX, 0x06); outb(GDCREG, 0x04);
1791     outb(ATC, 0x10); outb(ATC, buf[5]);
1793     outb(ATC, 0x20);				/* enable palette */
1797     outb(TSIDX, 0x00); outb(TSREG, 0x01);
1799     outb(TSIDX, 0x02); outb(TSREG, buf[0]);
1800     outb(TSIDX, 0x04); outb(TSREG, buf[1]);
1802     outb(TSIDX, 0x00); outb(TSREG, 0x03);
1804     outb(GDCIDX, 0x04); outb(GDCREG, buf[2]);
1805     outb(GDCIDX, 0x05); outb(GDCREG, buf[3]);
1807 	outb(GDCIDX, 0x06); outb(GDCREG,(buf[4] & 0x03) | 0x08);
1809 	outb(GDCIDX, 0x06); outb(GDCREG,(buf[4] & 0x03) | 0x0c);
1876 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1877 	outb(TSIDX, 0x01); val = inb(TSREG);	/* disable screen */
1878 	outb(TSIDX, 0x01); outb(TSREG, val | 0x20);
1879 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1898 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1899 	outb(TSIDX, 0x01); outb(TSREG, val & 0xdf);	/* enable screen */
1900 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1956 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1957 	outb(TSIDX, 0x01); val = inb(TSREG);	/* disable screen */
1958 	outb(TSIDX, 0x01); outb(TSREG, val | 0x20);
1959 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1978 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1979 	outb(TSIDX, 0x01); outb(TSREG, val & 0xdf);	/* enable screen */
1980 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
2011     outb(TSIDX, 0x03); outb(TSREG, cg[page]);
2038     outb(PALRADR, 0x00);
2055     outb(PALRADR, base);
2080     outb(PIXMASK, 0xff);		/* no pixelmask */
2081     outb(PALWADR, 0x00);
2084 	outb(PALDATA, palette[i] >> bits);
2086     outb(ATC, 0x20);			/* enable palette */
2099     outb(PIXMASK, 0xff);		/* no pixelmask */
2100     outb(PALWADR, base);
2103 	outb(PALDATA, r[i] >> bits);
2104 	outb(PALDATA, g[i] >> bits);
2105 	outb(PALDATA, b[i] >> bits);
2108     outb(ATC, 0x20);			/* enable palette */
2127 	outb(ATC, 0x31); outb(ATC, color & 0xff);
2130 	outb(adp->va_crtc_addr + 5, color & 0x0f); /* color select register */
2174     outb(TSIDX, 0x00); outb(TSREG, 0x01);	/* stop sequencer */
2176 	outb(TSIDX, i + 1);
2180     outb(TSIDX, 0x00); outb(TSREG, 0x03);	/* start sequencer */
2183 	outb(crtc_addr, i);
2188 	outb(ATC, i);
2192 	outb(GDCIDX, i);
2196     outb(ATC, 0x20);				/* enable palette */
2251     outb(TSIDX, 0x00); outb(TSREG, 0x01);	/* stop sequencer */
2253 	outb(TSIDX, i + 1);
2254 	outb(TSREG, buf[i + 5]);
2256     outb(MISC, buf[9]);				/* set dot-clock */
2257     outb(TSIDX, 0x00); outb(TSREG, 0x03);	/* start sequencer */
2258     outb(crtc_addr, 0x11);
2259     outb(crtc_addr + 1, inb(crtc_addr + 1) & 0x7F);
2261 	outb(crtc_addr, i);
2262 	outb(crtc_addr + 1, buf[i + 10]);
2266 	outb(ATC, i);
2267 	outb(ATC, buf[i + 35]);
2270 	outb(GDCIDX, i);
2271 	outb(GDCREG, buf[i + 55]);
2274     outb(ATC, 0x20);				/* enable palette */
2327     outb(adp->va_crtc_addr, 14);
2329     outb(adp->va_crtc_addr, 15);
2364     outb(adp->va_crtc_addr, 14);
2365     outb(adp->va_crtc_addr + 1, off >> 8);
2366     outb(adp->va_crtc_addr, 15);
2367     outb(adp->va_crtc_addr + 1, off & 0x00ff);
2398 	    outb(adp->va_crtc_addr, 10);
2399 	    outb(adp->va_crtc_addr + 1, 32);
2400 	    outb(adp->va_crtc_addr, 11);
2401 	    outb(adp->va_crtc_addr + 1, 0);
2403 	    outb(adp->va_crtc_addr, 10);
2404 	    outb(adp->va_crtc_addr + 1, celsize - base - height);
2405 	    outb(adp->va_crtc_addr, 11);
2406 	    outb(adp->va_crtc_addr + 1, celsize - base - 1);
2412 	    outb(adp->va_crtc_addr, 10);
2413 	    outb(adp->va_crtc_addr + 1, celsize);
2414 	    outb(adp->va_crtc_addr, 11);
2415 	    outb(adp->va_crtc_addr + 1, 0);
2417 	    outb(adp->va_crtc_addr, 10);
2418 	    outb(adp->va_crtc_addr + 1, celsize - base - height);
2419 	    outb(adp->va_crtc_addr, 11);
2420 	    outb(adp->va_crtc_addr + 1, celsize - base);
2447 	    outb(TSIDX, 0x01);
2449 	    outb(TSIDX, 0x01);
2450 	    outb(TSREG, val | 0x20);
2451 	    outb(adp->va_crtc_addr, 0x17);
2453 	    outb(adp->va_crtc_addr + 1, val & ~0x80);
2456 	    outb(TSIDX, 0x01);
2458 	    outb(TSIDX, 0x01);
2459 	    outb(TSREG, val | 0x20);
2462 	    outb(TSIDX, 0x01);
2464 	    outb(TSIDX, 0x01);
2465 	    outb(TSREG, val & 0xDF);
2466 	    outb(adp->va_crtc_addr, 0x17);
2468 	    outb(adp->va_crtc_addr + 1, val | 0x80);
2483 	    outb(adp->va_crtc_addr + 4, 0x25);
2486 	    outb(adp->va_crtc_addr + 4, 0x2d);
2497 	    outb(adp->va_crtc_addr + 4, 0x21);
2500 	    outb(adp->va_crtc_addr + 4, 0x29);