dev/ep/if_ep.c

409 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
424 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
425 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
434 	CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
436 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
437 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
440 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
443 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
450 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);
451 	CSR_WRITE_2(sc, EP_COMMAND, RX_ENABLE);
452 	CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
466 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
467 	CSR_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);
506 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);
526 		CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
534 		CSR_WRITE_2(sc, EP_COMMAND,
572 			CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);
606 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);	/* disable all Ints */
613 		CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));
667 					CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
681 					CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
687 						CSR_WRITE_2(sc, EP_COMMAND,
700 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);	/* ACK int Latch */
706 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
807 		CSR_WRITE_2(sc, EP_COMMAND,
811 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
829 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
833 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
843 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
853 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
869 			CSR_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);
988 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISABLE);
989 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
992 	CSR_WRITE_2(sc, EP_COMMAND, TX_DISABLE);
993 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
996 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
998 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
1001 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);
1002 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);
1003 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);
1004 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);