Lines Matching refs:phy
73 struct e1000_phy_info *phy = &hw->phy;
77 phy->ops.init_params = e1000_null_ops_generic;
78 phy->ops.acquire = e1000_null_ops_generic;
79 phy->ops.check_polarity = e1000_null_ops_generic;
80 phy->ops.check_reset_block = e1000_null_ops_generic;
81 phy->ops.commit = e1000_null_ops_generic;
82 phy->ops.force_speed_duplex = e1000_null_ops_generic;
83 phy->ops.get_cfg_done = e1000_null_ops_generic;
84 phy->ops.get_cable_length = e1000_null_ops_generic;
85 phy->ops.get_info = e1000_null_ops_generic;
86 phy->ops.set_page = e1000_null_set_page;
87 phy->ops.read_reg = e1000_null_read_reg;
88 phy->ops.read_reg_locked = e1000_null_read_reg;
89 phy->ops.read_reg_page = e1000_null_read_reg;
90 phy->ops.release = e1000_null_phy_generic;
91 phy->ops.reset = e1000_null_ops_generic;
92 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
93 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
94 phy->ops.write_reg = e1000_null_write_reg;
95 phy->ops.write_reg_locked = e1000_null_write_reg;
96 phy->ops.write_reg_page = e1000_null_write_reg;
97 phy->ops.power_up = e1000_null_phy_generic;
98 phy->ops.power_down = e1000_null_phy_generic;
99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
101 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
221 struct e1000_phy_info *phy = &hw->phy;
228 if (!phy->ops.read_reg)
232 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
236 phy->id = (u32)(phy_id << 16);
238 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
242 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
243 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
245 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
266 if (!hw->phy.ops.write_reg)
269 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
273 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
287 struct e1000_phy_info *phy = &hw->phy;
302 (phy->addr << E1000_MDIC_PHY_SHIFT) |
352 struct e1000_phy_info *phy = &hw->phy;
368 (phy->addr << E1000_MDIC_PHY_SHIFT) |
418 struct e1000_phy_info *phy = &hw->phy;
428 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
465 struct e1000_phy_info *phy = &hw->phy;
472 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
474 hw->phy.addr);
486 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
655 if (!hw->phy.ops.acquire)
658 ret_val = hw->phy.ops.acquire(hw);
665 hw->phy.ops.release(hw);
685 if (!hw->phy.ops.acquire)
688 ret_val = hw->phy.ops.acquire(hw);
695 hw->phy.ops.release(hw);
706 * already acquired. Note, this function sets phy.addr to 1 so the caller
715 hw->phy.addr = 1;
739 if (!hw->phy.ops.acquire)
742 ret_val = hw->phy.ops.acquire(hw);
756 hw->phy.ops.release(hw);
808 if (!hw->phy.ops.acquire)
811 ret_val = hw->phy.ops.acquire(hw);
825 hw->phy.ops.release(hw);
879 if (!hw->phy.ops.acquire)
882 ret_val = hw->phy.ops.acquire(hw);
898 hw->phy.ops.release(hw);
954 if (!hw->phy.ops.acquire)
957 ret_val = hw->phy.ops.acquire(hw);
970 hw->phy.ops.release(hw);
1015 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1020 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1025 switch (hw->phy.ms_type) {
1040 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1056 if (hw->phy.type == e1000_phy_82580) {
1057 ret_val = hw->phy.ops.reset(hw);
1065 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1074 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1079 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1088 switch (hw->phy.mdix) {
1099 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1115 struct e1000_phy_info *phy = &hw->phy;
1123 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1128 if (phy->type != e1000_phy_bm)
1140 switch (phy->mdix) {
1163 if (phy->disable_polarity_correction)
1167 if (phy->type == e1000_phy_bm) {
1169 if (phy->id == BME1000_E_PHY_ID_R2) {
1171 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1176 ret_val = phy->ops.commit(hw);
1186 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1190 if ((phy->type == e1000_phy_m88) &&
1191 (phy->revision < E1000_REVISION_4) &&
1192 (phy->id != BME1000_E_PHY_ID_R2)) {
1196 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1203 if ((phy->revision == E1000_REVISION_2) &&
1204 (phy->id == M88E1111_I_PHY_ID)) {
1215 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1221 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1223 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1228 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1234 ret_val = phy->ops.commit(hw);
1240 if (phy->type == e1000_phy_82578) {
1241 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1249 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1267 struct e1000_phy_info *phy = &hw->phy;
1275 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1288 switch (phy->mdix) {
1297 if (phy->id != M88E1112_E_PHY_ID) {
1315 if (phy->disable_polarity_correction)
1319 if (phy->id == M88E1543_E_PHY_ID) {
1322 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1326 ret_val = phy->ops.commit(hw);
1337 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1342 ret_val = phy->ops.commit(hw);
1364 struct e1000_phy_info *phy = &hw->phy;
1371 ret_val = hw->phy.ops.reset(hw);
1385 if (phy->type == e1000_phy_igp) {
1387 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1395 if (hw->phy.ops.set_d0_lplu_state) {
1396 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1403 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1409 switch (phy->mdix) {
1421 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1431 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1433 ret_val = phy->ops.read_reg(hw,
1440 ret_val = phy->ops.write_reg(hw,
1447 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1452 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1474 struct e1000_phy_info *phy = &hw->phy;
1481 phy->autoneg_advertised &= phy->autoneg_mask;
1484 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1488 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1490 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1513 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1516 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1522 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1528 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1534 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1540 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1544 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1603 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1609 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1610 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1627 struct e1000_phy_info *phy = &hw->phy;
1636 phy->autoneg_advertised &= phy->autoneg_mask;
1641 if (!phy->autoneg_advertised)
1642 phy->autoneg_advertised = phy->autoneg_mask;
1655 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1660 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1667 if (phy->autoneg_wait_to_complete) {
1708 ret_val = hw->phy.ops.force_speed_duplex(hw);
1744 struct e1000_phy_info *phy = &hw->phy;
1751 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1757 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1764 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1771 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1779 if (phy->autoneg_wait_to_complete) {
1780 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1810 struct e1000_phy_info *phy = &hw->phy;
1818 if (phy->type != e1000_phy_i210) {
1822 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1828 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1836 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1842 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1846 /* Reset the phy to commit changes. */
1847 ret_val = hw->phy.ops.commit(hw);
1851 if (phy->autoneg_wait_to_complete) {
1852 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1862 switch (hw->phy.id) {
1872 if (hw->phy.type != e1000_phy_m88)
1883 ret_val = phy->ops.write_reg(hw,
1901 if (hw->phy.type != e1000_phy_m88)
1904 if (hw->phy.id == I347AT4_E_PHY_ID ||
1905 hw->phy.id == M88E1340M_E_PHY_ID ||
1906 hw->phy.id == M88E1112_E_PHY_ID)
1908 if (hw->phy.id == I210_I_PHY_ID)
1910 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1911 (hw->phy.id == M88E1512_E_PHY_ID))
1913 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1917 /* Resetting the phy means we need to re-force TX_CLK in the
1922 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1929 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1934 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1949 struct e1000_phy_info *phy = &hw->phy;
1956 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1962 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1967 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1974 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1982 if (phy->autoneg_wait_to_complete) {
1983 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
2033 /* Disable autoneg on the phy */
2080 struct e1000_phy_info *phy = &hw->phy;
2086 if (!hw->phy.ops.read_reg)
2089 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2095 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2104 if (phy->smart_speed == e1000_smart_speed_on) {
2105 ret_val = phy->ops.read_reg(hw,
2112 ret_val = phy->ops.write_reg(hw,
2117 } else if (phy->smart_speed == e1000_smart_speed_off) {
2118 ret_val = phy->ops.read_reg(hw,
2125 ret_val = phy->ops.write_reg(hw,
2131 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2132 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2133 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2135 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2141 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2147 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2164 struct e1000_phy_info *phy = &hw->phy;
2170 switch (phy->type) {
2187 phy->speed_downgraded = FALSE;
2191 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2194 phy->speed_downgraded = !!(phy_data & mask);
2209 struct e1000_phy_info *phy = &hw->phy;
2215 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2218 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2236 struct e1000_phy_info *phy = &hw->phy;
2245 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2261 ret_val = phy->ops.read_reg(hw, offset, &data);
2264 phy->cable_polarity = ((data & mask)
2279 struct e1000_phy_info *phy = &hw->phy;
2287 if (phy->polarity_correction) {
2295 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2298 phy->cable_polarity = ((phy_data & mask)
2319 if (!hw->phy.ops.read_reg)
2324 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2327 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2358 if (!hw->phy.ops.read_reg)
2366 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2377 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2410 struct e1000_phy_info *phy = &hw->phy;
2416 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2426 phy->min_cable_length = e1000_m88_cable_length_table[index];
2427 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2429 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2436 struct e1000_phy_info *phy = &hw->phy;
2443 switch (hw->phy.id) {
2446 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2447 (I347AT4_PCDL + phy->addr),
2453 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2460 /* Populate the phy structure with cable length in meters */
2461 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2463 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2470 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2475 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2480 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2486 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2492 /* Populate the phy structure with cable length in meters */
2493 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2494 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2495 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2498 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2506 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2511 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2515 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2526 phy->min_cable_length = e1000_m88_cable_length_table[index];
2527 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2529 phy->cable_length = (phy->min_cable_length +
2530 phy->max_cable_length) / 2;
2533 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2559 struct e1000_phy_info *phy = &hw->phy;
2575 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2608 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2610 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2612 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2629 struct e1000_phy_info *phy = &hw->phy;
2636 if (phy->media_type != e1000_media_type_copper) {
2650 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2654 phy->polarity_correction = !!(phy_data &
2661 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2665 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2668 ret_val = hw->phy.ops.get_cable_length(hw);
2672 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2676 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2680 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2685 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2686 phy->local_rx = e1000_1000t_rx_status_undefined;
2687 phy->remote_rx = e1000_1000t_rx_status_undefined;
2704 struct e1000_phy_info *phy = &hw->phy;
2720 phy->polarity_correction = TRUE;
2726 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2730 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2734 ret_val = phy->ops.get_cable_length(hw);
2738 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2742 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2746 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2750 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2751 phy->local_rx = e1000_1000t_rx_status_undefined;
2752 phy->remote_rx = e1000_1000t_rx_status_undefined;
2762 * Populates "phy" structure with various feature states.
2766 struct e1000_phy_info *phy = &hw->phy;
2782 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2785 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2787 if (phy->polarity_correction) {
2793 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2798 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2802 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2805 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2806 phy->local_rx = e1000_1000t_rx_status_undefined;
2807 phy->remote_rx = e1000_1000t_rx_status_undefined;
2826 if (!hw->phy.ops.read_reg)
2829 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2834 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2854 struct e1000_phy_info *phy = &hw->phy;
2860 if (phy->ops.check_reset_block) {
2861 ret_val = phy->ops.check_reset_block(hw);
2866 ret_val = phy->ops.acquire(hw);
2874 usec_delay(phy->reset_delay_us);
2881 phy->ops.release(hw);
2883 return phy->ops.get_cfg_done(hw);
2914 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2916 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2918 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2920 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2922 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2924 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2926 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2928 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2930 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2932 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2934 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2936 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2938 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2940 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2942 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2944 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2946 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2948 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2950 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2952 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2954 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2956 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2958 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2960 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2962 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2964 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2968 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2970 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2974 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2976 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2978 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2980 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2987 * @phy_id: phy_id read from the phy
2989 * Returns the phy type from the id.
3064 hw->phy.id = phy_type;
3067 hw->phy.addr = phy_addr;
3072 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3092 * Returns the phy address for the page requested.
3120 ret_val = hw->phy.ops.acquire(hw);
3131 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3136 /* Page select is register 31 for phy address 1 and 22 for
3137 * phy address 2 and 3. Page select is shifted only for
3138 * phy address 1.
3140 if (hw->phy.addr == 1) {
3159 hw->phy.ops.release(hw);
3180 ret_val = hw->phy.ops.acquire(hw);
3191 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3196 /* Page select is register 31 for phy address 1 and 22 for
3197 * phy address 2 and 3. Page select is shifted only for
3198 * phy address 1.
3200 if (hw->phy.addr == 1) {
3218 hw->phy.ops.release(hw);
3239 ret_val = hw->phy.ops.acquire(hw);
3250 hw->phy.addr = 1;
3264 hw->phy.ops.release(hw);
3284 ret_val = hw->phy.ops.acquire(hw);
3295 hw->phy.addr = 1;
3310 hw->phy.ops.release(hw);
3332 /* All page select, port ctrl and wakeup registers use phy address 1 */
3333 hw->phy.addr = 1;
3498 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3500 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3516 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3518 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3539 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3544 ret_val = hw->phy.ops.acquire(hw);
3570 hw->phy.addr = phy_addr;
3584 hw->phy.ops.release(hw);
3648 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3653 ret_val = hw->phy.ops.acquire(hw);
3677 if ((hw->phy.type == e1000_phy_82578) &&
3678 (hw->phy.revision >= 1) &&
3679 (hw->phy.addr == 2) &&
3695 hw->phy.addr = phy_addr;
3710 hw->phy.ops.release(hw);
3792 /* This takes care of the difference with desktop vs mobile phy */
3793 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3797 /* All operations in this function are phy address 2 */
3798 hw->phy.addr = 2;
3837 if (hw->phy.type != e1000_phy_82578)
3841 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3846 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3860 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3866 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3880 struct e1000_phy_info *phy = &hw->phy;
3886 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3889 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3904 struct e1000_phy_info *phy = &hw->phy;
3911 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3917 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3923 if (phy->autoneg_wait_to_complete) {
3924 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3953 struct e1000_phy_info *phy = &hw->phy;
3969 phy->polarity_correction = TRUE;
3975 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3979 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3983 ret_val = hw->phy.ops.get_cable_length(hw);
3987 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3991 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3995 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3999 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4000 phy->local_rx = e1000_1000t_rx_status_undefined;
4001 phy->remote_rx = e1000_1000t_rx_status_undefined;
4016 struct e1000_phy_info *phy = &hw->phy;
4022 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4032 phy->cable_length = length;
4054 ret_val = hw->phy.ops.acquire(hw);
4064 hw->phy.ops.release(hw);
4086 ret_val = hw->phy.ops.acquire(hw);
4096 hw->phy.ops.release(hw);
4250 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");