Lines Matching refs:nvm
642 struct e1000_nvm_info *nvm = &hw->nvm;
650 nvm->type = e1000_nvm_flash_sw;
659 nvm->flash_base_addr = 0;
663 nvm->flash_bank_size = nvm_size / 2;
665 nvm->flash_bank_size /= sizeof(u16);
685 nvm->flash_base_addr = sector_base_addr
691 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
693 nvm->flash_bank_size /= 2;
695 nvm->flash_bank_size /= sizeof(u16);
698 nvm->word_size = E1000_SHADOW_RAM_WORDS;
701 for (i = 0; i < nvm->word_size; i++) {
707 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
708 nvm->ops.release = e1000_release_nvm_ich8lan;
710 nvm->ops.read = e1000_read_nvm_spt;
711 nvm->ops.update = e1000_update_nvm_checksum_spt;
713 nvm->ops.read = e1000_read_nvm_ich8lan;
714 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
716 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
717 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
718 nvm->ops.write = e1000_write_nvm_ich8lan;
1832 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
2362 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2367 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
3414 struct e1000_nvm_info *nvm = &hw->nvm;
3415 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3429 bank1_offset = nvm->flash_bank_size;
3520 struct e1000_nvm_info *nvm = &hw->nvm;
3531 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3533 DEBUGOUT("nvm parameter(s) out of bounds\n");
3538 nvm->ops.acquire(hw);
3546 act_offset = (bank) ? nvm->flash_bank_size : 0;
3592 nvm->ops.release(hw);
3613 struct e1000_nvm_info *nvm = &hw->nvm;
3622 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3624 DEBUGOUT("nvm parameter(s) out of bounds\n");
3629 nvm->ops.acquire(hw);
3637 act_offset = (bank) ? nvm->flash_bank_size : 0;
3654 nvm->ops.release(hw);
3891 hw->nvm.flash_base_addr);
3966 hw->nvm.flash_base_addr);
4033 struct e1000_nvm_info *nvm = &hw->nvm;
4039 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4041 DEBUGOUT("nvm parameter(s) out of bounds\n");
4045 nvm->ops.acquire(hw);
4052 nvm->ops.release(hw);
4070 struct e1000_nvm_info *nvm = &hw->nvm;
4082 if (nvm->type != e1000_nvm_flash_sw)
4085 nvm->ops.acquire(hw);
4098 new_bank_offset = nvm->flash_bank_size;
4104 old_bank_offset = nvm->flash_bank_size;
4202 nvm->ops.release(hw);
4208 nvm->ops.reload(hw);
4232 struct e1000_nvm_info *nvm = &hw->nvm;
4244 if (nvm->type != e1000_nvm_flash_sw)
4247 nvm->ops.acquire(hw);
4260 new_bank_offset = nvm->flash_bank_size;
4266 old_bank_offset = nvm->flash_bank_size;
4355 nvm->ops.release(hw);
4361 nvm->ops.reload(hw);
4410 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4416 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4419 ret_val = hw->nvm.ops.update(hw);
4457 hw->nvm.flash_base_addr);
4549 hw->nvm.flash_base_addr);
4713 struct e1000_nvm_info *nvm = &hw->nvm;
4718 u32 flash_bank_size = nvm->flash_bank_size * 2;
4762 flash_linear_addr = hw->nvm.flash_base_addr;
4838 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4874 ret_val = hw->nvm.ops.valid_led_default(hw, &data);