Lines Matching refs:phy
164 struct e1000_phy_info *phy = &hw->phy;
170 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
173 if (hw->phy.media_type != e1000_media_type_copper) {
174 phy->type = e1000_phy_none;
178 phy->ops.power_up = e1000_power_up_phy_copper;
179 phy->ops.power_down = e1000_power_down_phy_copper_82575;
181 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
182 phy->reset_delay_us = 100;
184 phy->ops.acquire = e1000_acquire_phy_82575;
185 phy->ops.check_reset_block = e1000_check_reset_block_generic;
186 phy->ops.commit = e1000_phy_sw_reset_generic;
187 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
188 phy->ops.release = e1000_release_phy_82575;
193 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
196 phy->ops.reset = e1000_phy_hw_reset_generic;
204 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
211 phy->ops.read_reg = e1000_read_phy_reg_82580;
212 phy->ops.write_reg = e1000_write_phy_reg_82580;
216 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
217 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
220 phy->ops.read_reg = e1000_read_phy_reg_igp;
221 phy->ops.write_reg = e1000_write_phy_reg_igp;
225 /* Set phy->phy_addr and phy->id. */
228 /* Verify phy id and set remaining function pointers */
229 switch (phy->id) {
236 phy->type = e1000_phy_m88;
237 phy->ops.check_polarity = e1000_check_polarity_m88;
238 phy->ops.get_info = e1000_get_phy_info_m88;
239 if (phy->id == I347AT4_E_PHY_ID ||
240 phy->id == M88E1112_E_PHY_ID ||
241 phy->id == M88E1340M_E_PHY_ID)
242 phy->ops.get_cable_length =
244 else if (phy->id == M88E1543_E_PHY_ID ||
245 phy->id == M88E1512_E_PHY_ID)
246 phy->ops.get_cable_length =
249 phy->ops.get_cable_length = e1000_get_cable_length_m88;
250 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
252 if (phy->id == M88E1112_E_PHY_ID) {
255 ret_val = phy->ops.write_reg(hw,
261 ret_val = phy->ops.read_reg(hw,
274 if (phy->id == M88E1512_E_PHY_ID) {
279 if (phy->id == M88E1543_E_PHY_ID) {
287 phy->type = e1000_phy_igp_3;
288 phy->ops.check_polarity = e1000_check_polarity_igp;
289 phy->ops.get_info = e1000_get_phy_info_igp;
290 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
291 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
292 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
293 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
297 phy->type = e1000_phy_82580;
298 phy->ops.check_polarity = e1000_check_polarity_82577;
299 phy->ops.force_speed_duplex =
301 phy->ops.get_cable_length = e1000_get_cable_length_82577;
302 phy->ops.get_info = e1000_get_phy_info_82577;
303 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
304 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
307 phy->type = e1000_phy_i210;
308 phy->ops.check_polarity = e1000_check_polarity_m88;
309 phy->ops.get_info = e1000_get_phy_info_m88;
310 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
311 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
312 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
313 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
469 (hw->phy.media_type == e1000_media_type_copper)
516 /* set lan id for port to determine which phy lock to use */
534 hw->phy.ops.init_params = e1000_init_phy_params_82575;
603 ret_val = hw->phy.ops.acquire(hw);
609 hw->phy.ops.release(hw);
636 ret_val = hw->phy.ops.acquire(hw);
642 hw->phy.ops.release(hw);
657 struct e1000_phy_info *phy = &hw->phy;
665 /* some i354 devices need an extra read for phy id */
673 * work. The result of this function should mean phy->phy_addr
674 * and phy->id are set correctly.
677 phy->addr = 1;
688 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
697 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
708 /* Power on sgmii phy if it is disabled */
719 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
723 phy_id, phy->addr);
732 phy->addr);
737 if (phy->addr == 8) {
738 phy->addr = 0;
760 struct e1000_phy_info *phy = &hw->phy;
771 if (!(hw->phy.ops.write_reg))
778 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
782 ret_val = hw->phy.ops.commit(hw);
786 if (phy->id == M88E1512_E_PHY_ID)
807 struct e1000_phy_info *phy = &hw->phy;
813 if (!(hw->phy.ops.read_reg))
816 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
822 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
828 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
831 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
837 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
845 if (phy->smart_speed == e1000_smart_speed_on) {
846 ret_val = phy->ops.read_reg(hw,
853 ret_val = phy->ops.write_reg(hw,
858 } else if (phy->smart_speed == e1000_smart_speed_off) {
859 ret_val = phy->ops.read_reg(hw,
866 ret_val = phy->ops.write_reg(hw,
893 struct e1000_phy_info *phy = &hw->phy;
914 if (phy->smart_speed == e1000_smart_speed_on)
916 else if (phy->smart_speed == e1000_smart_speed_off)
940 struct e1000_phy_info *phy = &hw->phy;
955 if (phy->smart_speed == e1000_smart_speed_on)
957 else if (phy->smart_speed == e1000_smart_speed_off)
959 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
960 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
961 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1073 (hw->phy.type == e1000_phy_igp_3))
1096 if (hw->phy.media_type != e1000_media_type_copper)
1120 if (hw->phy.media_type != e1000_media_type_copper) {
1154 struct e1000_phy_info *phy = &hw->phy;
1162 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1166 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1174 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1178 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1193 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1200 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1218 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1316 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1498 /* allow time for SFP cage time to power up phy */
1501 ret_val = hw->phy.ops.reset(hw);
1507 switch (hw->phy.type) {
1510 switch (hw->phy.id) {
1561 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1592 /* sgmii mode lets the phy handle forcing speed/duplex */
1702 /* Set internal phy as default */
1714 hw->phy.media_type = e1000_media_type_internal_serdes;
1717 hw->phy.media_type = e1000_media_type_copper;
1720 /* Get phy control interface type set (MDIO vs. I2C)*/
1722 hw->phy.media_type = e1000_media_type_copper;
1732 (hw->phy.media_type == e1000_media_type_unknown)) {
1737 hw->phy.media_type = e1000_media_type_internal_serdes;
1740 hw->phy.media_type = e1000_media_type_copper;
1754 if (hw->phy.media_type == e1000_media_type_copper)
1814 hw->phy.media_type = e1000_media_type_internal_serdes;
1817 hw->phy.media_type = e1000_media_type_internal_serdes;
1820 hw->phy.media_type = e1000_media_type_copper;
1822 hw->phy.media_type = e1000_media_type_unknown;
1827 hw->phy.media_type = e1000_media_type_unknown;
1857 switch (hw->phy.media_type) {
1979 struct e1000_phy_info *phy = &hw->phy;
1981 if (!(phy->ops.check_reset_block))
1985 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2051 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2296 ret_val = hw->phy.ops.acquire(hw);
2302 hw->phy.ops.release(hw);
2322 ret_val = hw->phy.ops.acquire(hw);
2328 hw->phy.ops.release(hw);
2716 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2721 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2723 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2749 struct e1000_phy_info *phy = &hw->phy;
2755 if (phy->id != M88E1512_E_PHY_ID)
2759 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2763 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2767 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2771 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2775 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2779 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2783 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2787 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2791 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2796 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2800 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2805 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2810 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2815 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2819 ret_val = phy->ops.commit(hw);
2838 struct e1000_phy_info *phy = &hw->phy;
2844 if (phy->id != M88E1543_E_PHY_ID)
2848 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2856 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2864 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2872 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2876 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2880 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2885 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2889 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2894 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2899 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2904 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2909 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2914 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2918 ret_val = phy->ops.commit(hw);
2945 (hw->phy.media_type != e1000_media_type_copper))
2995 struct e1000_phy_info *phy = &hw->phy;
3001 if ((hw->phy.media_type != e1000_media_type_copper) ||
3002 ((phy->id != M88E1543_E_PHY_ID) &&
3003 (phy->id != M88E1512_E_PHY_ID)))
3008 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3012 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3018 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3024 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3077 struct e1000_phy_info *phy = &hw->phy;
3084 if ((hw->phy.media_type != e1000_media_type_copper) ||
3085 ((phy->id != M88E1543_E_PHY_ID) &&
3086 (phy->id != M88E1512_E_PHY_ID)))