Lines Matching refs:nvm
330 struct e1000_nvm_info *nvm = &hw->nvm;
350 nvm->word_size = 1 << size;
352 nvm->opcode_bits = 8;
353 nvm->delay_usec = 1;
355 switch (nvm->override) {
357 nvm->page_size = 32;
358 nvm->address_bits = 16;
361 nvm->page_size = 8;
362 nvm->address_bits = 8;
365 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
366 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
370 if (nvm->word_size == (1 << 15))
371 nvm->page_size = 128;
373 nvm->type = e1000_nvm_eeprom_spi;
375 nvm->type = e1000_nvm_flash_hw;
379 nvm->ops.acquire = e1000_acquire_nvm_82575;
380 nvm->ops.release = e1000_release_nvm_82575;
381 if (nvm->word_size < (1 << 15))
382 nvm->ops.read = e1000_read_nvm_eerd;
384 nvm->ops.read = e1000_read_nvm_spi;
386 nvm->ops.write = e1000_write_nvm_spi;
387 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
388 nvm->ops.update = e1000_update_nvm_checksum_generic;
389 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
394 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
395 nvm->ops.update = e1000_update_nvm_checksum_82580;
399 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
400 nvm->ops.update = e1000_update_nvm_checksum_i350;
533 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
1604 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1850 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2355 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2508 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2545 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2553 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2579 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2619 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2628 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,