Lines Matching refs:ddev
282 DRM_SPINLOCK_IRQSAVE(&rdev->ddev->event_lock, flags);
286 DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags);
306 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
325 DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags);
335 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
341 DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags);
343 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
1176 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1184 drm_property_create_enum(rdev->ddev, 0,
1190 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1194 drm_mode_create_scaling_mode_property(rdev->ddev);
1198 drm_property_create_enum(rdev->ddev, 0,
1204 drm_property_create_enum(rdev->ddev, 0,
1209 drm_property_create_range(rdev->ddev, 0,
1215 drm_property_create_range(rdev->ddev, 0,
1345 drm_mode_config_init(rdev->ddev);
1348 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1351 rdev->ddev->mode_config.max_width = 16384;
1352 rdev->ddev->mode_config.max_height = 16384;
1354 rdev->ddev->mode_config.max_width = 8192;
1355 rdev->ddev->mode_config.max_height = 8192;
1357 rdev->ddev->mode_config.max_width = 4096;
1358 rdev->ddev->mode_config.max_height = 4096;
1361 rdev->ddev->mode_config.preferred_depth = 24;
1362 rdev->ddev->mode_config.prefer_shadow = 1;
1364 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1382 radeon_crtc_init(rdev->ddev, i);
1386 ret = radeon_setup_enc_conn(rdev->ddev);
1407 drm_kms_helper_poll_init(rdev->ddev);
1420 drm_kms_helper_poll_fini(rdev->ddev);
1422 drm_mode_config_cleanup(rdev->ddev);