Lines Matching defs:track
54 /* value we track */
310 static void r600_cs_track_init(struct r600_cs_track *track)
315 track->sq_config = DX9_CONSTS;
317 track->cb_color_base_last[i] = 0;
318 track->cb_color_size[i] = 0;
319 track->cb_color_size_idx[i] = 0;
320 track->cb_color_info[i] = 0;
321 track->cb_color_view[i] = 0xFFFFFFFF;
322 track->cb_color_bo[i] = NULL;
323 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
324 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
325 track->cb_color_frag_bo[i] = NULL;
326 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
327 track->cb_color_tile_bo[i] = NULL;
328 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
329 track->cb_color_mask[i] = 0xFFFFFFFF;
331 track->is_resolve = false;
332 track->nsamples = 16;
333 track->log_nsamples = 4;
334 track->cb_target_mask = 0xFFFFFFFF;
335 track->cb_shader_mask = 0xFFFFFFFF;
336 track->cb_dirty = true;
337 track->db_bo = NULL;
338 track->db_bo_mc = 0xFFFFFFFF;
340 track->db_depth_info = 7 | (1 << 25);
341 track->db_depth_view = 0xFFFFC000;
342 track->db_depth_size = 0xFFFFFFFF;
343 track->db_depth_size_idx = 0;
344 track->db_depth_control = 0xFFFFFFFF;
345 track->db_dirty = true;
346 track->htile_bo = NULL;
347 track->htile_offset = 0xFFFFFFFF;
348 track->htile_surface = 0;
351 track->vgt_strmout_size[i] = 0;
352 track->vgt_strmout_bo[i] = NULL;
353 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
354 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
356 track->streamout_dirty = true;
357 track->sx_misc_kill_all_prims = false;
362 struct r600_cs_track *track = p->track;
371 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
373 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
374 format = G_0280A0_FORMAT(track->cb_color_info[i]);
378 i, track->cb_color_info[i]);
382 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
383 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
388 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
390 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
392 array_check.group_size = track->group_size;
393 array_check.nbanks = track->nbanks;
394 array_check.npipes = track->npipes;
400 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
401 track->cb_color_info[i]);
418 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
419 track->cb_color_info[i]);
446 tmp += track->cb_color_view[i] & 0xFF;
450 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
453 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
464 (uintmax_t)track->cb_color_bo_offset[i], tmp,
465 radeon_bo_size(track->cb_color_bo[i]),
478 ib[track->cb_color_size_idx[i]] = tmp;
481 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
485 if (track->nsamples > 1) {
486 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
489 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
491 if (bytes + track->cb_color_frag_offset[i] >
492 radeon_bo_size(track->cb_color_frag_bo[i])) {
496 (uintmax_t)track->cb_color_frag_offset[i],
497 radeon_bo_size(track->cb_color_frag_bo[i]));
504 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
509 if (bytes + track->cb_color_tile_offset[i] >
510 radeon_bo_size(track->cb_color_tile_bo[i])) {
514 (uintmax_t)track->cb_color_tile_offset[i],
515 radeon_bo_size(track->cb_color_tile_bo[i]));
529 struct r600_cs_track *track = p->track;
540 if (track->db_bo == NULL) {
544 switch (G_028010_FORMAT(track->db_depth_info)) {
559 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
562 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
563 if (!track->db_depth_size_idx) {
567 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
571 track->db_depth_size, bpe, track->db_offset,
572 radeon_bo_size(track->db_bo));
575 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
577 size = radeon_bo_size(track->db_bo);
579 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
580 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
585 base_offset = track->db_bo_mc + track->db_offset;
586 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
588 array_check.group_size = track->group_size;
589 array_check.nbanks = track->nbanks;
590 array_check.npipes = track->npipes;
591 array_check.nsamples = track->nsamples;
596 G_028010_ARRAY_MODE(track->db_depth_info),
597 track->db_depth_info);
609 G_028010_ARRAY_MODE(track->db_depth_info),
610 track->db_depth_info);
630 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
631 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
632 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
633 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
636 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
637 radeon_bo_size(track->db_bo));
643 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
647 if (track->htile_bo == NULL) {
649 __func__, __LINE__, track->db_depth_info);
652 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
654 __func__, __LINE__, track->db_depth_size);
660 if (G_028D24_LINEAR(track->htile_surface)) {
664 nby = roundup(nby, track->npipes * 8);
670 switch (track->npipes) {
693 __func__, __LINE__, track->npipes);
701 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
702 size += track->htile_offset;
704 if (size > radeon_bo_size(track->htile_bo)) {
706 __func__, __LINE__, radeon_bo_size(track->htile_bo),
712 track->db_dirty = false;
718 struct r600_cs_track *track = p->track;
727 if (track->streamout_dirty && track->vgt_strmout_en) {
729 if (track->vgt_strmout_buffer_en & (1 << i)) {
730 if (track->vgt_strmout_bo[i]) {
731 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
732 (u64)track->vgt_strmout_size[i];
733 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
736 radeon_bo_size(track->vgt_strmout_bo[i]));
745 track->streamout_dirty = false;
748 if (track->sx_misc_kill_all_prims)
754 if (track->cb_dirty) {
755 tmp = track->cb_target_mask;
758 if (track->is_resolve) {
765 if (track->cb_color_bo[i] == NULL) {
767 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
776 track->cb_dirty = false;
780 if (track->db_dirty &&
781 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
782 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
783 G_028800_Z_ENABLE(track->db_depth_control))) {
1068 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1109 track->sq_config = radeon_get_ib_value(p, idx);
1112 track->db_depth_control = radeon_get_ib_value(p, idx);
1113 track->db_dirty = true;
1124 track->db_depth_info = radeon_get_ib_value(p, idx);
1126 track->db_depth_info &= C_028010_ARRAY_MODE;
1129 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1132 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1135 track->db_depth_info = radeon_get_ib_value(p, idx);
1137 track->db_dirty = true;
1140 track->db_depth_view = radeon_get_ib_value(p, idx);
1141 track->db_dirty = true;
1144 track->db_depth_size = radeon_get_ib_value(p, idx);
1145 track->db_depth_size_idx = idx;
1146 track->db_dirty = true;
1149 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1150 track->streamout_dirty = true;
1153 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1154 track->streamout_dirty = true;
1167 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1169 track->vgt_strmout_bo[tmp] = reloc->robj;
1170 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1171 track->streamout_dirty = true;
1179 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1180 track->streamout_dirty = true;
1192 track->cb_target_mask = radeon_get_ib_value(p, idx);
1193 track->cb_dirty = true;
1196 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1200 track->log_nsamples = tmp;
1201 track->nsamples = 1 << tmp;
1202 track->cb_dirty = true;
1206 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1207 track->cb_dirty = true;
1225 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1228 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1231 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1235 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1237 track->cb_dirty = true;
1248 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1249 track->cb_dirty = true;
1260 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1261 track->cb_color_size_idx[tmp] = idx;
1262 track->cb_dirty = true;
1283 if (!track->cb_color_base_last[tmp]) {
1287 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1288 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1289 ib[idx] = track->cb_color_base_last[tmp];
1296 track->cb_color_frag_bo[tmp] = reloc->robj;
1297 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1300 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1301 track->cb_dirty = true;
1314 if (!track->cb_color_base_last[tmp]) {
1318 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1319 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1320 ib[idx] = track->cb_color_base_last[tmp];
1327 track->cb_color_tile_bo[tmp] = reloc->robj;
1328 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1331 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1332 track->cb_dirty = true;
1344 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1345 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1346 track->cb_dirty = true;
1364 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1366 track->cb_color_base_last[tmp] = ib[idx];
1367 track->cb_color_bo[tmp] = reloc->robj;
1368 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1369 track->cb_dirty = true;
1378 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1380 track->db_bo = reloc->robj;
1381 track->db_bo_mc = reloc->lobj.gpu_offset;
1382 track->db_dirty = true;
1391 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1393 track->htile_bo = reloc->robj;
1394 track->db_dirty = true;
1397 track->htile_surface = radeon_get_ib_value(p, idx);
1400 track->db_dirty = true;
1473 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1559 struct r600_cs_track *track = p->track;
1599 array_check.group_size = track->group_size;
1600 array_check.nbanks = track->nbanks;
1601 array_check.npipes = track->npipes;
1713 struct r600_cs_track *track;
1721 track = (struct r600_cs_track *)p->track;
2104 if (track->sq_config & DX9_CONSTS) {
2182 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2188 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2190 (uintmax_t)offset, track->vgt_strmout_bo_offset[idx_value]);
2351 struct r600_cs_track *track;
2354 if (p->track == NULL) {
2356 track = malloc(sizeof(*track),
2358 if (track == NULL)
2360 r600_cs_track_init(track);
2362 track->npipes = p->rdev->config.r600.tiling_npipes;
2363 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2364 track->group_size = p->rdev->config.r600.tiling_group_size;
2366 track->npipes = p->rdev->config.rv770.tiling_npipes;
2367 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2368 track->group_size = p->rdev->config.rv770.tiling_group_size;
2370 p->track = track;
2375 free(p->track, DRM_MEM_DRIVER);
2376 p->track = NULL;
2391 free(p->track, DRM_MEM_DRIVER);
2392 p->track = NULL;
2396 free(p->track, DRM_MEM_DRIVER);
2397 p->track = NULL;
2407 free(p->track, DRM_MEM_DRIVER);
2408 p->track = NULL;