Lines Matching defs:ring
1422 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1432 radeon_ring_lockup_update(ring);
1436 radeon_ring_force_activity(rdev, ring);
1437 return radeon_ring_test_lockup(rdev, ring);
1444 * @ring: radeon_ring structure holding ring information
1449 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1455 radeon_ring_lockup_update(ring);
1458 /* force ring activities */
1459 radeon_ring_force_activity(rdev, ring);
1460 return radeon_ring_test_lockup(rdev, ring);
1964 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2202 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2206 r = radeon_ring_lock(rdev, ring, 7);
2208 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2211 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2212 radeon_ring_write(ring, 0x1);
2214 radeon_ring_write(ring, 0x0);
2215 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2217 radeon_ring_write(ring, 0x3);
2218 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2220 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2221 radeon_ring_write(ring, 0);
2222 radeon_ring_write(ring, 0);
2223 radeon_ring_unlock_commit(rdev, ring);
2232 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2243 /* Set ring buffer size */
2244 rb_bufsz = drm_order(ring->ring_size / 8);
2255 /* Initialize the ring buffer's read and write pointers */
2258 ring->wptr = 0;
2259 WREG32(CP_RB_WPTR, ring->wptr);
2277 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2280 ring->rptr = RREG32(CP_RB_RPTR);
2283 ring->ready = true;
2284 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2286 ring->ready = false;
2292 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2297 /* Align ring size */
2300 ring->ring_size = ring_size;
2301 ring->align_mask = 16 - 1;
2303 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2304 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2307 ring->rptr_save_reg = 0;
2314 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2316 radeon_ring_fini(rdev, ring);
2317 radeon_scratch_free(rdev, ring->rptr_save_reg);
2324 * to the 3D engine (ring buffer, IBs, etc.), but the
2347 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2355 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2360 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2377 /* Set ring buffer size in dwords */
2378 rb_bufsz = drm_order(ring->ring_size / 4);
2385 /* Initialize the ring buffer's read and write pointers */
2398 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2414 ring->wptr = 0;
2415 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2417 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2421 ring->ready = true;
2423 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2425 ring->ready = false;
2439 * Stop the async dma engine and free the ring (r6xx-evergreen).
2444 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2462 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2475 r = radeon_ring_lock(rdev, ring, 3);
2477 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2481 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2482 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2483 radeon_ring_write(ring, 0xDEADBEEF);
2484 radeon_ring_unlock_commit(rdev, ring);
2492 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2494 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2495 ring->idx, scratch, tmp);
2506 * @ring: radeon_ring structure holding ring information
2513 struct radeon_ring *ring)
2528 r = radeon_ring_lock(rdev, ring, 4);
2530 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2533 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2534 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2535 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2536 radeon_ring_write(ring, 0xDEADBEEF);
2537 radeon_ring_unlock_commit(rdev, ring);
2547 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2549 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2550 ring->idx, tmp);
2563 struct radeon_ring *ring = &rdev->ring[fence->ring];
2566 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2568 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2569 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2572 radeon_ring_write(ring, 0xFFFFFFFF);
2573 radeon_ring_write(ring, 0);
2574 radeon_ring_write(ring, 10); /* poll interval */
2576 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2577 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2578 radeon_ring_write(ring, addr & 0xffffffff);
2579 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2580 radeon_ring_write(ring, fence->seq);
2581 radeon_ring_write(ring, 0);
2584 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2585 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2588 radeon_ring_write(ring, 0xFFFFFFFF);
2589 radeon_ring_write(ring, 0);
2590 radeon_ring_write(ring, 10); /* poll interval */
2591 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2592 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2594 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2595 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2596 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2598 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2599 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2600 radeon_ring_write(ring, fence->seq);
2602 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2603 radeon_ring_write(ring, RB_INT_STAT);
2608 struct radeon_ring *ring,
2618 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2619 radeon_ring_write(ring, addr & 0xffffffff);
2620 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2628 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2633 * Add a DMA fence packet to the ring to write
2640 struct radeon_ring *ring = &rdev->ring[fence->ring];
2641 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2644 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2645 radeon_ring_write(ring, addr & 0xfffffffc);
2646 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2647 radeon_ring_write(ring, lower_32_bits(fence->seq));
2649 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2653 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2656 * @ring: radeon_ring structure holding ring information
2660 * Add a DMA semaphore packet to the ring wait on or signal
2664 struct radeon_ring *ring,
2671 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2672 radeon_ring_write(ring, addr & 0xfffffffc);
2673 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2715 struct radeon_ring *ring = &rdev->ring[ring_index];
2728 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
2735 if (radeon_fence_need_sync(*fence, ring->idx)) {
2736 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2737 ring->idx);
2738 radeon_fence_note_sync(*fence, ring->idx);
2748 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2749 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2750 radeon_ring_write(ring, src_offset & 0xfffffffc);
2751 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2757 r = radeon_fence_emit(rdev, fence, ring->idx);
2759 radeon_ring_unlock_undo(rdev, ring);
2763 radeon_ring_unlock_commit(rdev, ring);
2784 struct radeon_ring *ring;
2844 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2845 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2851 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2852 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2994 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2995 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2997 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2998 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3058 struct radeon_ring *ring = &rdev->ring[ib->ring];
3061 if (ring->rptr_save_reg) {
3062 next_rptr = ring->wptr + 3 + 4;
3063 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3064 radeon_ring_write(ring, ((ring->rptr_save_reg -
3066 radeon_ring_write(ring, next_rptr);
3068 next_rptr = ring->wptr + 5 + 4;
3069 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3070 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3071 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3072 radeon_ring_write(ring, next_rptr);
3073 radeon_ring_write(ring, 0);
3076 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3077 radeon_ring_write(ring,
3082 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3083 radeon_ring_write(ring, ib->length_dw);
3086 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3100 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3126 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3143 * @ring: radeon_ring structure holding ring information
3145 * Test a simple IB in the DMA ring (r6xx-SI).
3148 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3164 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3195 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3210 * Schedule an IB in the DMA ring (r6xx-r7xx).
3214 struct radeon_ring *ring = &rdev->ring[ib->ring];
3217 u32 next_rptr = ring->wptr + 4;
3221 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3222 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3223 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3224 radeon_ring_write(ring, next_rptr);
3227 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3230 while ((ring->wptr & 7) != 5)
3231 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3232 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3233 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3234 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3241 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3242 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3243 * writing to the ring and the GPU consuming, the GPU writes to the ring
3253 /* Align ring size */
3266 /* Allocate ring buffer */
3273 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3287 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3290 ring_ptr = &rdev->ih.ring;
3297 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3316 rdev->ih.ring = NULL;
3491 /* allocate ring */
3507 /* set dummy read address to ring address */
3514 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3837 /* When a ring buffer overflow happen start parsing interrupt
3841 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3852 * Each IV ring entry is 128 bits:
3907 /* Order reading of wptr vs. reading of IH ring data */
3916 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3917 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4042 case 176: /* CP_INT in ring buffer */
4120 * through ring buffer, this leads to corruption in rendering, see