Lines Matching defs:track
55 /* value we track */
124 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
129 track->cb_color_fmask_bo[i] = NULL;
130 track->cb_color_cmask_bo[i] = NULL;
131 track->cb_color_cmask_slice[i] = 0;
132 track->cb_color_fmask_slice[i] = 0;
136 track->cb_color_bo[i] = NULL;
137 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
138 track->cb_color_info[i] = 0;
139 track->cb_color_view[i] = 0xFFFFFFFF;
140 track->cb_color_pitch[i] = 0;
141 track->cb_color_slice[i] = 0xfffffff;
142 track->cb_color_slice_idx[i] = 0;
144 track->cb_target_mask = 0xFFFFFFFF;
145 track->cb_shader_mask = 0xFFFFFFFF;
146 track->cb_dirty = true;
148 track->db_depth_slice = 0xffffffff;
149 track->db_depth_view = 0xFFFFC000;
150 track->db_depth_size = 0xFFFFFFFF;
151 track->db_depth_control = 0xFFFFFFFF;
152 track->db_z_info = 0xFFFFFFFF;
153 track->db_z_read_offset = 0xFFFFFFFF;
154 track->db_z_write_offset = 0xFFFFFFFF;
155 track->db_z_read_bo = NULL;
156 track->db_z_write_bo = NULL;
157 track->db_s_info = 0xFFFFFFFF;
158 track->db_s_read_offset = 0xFFFFFFFF;
159 track->db_s_write_offset = 0xFFFFFFFF;
160 track->db_s_read_bo = NULL;
161 track->db_s_write_bo = NULL;
162 track->db_dirty = true;
163 track->htile_bo = NULL;
164 track->htile_offset = 0xFFFFFFFF;
165 track->htile_surface = 0;
168 track->vgt_strmout_size[i] = 0;
169 track->vgt_strmout_bo[i] = NULL;
170 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
172 track->streamout_dirty = true;
173 track->sx_misc_kill_all_prims = false;
211 struct evergreen_cs_track *track = p->track;
214 palign = MAX(64, track->group_size / surf->bpe);
216 surf->base_align = track->group_size;
233 struct evergreen_cs_track *track = p->track;
236 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
239 surf->base_align = track->group_size;
246 track->group_size, surf->bpe, surf->nsamples);
264 struct evergreen_cs_track *track = p->track;
275 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
402 struct evergreen_cs_track *track = p->track;
408 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
409 pitch = track->cb_color_pitch[id];
410 slice = track->cb_color_slice[id];
413 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
414 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
415 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
416 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
417 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
418 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
419 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
425 id, track->cb_color_info[id]);
437 __func__, __LINE__, id, track->cb_color_pitch[id],
438 track->cb_color_slice[id], track->cb_color_attrib[id],
439 track->cb_color_info[id]);
443 offset = track->cb_color_bo_offset[id] << 8;
451 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
464 bsize = radeon_bo_size(track->cb_color_bo[id]);
465 tmp = track->cb_color_bo_offset[id] << 8;
479 ib[track->cb_color_slice_idx[id]] = slice;
488 track->cb_color_bo_offset[id] << 8, mslice,
489 radeon_bo_size(track->cb_color_bo[id]), slice);
505 struct evergreen_cs_track *track = p->track;
508 if (track->htile_bo == NULL) {
510 __func__, __LINE__, track->db_z_info);
514 if (G_028ABC_LINEAR(track->htile_surface)) {
518 nby = roundup(nby, track->npipes * 8);
524 switch (track->npipes) {
547 __func__, __LINE__, track->npipes);
555 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
556 size += track->htile_offset;
558 if (size > radeon_bo_size(track->htile_bo)) {
560 __func__, __LINE__, radeon_bo_size(track->htile_bo),
569 struct evergreen_cs_track *track = p->track;
575 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
576 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
577 slice = track->db_depth_slice;
580 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
581 surf.format = G_028044_FORMAT(track->db_s_info);
582 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
583 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
584 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
585 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
586 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
612 __func__, __LINE__, track->db_depth_size,
613 track->db_depth_slice, track->db_s_info, track->db_z_info);
618 offset = track->db_s_read_offset << 8;
625 if (offset > radeon_bo_size(track->db_s_read_bo)) {
629 (unsigned long)track->db_s_read_offset << 8, mslice,
630 radeon_bo_size(track->db_s_read_bo));
632 __func__, __LINE__, track->db_depth_size,
633 track->db_depth_slice, track->db_s_info, track->db_z_info);
637 offset = track->db_s_write_offset << 8;
644 if (offset > radeon_bo_size(track->db_s_write_bo)) {
648 (unsigned long)track->db_s_write_offset << 8, mslice,
649 radeon_bo_size(track->db_s_write_bo));
654 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
666 struct evergreen_cs_track *track = p->track;
672 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
673 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
674 slice = track->db_depth_slice;
677 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
678 surf.format = G_028040_FORMAT(track->db_z_info);
679 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
680 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
681 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
682 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
683 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
703 __func__, __LINE__, track->db_depth_size,
704 track->db_depth_slice, track->db_z_info);
711 __func__, __LINE__, track->db_depth_size,
712 track->db_depth_slice, track->db_z_info);
716 offset = track->db_z_read_offset << 8;
723 if (offset > radeon_bo_size(track->db_z_read_bo)) {
727 (unsigned long)track->db_z_read_offset << 8, mslice,
728 radeon_bo_size(track->db_z_read_bo));
732 offset = track->db_z_write_offset << 8;
739 if (offset > radeon_bo_size(track->db_z_write_bo)) {
743 (unsigned long)track->db_z_write_offset << 8, mslice,
744 radeon_bo_size(track->db_z_write_bo));
749 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
940 struct evergreen_cs_track *track = p->track;
946 if (track->streamout_dirty && track->vgt_strmout_config) {
948 if (track->vgt_strmout_config & (1 << i)) {
949 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
955 if (track->vgt_strmout_bo[i]) {
956 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
957 (u64)track->vgt_strmout_size[i];
958 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
961 radeon_bo_size(track->vgt_strmout_bo[i]));
970 track->streamout_dirty = false;
973 if (track->sx_misc_kill_all_prims)
978 if (track->cb_dirty) {
979 tmp = track->cb_target_mask;
983 if (track->cb_color_bo[i] == NULL) {
985 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
995 track->cb_dirty = false;
998 if (track->db_dirty) {
1000 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
1001 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
1007 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
1008 G_028800_Z_ENABLE(track->db_depth_control)) {
1013 track->db_dirty = false;
1292 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1367 track->db_depth_control = radeon_get_ib_value(p, idx);
1368 track->db_dirty = true;
1385 track->db_z_info = radeon_get_ib_value(p, idx);
1394 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1396 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1403 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1410 track->db_dirty = true;
1413 track->db_s_info = radeon_get_ib_value(p, idx);
1414 track->db_dirty = true;
1417 track->db_depth_view = radeon_get_ib_value(p, idx);
1418 track->db_dirty = true;
1421 track->db_depth_size = radeon_get_ib_value(p, idx);
1422 track->db_dirty = true;
1425 track->db_depth_slice = radeon_get_ib_value(p, idx);
1426 track->db_dirty = true;
1435 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1437 track->db_z_read_bo = reloc->robj;
1438 track->db_dirty = true;
1447 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1449 track->db_z_write_bo = reloc->robj;
1450 track->db_dirty = true;
1459 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1461 track->db_s_read_bo = reloc->robj;
1462 track->db_dirty = true;
1471 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1473 track->db_s_write_bo = reloc->robj;
1474 track->db_dirty = true;
1477 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1478 track->streamout_dirty = true;
1481 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1482 track->streamout_dirty = true;
1495 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1497 track->vgt_strmout_bo[tmp] = reloc->robj;
1498 track->streamout_dirty = true;
1506 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1507 track->streamout_dirty = true;
1518 track->cb_target_mask = radeon_get_ib_value(p, idx);
1519 track->cb_dirty = true;
1522 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1523 track->cb_dirty = true;
1532 track->nsamples = 1 << tmp;
1541 track->nsamples = 1 << tmp;
1552 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1553 track->cb_dirty = true;
1560 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1561 track->cb_dirty = true;
1572 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1581 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1583 track->cb_dirty = true;
1590 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1599 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1601 track->cb_dirty = true;
1612 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1613 track->cb_dirty = true;
1620 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1621 track->cb_dirty = true;
1632 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1633 track->cb_color_slice_idx[tmp] = idx;
1634 track->cb_dirty = true;
1641 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1642 track->cb_color_slice_idx[tmp] = idx;
1643 track->cb_dirty = true;
1666 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1674 track->cb_color_attrib[tmp] = ib[idx];
1675 track->cb_dirty = true;
1694 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1702 track->cb_color_attrib[tmp] = ib[idx];
1703 track->cb_dirty = true;
1720 track->cb_color_fmask_bo[tmp] = reloc->robj;
1737 track->cb_color_cmask_bo[tmp] = reloc->robj;
1748 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1759 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1776 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1778 track->cb_color_bo[tmp] = reloc->robj;
1779 track->cb_dirty = true;
1792 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1794 track->cb_color_bo[tmp] = reloc->robj;
1795 track->cb_dirty = true;
1804 track->htile_offset = radeon_get_ib_value(p, idx);
1806 track->htile_bo = reloc->robj;
1807 track->db_dirty = true;
1811 track->htile_surface = radeon_get_ib_value(p, idx);
1814 track->db_dirty = true;
1953 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1992 struct evergreen_cs_track *track;
2000 track = (struct evergreen_cs_track *)p->track;
2510 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2760 struct evergreen_cs_track *track;
2764 if (p->track == NULL) {
2766 track = malloc(sizeof(*track), DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2767 if (track == NULL)
2769 evergreen_cs_track_init(track);
2777 track->npipes = 1;
2781 track->npipes = 2;
2784 track->npipes = 4;
2787 track->npipes = 8;
2793 track->nbanks = 4;
2797 track->nbanks = 8;
2800 track->nbanks = 16;
2806 track->group_size = 256;
2810 track->group_size = 512;
2816 track->row_size = 1;
2820 track->row_size = 2;
2823 track->row_size = 4;
2827 p->track = track;
2832 free(p->track, DRM_MEM_DRIVER);
2833 p->track = NULL;
2848 free(p->track, DRM_MEM_DRIVER);
2849 p->track = NULL;
2853 free(p->track, DRM_MEM_DRIVER);
2854 p->track = NULL;
2864 free(p->track, DRM_MEM_DRIVER);
2865 p->track = NULL;