Lines Matching refs:cacheline_size
985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1116 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1440 i965_cursor_wm_info.cacheline_size);
1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
2067 tlb_miss = display->fifo_size*display->cacheline_size -
2071 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);