Lines Matching defs:intel_crtc
934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
936 return intel_crtc->cpu_transcoder;
1068 struct intel_crtc *crtc,
1572 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1574 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581 pll = intel_crtc->pch_pll;
1590 intel_crtc->base.base.id);
1612 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1614 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1615 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1629 intel_crtc->base.base.id);
1644 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
2040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2043 int plane = intel_crtc->plane;
2108 intel_crtc->dspaddr_offset =
2112 linear_offset -= intel_crtc->dspaddr_offset;
2114 intel_crtc->dspaddr_offset = linear_offset;
2122 obj->gtt_offset + intel_crtc->dspaddr_offset);
2137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140 int plane = intel_crtc->plane;
2201 intel_crtc->dspaddr_offset =
2205 linear_offset -= intel_crtc->dspaddr_offset;
2211 obj->gtt_offset + intel_crtc->dspaddr_offset);
2274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2283 switch (intel_crtc->pipe) {
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2313 if(intel_crtc->plane > dev_priv->num_pipe) {
2315 intel_crtc->plane,
2347 intel_wait_for_vblank(dev, intel_crtc->pipe);
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
2440 struct intel_crtc *pipe_B_crtc =
2442 struct intel_crtc *pipe_C_crtc =
2465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466 int pipe = intel_crtc->pipe;
2467 int plane = intel_crtc->plane;
2488 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 int pipe = intel_crtc->pipe;
2586 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2700 int pipe = intel_crtc->pipe;
2721 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2811 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2813 struct drm_device *dev = intel_crtc->base.dev;
2815 int pipe = intel_crtc->pipe;
2823 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2852 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2854 struct drm_device *dev = intel_crtc->base.dev;
2856 int pipe = intel_crtc->pipe;
2885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2886 int pipe = intel_crtc->pipe;
3094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3095 int pipe = intel_crtc->pipe;
3115 ironlake_enable_pch_pll(intel_crtc);
3136 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3219 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3221 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3232 intel_crtc->pch_pll = NULL;
3235 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3237 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3241 pll = intel_crtc->pch_pll;
3244 intel_crtc->base.base.id, pll->pll_reg);
3250 i = intel_crtc->pipe;
3254 intel_crtc->base.base.id, pll->pll_reg);
3269 intel_crtc->base.base.id,
3281 intel_crtc->base.base.id, pll->pll_reg);
3289 intel_crtc->pch_pll = pll;
3291 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3326 int pipe = intel_crtc->pipe;
3327 int plane = intel_crtc->plane;
3333 if (intel_crtc->active)
3336 intel_crtc->active = true;
3351 ironlake_fdi_pll_enable(intel_crtc);
3400 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3419 int pipe = intel_crtc->pipe;
3420 int plane = intel_crtc->plane;
3425 if (intel_crtc->active)
3428 intel_crtc->active = true;
3440 intel_ddi_enable_pipe_clock(intel_crtc);
3487 intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496 int pipe = intel_crtc->pipe;
3497 int plane = intel_crtc->plane;
3501 if (!intel_crtc->active)
3558 intel_disable_pch_pll(intel_crtc);
3560 ironlake_fdi_pll_disable(intel_crtc);
3562 intel_crtc->active = false;
3574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576 int pipe = intel_crtc->pipe;
3577 int plane = intel_crtc->plane;
3578 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3581 if (!intel_crtc->active)
3606 intel_ddi_disable_pipe_clock(intel_crtc);
3617 intel_crtc->active = false;
3627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628 intel_put_pch_pll(intel_crtc);
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3637 intel_crtc->cpu_transcoder = (enum transcoder)intel_crtc->pipe;
3642 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3644 if (!enable && intel_crtc->overlay) {
3645 struct drm_device *dev = intel_crtc->base.dev;
3650 (void) intel_overlay_switch_off(intel_crtc->overlay);
3664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3666 int pipe = intel_crtc->pipe;
3667 int plane = intel_crtc->plane;
3671 if (intel_crtc->active)
3674 intel_crtc->active = true;
3685 intel_crtc_dpms_overlay(intel_crtc, true);
3696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 int pipe = intel_crtc->pipe;
3699 int plane = intel_crtc->plane;
3703 if (!intel_crtc->active)
3712 intel_crtc_dpms_overlay(intel_crtc, false);
3729 intel_crtc->active = false;
3743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744 int pipe = intel_crtc->pipe;
4283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284 int pipe = intel_crtc->pipe;
4301 intel_crtc->lowfreq_avail = false;
4305 intel_crtc->lowfreq_avail = true;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 int pipe = intel_crtc->pipe;
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365 int pipe = intel_crtc->pipe;
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465 int pipe = intel_crtc->pipe;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
4631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4635 struct drm_device *dev = intel_crtc->base.dev;
4637 enum pipe pipe = intel_crtc->pipe;
4638 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
4699 int plane = intel_crtc->plane;
4826 if (intel_crtc->lowfreq_avail) {
4842 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194 int pipe = intel_crtc->pipe;
5200 switch (intel_crtc->bpp) {
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5338 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5340 struct drm_device *dev = intel_crtc->base.dev;
5342 struct intel_crtc *pipe_B_crtc =
5346 intel_crtc->pipe, intel_crtc->fdi_lanes);
5347 if (intel_crtc->fdi_lanes > 4) {
5349 intel_crtc->pipe, intel_crtc->fdi_lanes);
5351 intel_crtc->fdi_lanes = 4;
5359 switch (intel_crtc->pipe) {
5364 intel_crtc->fdi_lanes > 2) {
5366 intel_crtc->pipe, intel_crtc->fdi_lanes);
5368 intel_crtc->fdi_lanes = 2;
5373 if (intel_crtc->fdi_lanes > 2)
5381 if (intel_crtc->fdi_lanes > 2) {
5383 intel_crtc->pipe, intel_crtc->fdi_lanes);
5385 intel_crtc->fdi_lanes = 2;
5419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5420 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5468 intel_crtc->bpp);
5470 intel_crtc->fdi_lanes = lane;
5474 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5483 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5487 struct drm_crtc *crtc = &intel_crtc->base;
5594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5595 int pipe = intel_crtc->pipe;
5596 int plane = intel_crtc->plane;
5639 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5649 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5658 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5665 intel_put_pch_pll(intel_crtc);
5716 if (intel_crtc->pch_pll) {
5717 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5720 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5728 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5731 intel_crtc->lowfreq_avail = false;
5732 if (intel_crtc->pch_pll) {
5734 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5735 intel_crtc->lowfreq_avail = true;
5737 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5741 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5743 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5747 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5778 int pipe = intel_crtc->pipe;
5779 int plane = intel_crtc->plane;
5809 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5811 intel_crtc->cpu_transcoder = pipe;
5820 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5842 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5856 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5864 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5871 intel_put_pch_pll(intel_crtc);
5929 intel_crtc->lowfreq_avail = false;
5931 if (intel_crtc->pch_pll) {
5932 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5935 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5943 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5946 if (intel_crtc->pch_pll) {
5948 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5949 intel_crtc->lowfreq_avail = true;
5951 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5956 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5991 int pipe = intel_crtc->pipe;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 int palreg = PALETTE(intel_crtc->pipe);
6278 if (!crtc->enabled || !intel_crtc->active)
6283 palreg = LGC_PALETTE(intel_crtc->pipe);
6287 (intel_crtc->lut_r[i] << 16) |
6288 (intel_crtc->lut_g[i] << 8) |
6289 intel_crtc->lut_b[i]);
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6301 if (intel_crtc->cursor_visible == visible)
6320 intel_crtc->cursor_visible = visible;
6327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328 int pipe = intel_crtc->pipe;
6331 if (intel_crtc->cursor_visible != visible) {
6343 intel_crtc->cursor_visible = visible;
6353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6354 int pipe = intel_crtc->pipe;
6357 if (intel_crtc->cursor_visible != visible) {
6368 intel_crtc->cursor_visible = visible;
6380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381 int pipe = intel_crtc->pipe;
6382 int x = intel_crtc->cursor_x;
6383 int y = intel_crtc->cursor_y;
6390 base = intel_crtc->cursor_addr;
6400 if (x + intel_crtc->cursor_width < 0)
6409 if (y + intel_crtc->cursor_height < 0)
6418 if (!visible && !intel_crtc->cursor_visible)
6440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6495 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6508 if (intel_crtc->cursor_bo) {
6510 if (intel_crtc->cursor_bo != obj)
6511 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6513 i915_gem_object_unpin(intel_crtc->cursor_bo);
6514 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6519 intel_crtc->cursor_addr = addr;
6520 intel_crtc->cursor_bo = obj;
6521 intel_crtc->cursor_width = width;
6522 intel_crtc->cursor_height = height;
6538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6540 intel_crtc->cursor_x = x;
6541 intel_crtc->cursor_y = y;
6552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6554 intel_crtc->lut_r[regno] = red >> 8;
6555 intel_crtc->lut_g[regno] = green >> 8;
6556 intel_crtc->lut_b[regno] = blue >> 8;
6562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6564 *red = intel_crtc->lut_r[regno] << 8;
6565 *green = intel_crtc->lut_g[regno] << 8;
6566 *blue = intel_crtc->lut_b[regno] << 8;
6573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6576 intel_crtc->lut_r[i] = red[i] >> 8;
6577 intel_crtc->lut_g[i] = green[i] >> 8;
6578 intel_crtc->lut_b[i] = blue[i] >> 8;
6697 struct intel_crtc *intel_crtc;
6758 intel_crtc = to_intel_crtc(crtc);
6794 intel_wait_for_vblank(dev, intel_crtc->pipe);
6831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6832 int pipe = intel_crtc->pipe;
6919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6951 int pipe = intel_crtc->pipe;
6981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6993 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6994 int pipe = intel_crtc->pipe;
7052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7058 work = intel_crtc->unpin_work;
7059 intel_crtc->unpin_work = NULL;
7070 free(intel_crtc, DRM_MEM_KMS);
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7102 if (intel_crtc == NULL)
7106 work = intel_crtc->unpin_work;
7119 intel_crtc->unpin_work = NULL;
7122 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7124 drm_vblank_put(dev, intel_crtc->pipe);
7130 atomic_clear_mask(1 << intel_crtc->plane,
7136 CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
7159 struct intel_crtc *intel_crtc =
7167 if (intel_crtc->unpin_work)
7168 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7172 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7176 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7203 if (intel_crtc->plane)
7210 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7215 intel_mark_page_flip_active(intel_crtc);
7231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244 if (intel_crtc->plane)
7251 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7253 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7256 intel_mark_page_flip_active(intel_crtc);
7272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7293 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7304 intel_mark_page_flip_active(intel_crtc);
7320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7334 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7336 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7342 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7345 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7348 intel_mark_page_flip_active(intel_crtc);
7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7379 switch(intel_crtc->plane) {
7401 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7404 intel_mark_page_flip_active(intel_crtc);
7430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7456 ret = drm_vblank_get(dev, intel_crtc->pipe);
7462 if (intel_crtc->unpin_work) {
7465 drm_vblank_put(dev, intel_crtc->pipe);
7470 intel_crtc->unpin_work = work;
7473 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7493 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7494 atomic_inc(&intel_crtc->unpin_work_count);
7504 CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
7509 atomic_dec(&intel_crtc->unpin_work_count);
7511 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7518 intel_crtc->unpin_work = NULL;
7521 drm_vblank_put(dev, intel_crtc->pipe);
7673 struct intel_crtc *intel_crtc;
7717 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7722 if (!intel_crtc->base.enabled)
7727 if (encoder->new_crtc == intel_crtc)
7732 *disable_pipes |= 1 << intel_crtc->pipe;
7737 intel_crtc = to_intel_crtc(crtc);
7739 *prepare_pipes |= 1 << intel_crtc->pipe;
7758 *modeset_pipes &= 1 << intel_crtc->pipe;
7759 *prepare_pipes &= 1 << intel_crtc->pipe;
7778 struct intel_crtc *intel_crtc;
7786 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7788 if (prepare_pipes & (1 << intel_crtc->pipe))
7795 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7797 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7804 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7806 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7822 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7823 list_for_each_entry((intel_crtc), \
7826 if (mask & (1 <<(intel_crtc)->pipe)) \
7831 struct intel_crtc *crtc;
7933 struct intel_crtc *intel_crtc;
7943 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7944 intel_crtc_disable(&intel_crtc->base);
7962 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7963 if (intel_crtc->base.enabled)
7964 dev_priv->display.crtc_disable(&intel_crtc->base);
7983 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7984 ret = !intel_crtc_mode_set(&intel_crtc->base,
7992 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7993 dev_priv->display.crtc_enable(&intel_crtc->base);
8349 struct intel_crtc *intel_crtc;
8352 intel_crtc = malloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), DRM_MEM_KMS, M_WAITOK | M_ZERO);
8353 if (intel_crtc == NULL)
8356 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8358 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8360 intel_crtc->lut_r[i] = i;
8361 intel_crtc->lut_g[i] = i;
8362 intel_crtc->lut_b[i] = i;
8366 intel_crtc->pipe = pipe;
8367 intel_crtc->plane = pipe;
8368 intel_crtc->cpu_transcoder = pipe;
8371 intel_crtc->plane = !pipe;
8375 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8376 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8377 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8379 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8381 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8389 struct intel_crtc *crtc;
9086 intel_check_plane_mapping(struct intel_crtc *crtc)
9104 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9253 struct intel_crtc *crtc;
9377 struct intel_crtc *intel_crtc;
9390 intel_crtc = to_intel_crtc(crtc);