Lines Matching defs:dpll
3235 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3266 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3296 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3301 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
4366 u32 dpll, mdiv, pdiv;
4374 dpll = DPLL_VGA_MODE_DIS;
4375 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4376 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4377 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4379 I915_WRITE(DPLL(pipe), dpll);
4410 dpll |= DPLL_VCO_ENABLE;
4411 I915_WRITE(DPLL(pipe), dpll);
4421 I915_WRITE(DPLL(pipe), dpll);
4466 u32 dpll;
4474 dpll = DPLL_VGA_MODE_DIS;
4477 dpll |= DPLLB_MODE_LVDS;
4479 dpll |= DPLLB_MODE_DAC_SERIAL;
4484 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4486 dpll |= DPLL_DVO_HIGH_SPEED;
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4517 dpll |= PLL_REF_INPUT_TVCLKINBC;
4520 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521 dpll |= 3;
4524 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4526 dpll |= PLL_REF_INPUT_DREFCLK;
4528 dpll |= DPLL_VCO_ENABLE;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4543 I915_WRITE(DPLL(pipe), dpll);
4565 I915_WRITE(DPLL(pipe), dpll);
4578 u32 dpll;
4582 dpll = DPLL_VGA_MODE_DIS;
4585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588 dpll |= PLL_P1_DIVIDE_BY_TWO;
4590 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 dpll |= PLL_P2_DIVIDE_BY_4;
4597 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4598 dpll |= 3;
4601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4603 dpll |= PLL_REF_INPUT_DREFCLK;
4605 dpll |= DPLL_VCO_ENABLE;
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4617 I915_WRITE(DPLL(pipe), dpll);
4628 I915_WRITE(DPLL(pipe), dpll);
5491 uint32_t dpll;
5536 dpll = 0;
5539 dpll |= DPLLB_MODE_LVDS;
5541 dpll |= DPLLB_MODE_DAC_SERIAL;
5545 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5547 dpll |= DPLL_DVO_HIGH_SPEED;
5550 dpll |= DPLL_DVO_HIGH_SPEED;
5553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5559 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5562 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5568 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5573 dpll |= PLL_REF_INPUT_TVCLKINBC;
5576 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5577 dpll |= 3;
5579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5581 dpll |= PLL_REF_INPUT_DREFCLK;
5583 return dpll;
5599 u32 dpll, fp = 0, fp2 = 0;
5649 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5658 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5717 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5728 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5782 u32 dpll = 0, fp = 0, fp2 = 0;
5856 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5864 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5932 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5943 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
6833 u32 dpll = I915_READ(DPLL(pipe));
6837 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6853 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6859 switch (dpll & DPLL_MODE_MASK) {
6861 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6865 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6870 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6884 if ((dpll & PLL_REF_INPUT_MASK) ==
6891 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6894 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6897 if (dpll & PLL_P2_DIVIDE_BY_4)
6953 int dpll;
6961 dpll = I915_READ(dpll_reg);
6962 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6967 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6968 I915_WRITE(dpll_reg, dpll);
6971 dpll = I915_READ(dpll_reg);
6972 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6996 int dpll;
7002 dpll = I915_READ(dpll_reg);
7003 dpll |= DISPLAY_RATE_SELECT_FPA1;
7004 I915_WRITE(dpll_reg, dpll);
7006 dpll = I915_READ(dpll_reg);
7007 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8909 /* 830/845 need to leave pipe A & dpll A up */