Lines Matching refs:DELAY
313 DELAY(50);
331 DELAY(10);
352 DELAY(10);
358 DELAY(10);
363 DELAY(10);
368 DELAY(10);
926 DELAY(10);
1599 DELAY(1000000);
1645 DELAY(1000000);
1692 DELAY(10); /* Wait 10 microseconds (actually 50 PCI cycles but at
1701 DELAY(200000);
1712 DELAY(1000);
1803 DELAY(200000);
1816 DELAY(1000);
1866 #define EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
1936 #define MII_EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
2289 DELAY(100);
2300 DELAY(10000);
2535 DELAY(10);
2540 DELAY(10);
2552 DELAY(10000);
2638 DELAY(10);
2644 DELAY(10);
2653 DELAY(10000);
3168 DELAY(10); /* Wait 10 microseconds (actually 50 PCI cycles but at
4719 DELAY(10); /* Wait 10 microseconds (actually 50 PCI cycles but at
4805 DELAY(11*1000);
4851 DELAY(100); /* Wait 10 microseconds (actually 50 PCI cycles but at