Lines Matching refs:phy
759 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
950 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
2248 /* Set mdio clock per phy */
2252 params->phy[phy_index].mdio_ctrl);
2545 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
2576 (params->phy[ELINK_INT_PHY].supported &
3175 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
3373 * phy has a default access mode, which could also be overridden
3375 * default phy configuration, or the nvram overrun
3415 struct elink_phy *phy,
3422 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3423 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3427 tmp = ((phy->addr << 21) | (reg << 16) | val |
3430 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3435 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3442 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3445 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3450 struct elink_phy *phy,
3458 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3459 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3463 val = ((phy->addr << 21) | (reg << 16) |
3466 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3471 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3479 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3484 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3491 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,
3498 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3501 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3504 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3505 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3508 val = ((phy->addr << 21) | (devad << 16) | reg |
3511 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3516 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3523 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3530 val = ((phy->addr << 21) | (devad << 16) |
3533 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3538 val = REG_RD(sc, phy->mdio_ctrl +
3546 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3554 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3555 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3556 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3558 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3562 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3563 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3568 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,
3575 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3578 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3581 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3582 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3586 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3589 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3594 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3601 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3607 tmp = ((phy->addr << 21) | (devad << 16) | val |
3610 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3615 tmp = REG_RD(sc, phy->mdio_ctrl +
3623 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3630 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3631 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3632 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3634 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3637 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3638 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3781 static elink_status_t elink_eee_disable(struct elink_phy *phy,
3790 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3797 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
3816 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3834 static void elink_eee_an_resolve(struct elink_phy *phy,
3843 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3844 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3994 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,
3998 elink_cl45_read(sc, phy, devad, reg, &val);
3999 elink_cl45_write(sc, phy, devad, reg, val | or_val);
4003 struct elink_phy *phy,
4007 elink_cl45_read(sc, phy, devad, reg, &val);
4008 elink_cl45_write(sc, phy, devad, reg, val & and_val);
4015 /* Probe for the phy according to the given phy_addr, and execute
4019 if (params->phy[phy_index].addr == phy_addr) {
4021 ¶ms->phy[phy_index], devad,
4032 /* Probe for the phy according to the given phy_addr, and execute
4036 if (params->phy[phy_index].addr == phy_addr) {
4038 ¶ms->phy[phy_index], devad,
4045 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,
4101 struct elink_phy *phy)
4110 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
4111 (phy->addr + ser_lane) : 0;
4114 aer_val = elink_get_warpcore_lane(phy, params);
4121 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4128 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4134 /* Internal phy section */
4170 static void elink_xgxs_specific_func(struct elink_phy *phy,
4180 phy->def_md_devad);
4199 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
4203 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
4212 switch (phy->req_flow_ctrl) {
4261 params->phy[actual_phy_idx].req_flow_ctrl =
4264 params->phy[actual_phy_idx].req_line_speed =
4267 params->phy[actual_phy_idx].speed_cap_mask =
4270 params->phy[actual_phy_idx].req_duplex =
4279 params->phy[actual_phy_idx].req_flow_ctrl,
4280 params->phy[actual_phy_idx].req_line_speed,
4281 params->phy[actual_phy_idx].speed_cap_mask);
4286 struct elink_phy *phy,
4292 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
4297 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4308 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);
4309 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
4312 static void elink_pause_resolve(struct elink_phy *phy,
4359 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
4367 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
4368 elink_cl22_read(sc, phy, 0x4, &ld_pause);
4369 elink_cl22_read(sc, phy, 0x5, &lp_pause);
4372 uint8_t lane = elink_get_warpcore_lane(phy, params);
4374 elink_cl45_read(sc, phy,
4381 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4383 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4386 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4388 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4398 elink_cl45_read(sc, phy,
4401 elink_cl45_read(sc, phy,
4410 elink_pause_resolve(phy, params, vars, pause_result);
4414 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
4420 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
4422 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
4423 elink_ext_phy_update_adv_fc(phy, params, vars);
4425 vars->flow_ctrl = phy->req_flow_ctrl;
4426 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4430 elink_ext_phy_update_adv_fc(phy, params, vars);
4440 * phy init is done purely in phy_init stage.
4463 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
4490 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4494 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4504 struct elink_phy *phy)
4529 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4537 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
4543 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4545 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4549 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
4554 uint16_t lane = elink_get_warpcore_lane(phy, params);
4555 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4557 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4561 elink_set_aer_mmd(params, phy);
4564 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
4583 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4586 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4590 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4595 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4601 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
4605 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4610 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4613 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4615 elink_set_aer_mmd(params, phy);
4620 lane = elink_get_warpcore_lane(phy, params);
4621 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4625 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4626 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4629 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4632 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4637 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4641 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4651 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4658 elink_ext_phy_set_pause(params, phy, vars);
4660 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4664 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4667 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
4668 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
4669 (phy->req_line_speed == ELINK_SPEED_20000)) {
4671 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4674 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4678 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4680 elink_set_aer_mmd(params, phy);
4682 elink_warpcore_enable_AN_KR2(phy, params, vars);
4685 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4690 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4705 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4709 elink_disable_kr2(params, vars, phy);
4713 elink_warpcore_restart_AN_KR(phy, params);
4716 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
4736 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4739 lane = elink_get_warpcore_lane(phy, params);
4741 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4744 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4747 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4750 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4753 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4756 elink_set_aer_mmd(params, phy);
4758 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4761 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4765 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4769 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4773 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4777 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4779 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4784 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
4793 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4797 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4801 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4804 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4808 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4812 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4816 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4821 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4823 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4828 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4884 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4888 lane = elink_get_warpcore_lane(phy, params);
4889 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4892 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4897 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4901 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4904 elink_warpcore_set_lpi_passthrough(phy, params);
4907 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4911 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4915 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4919 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
4925 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4929 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4932 elink_set_aer_mmd(params, phy);
4934 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
4936 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4939 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4943 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4947 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4950 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4953 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4957 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4959 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4963 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4966 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4969 elink_set_aer_mmd(params, phy);
4973 struct elink_phy *phy,
4977 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4981 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4984 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4987 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4990 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4993 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4996 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4999 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5002 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5005 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5009 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5013 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5017 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5021 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5026 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
5035 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5038 elink_warpcore_set_lpi_passthrough(phy, params);
5040 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5042 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5047 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5050 switch (phy->req_line_speed) {
5061 "Speed not supported: 0x%x\n", phy->req_line_speed);
5065 if (phy->req_duplex == DUPLEX_FULL)
5068 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5072 phy->req_line_speed);
5073 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5079 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5086 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5091 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5093 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5098 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5103 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5110 struct elink_phy *phy,
5115 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5121 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5123 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5128 static void elink_warpcore_clear_regs(struct elink_phy *phy,
5151 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5155 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
5158 lane = elink_get_warpcore_lane(phy, params);
5159 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5203 static int elink_is_sfp_module_plugged(struct elink_phy *phy,
5221 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
5227 lane = elink_get_warpcore_lane(phy, params);
5229 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
5235 static void elink_warpcore_config_runtime(struct elink_phy *phy,
5249 uint16_t lane = elink_get_warpcore_lane(phy, params);
5258 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
5268 elink_warpcore_reset_lane(sc, phy, 1);
5269 elink_warpcore_reset_lane(sc, phy, 0);
5272 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
5288 static void elink_warpcore_config_sfi(struct elink_phy *phy,
5291 uint16_t lane = elink_get_warpcore_lane(phy, params);
5293 elink_warpcore_clear_regs(phy, params, lane);
5296 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
5298 elink_warpcore_set_10G_XFI(phy, params, 0);
5301 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
5306 struct elink_phy *phy,
5322 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
5326 static void elink_warpcore_config_init(struct elink_phy *phy,
5333 uint16_t lane = elink_get_warpcore_lane(phy, params);
5341 elink_set_aer_mmd(params, phy);
5342 elink_warpcore_reset_lane(sc, phy, 1);
5345 (phy->req_line_speed &&
5346 ((phy->req_line_speed == ELINK_SPEED_100) ||
5347 (phy->req_line_speed == ELINK_SPEED_10)))) {
5350 elink_warpcore_clear_regs(phy, params, lane);
5351 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
5357 elink_warpcore_enable_AN_KR(phy, params, vars);
5360 elink_warpcore_set_10G_KR(phy, params, vars);
5365 elink_warpcore_clear_regs(phy, params, lane);
5368 elink_warpcore_set_10G_XFI(phy, params, 1);
5377 elink_warpcore_set_sgmii_speed(phy,
5392 if (elink_is_sfp_module_plugged(phy, params))
5393 elink_sfp_module_detection(phy, params);
5396 phy, 1);
5399 elink_warpcore_config_sfi(phy, params);
5408 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5411 elink_sfp_module_detection(phy, params);
5415 elink_warpcore_enable_AN_KR(phy, params, vars);
5418 elink_warpcore_set_20G_force_KR2(phy, params);
5430 elink_warpcore_reset_lane(sc, phy, 0);
5434 static void elink_warpcore_link_reset(struct elink_phy *phy,
5439 elink_sfp_e3_set_transmitter(params, phy, 0);
5441 elink_set_aer_mmd(params, phy);
5443 elink_warpcore_reset_lane(sc, phy, 1);
5447 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5450 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5454 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5457 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5461 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5463 lane = elink_get_warpcore_lane(phy, params);
5465 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5468 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5470 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5473 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5477 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
5482 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5485 elink_set_aer_mmd(params, phy);
5489 static void elink_set_warpcore_loopback(struct elink_phy *phy,
5496 params->loopback_mode, phy->req_line_speed);
5498 if (phy->req_line_speed < ELINK_SPEED_10000 ||
5499 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5503 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5506 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5510 lane = elink_get_warpcore_lane(phy, params);
5511 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5514 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5516 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5521 elink_set_aer_mmd(params, phy);
5524 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5527 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5543 ELINK_DEBUG_P0(sc, "phy link up\n");
5624 ELINK_DEBUG_P0(sc, "phy link down\n");
5672 params->phy[ELINK_INT_PHY].media_type =
5675 params->phy[ELINK_EXT_PHY1].media_type =
5678 params->phy[ELINK_EXT_PHY2].media_type =
5709 struct elink_phy *phy)
5718 CL22_RD_OVER_CL45(sc, phy,
5723 CL22_WR_OVER_CL45(sc, phy,
5730 struct elink_phy *phy,
5736 CL22_RD_OVER_CL45(sc, phy,
5741 CL22_WR_OVER_CL45(sc, phy,
5754 CL22_RD_OVER_CL45(sc, phy,
5774 struct elink_phy *phy)
5790 CL22_WR_OVER_CL45(sc, phy,
5797 CL22_WR_OVER_CL45(sc, phy,
5803 CL22_WR_OVER_CL45(sc, phy,
5809 CL22_WR_OVER_CL45(sc, phy,
5815 static void elink_set_parallel_detection(struct elink_phy *phy,
5820 CL22_RD_OVER_CL45(sc, phy,
5824 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5828 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5829 phy->speed_cap_mask, control2);
5830 CL22_WR_OVER_CL45(sc, phy,
5835 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5836 (phy->speed_cap_mask &
5840 CL22_WR_OVER_CL45(sc, phy,
5845 CL22_RD_OVER_CL45(sc, phy,
5854 CL22_WR_OVER_CL45(sc, phy,
5860 CL22_WR_OVER_CL45(sc, phy,
5868 static void elink_set_autoneg(struct elink_phy *phy,
5877 CL22_RD_OVER_CL45(sc, phy,
5888 CL22_WR_OVER_CL45(sc, phy,
5894 CL22_RD_OVER_CL45(sc, phy,
5905 CL22_WR_OVER_CL45(sc, phy,
5910 CL22_RD_OVER_CL45(sc, phy,
5923 CL22_WR_OVER_CL45(sc, phy,
5930 CL22_WR_OVER_CL45(sc, phy,
5936 CL22_WR_OVER_CL45(sc, phy,
5944 CL22_RD_OVER_CL45(sc, phy,
5948 if (phy->speed_cap_mask &
5951 if (phy->speed_cap_mask &
5955 CL22_WR_OVER_CL45(sc, phy,
5966 CL22_WR_OVER_CL45(sc, phy,
5972 static void elink_program_serdes(struct elink_phy *phy,
5980 CL22_RD_OVER_CL45(sc, phy,
5986 if (phy->req_duplex == DUPLEX_FULL)
5988 CL22_WR_OVER_CL45(sc, phy,
5995 CL22_RD_OVER_CL45(sc, phy,
6015 CL22_WR_OVER_CL45(sc, phy,
6021 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
6028 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
6030 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6032 CL22_WR_OVER_CL45(sc, phy,
6036 CL22_WR_OVER_CL45(sc, phy,
6041 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
6049 CL22_WR_OVER_CL45(sc, phy,
6052 CL22_RD_OVER_CL45(sc, phy,
6057 CL22_WR_OVER_CL45(sc, phy,
6062 static void elink_restart_autoneg(struct elink_phy *phy,
6073 CL22_RD_OVER_CL45(sc, phy,
6078 CL22_WR_OVER_CL45(sc, phy,
6086 CL22_RD_OVER_CL45(sc, phy,
6093 CL22_WR_OVER_CL45(sc, phy,
6102 static void elink_initialize_sgmii_process(struct elink_phy *phy,
6111 CL22_RD_OVER_CL45(sc, phy,
6120 CL22_WR_OVER_CL45(sc, phy,
6130 CL22_RD_OVER_CL45(sc, phy,
6158 if (phy->req_duplex == DUPLEX_FULL)
6161 CL22_WR_OVER_CL45(sc, phy,
6168 elink_restart_autoneg(phy, params, 0);
6174 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
6179 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6181 CL22_RD_OVER_CL45(sc, phy,
6185 CL22_RD_OVER_CL45(sc, phy,
6195 CL22_RD_OVER_CL45(sc, phy,
6208 static void elink_update_adv_fc(struct elink_phy *phy,
6223 CL22_RD_OVER_CL45(sc, phy,
6227 CL22_RD_OVER_CL45(sc, phy,
6237 CL22_RD_OVER_CL45(sc, phy,
6241 CL22_RD_OVER_CL45(sc, phy,
6251 elink_pause_resolve(phy, params, vars, pause_result);
6255 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
6264 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
6266 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6267 elink_update_adv_fc(phy, params, vars, gp_status);
6269 vars->flow_ctrl = phy->req_flow_ctrl;
6270 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6274 if (elink_direct_parallel_detect_used(phy, params)) {
6278 elink_update_adv_fc(phy, params, vars, gp_status);
6283 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
6290 CL22_RD_OVER_CL45(sc, phy,
6298 CL22_WR_OVER_CL45(sc, phy,
6305 CL22_RD_OVER_CL45(sc, phy,
6321 CL22_RD_OVER_CL45(sc, phy,
6342 CL22_WR_OVER_CL45(sc, phy,
6347 elink_restart_autoneg(phy, params, 0);
6351 static void elink_xgxs_an_resolve(struct elink_phy *phy,
6360 if (elink_direct_parallel_detect_used(phy, params))
6364 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
6372 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6375 ELINK_DEBUG_P0(sc, "phy link up\n");
6442 ELINK_DEBUG_P0(sc, "phy link down\n");
6457 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
6467 CL22_RD_OVER_CL45(sc, phy,
6473 ELINK_DEBUG_P1(sc, "duplex status read from phy is = %x\n",
6476 ELINK_DEBUG_P1(sc, "phy status does not allow interface to be FULL_DUPLEX : %x\n",
6486 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
6494 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
6495 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6496 elink_xgxs_an_resolve(phy, params, vars,
6500 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
6503 elink_check_fallback_to_cl37(phy, params);
6512 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
6523 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
6539 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
6547 lane = elink_get_warpcore_lane(phy, params);
6550 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
6551 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6553 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6558 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
6559 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
6561 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6563 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6569 elink_ext_phy_resolve_fc(phy, params, vars);
6571 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6580 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
6582 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6584 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6592 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
6594 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6602 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6611 elink_ext_phy_resolve_fc(phy, params, vars);
6623 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6635 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6651 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6654 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6665 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
6669 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
6670 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
6680 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6686 CL22_RD_OVER_CL45(sc, phy,
6700 CL22_RD_OVER_CL45(sc, phy,
6709 CL22_WR_OVER_CL45(sc, phy,
6763 static void elink_set_preemphasis(struct elink_phy *phy,
6772 CL22_WR_OVER_CL45(sc, phy,
6775 phy->rx_preemphasis[i]);
6780 CL22_WR_OVER_CL45(sc, phy,
6783 phy->tx_preemphasis[i]);
6787 static void elink_xgxs_config_init(struct elink_phy *phy,
6798 elink_set_preemphasis(phy, params);
6807 elink_set_autoneg(phy, params, vars, 0);
6810 elink_program_serdes(phy, params, vars);
6816 elink_set_brcm_cl37_advertisement(phy, params);
6819 elink_set_ieee_aneg_advertisement(phy, params,
6823 elink_set_autoneg(phy, params, vars, enable_cl73);
6826 elink_restart_autoneg(phy, params, enable_cl73);
6832 elink_initialize_sgmii_process(phy, params, vars);
6836 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
6842 if ((phy->req_line_speed &&
6843 ((phy->req_line_speed == ELINK_SPEED_100) ||
6844 (phy->req_line_speed == ELINK_SPEED_10))) ||
6845 (!phy->req_line_speed &&
6846 (phy->speed_cap_mask >=
6848 (phy->speed_cap_mask <
6850 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6855 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6856 elink_set_aer_mmd(params, phy);
6857 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6858 elink_set_master_ln(params, phy);
6860 rc = elink_reset_unicore(params, phy, 0);
6865 elink_set_aer_mmd(params, phy);
6867 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6868 elink_set_master_ln(params, phy);
6869 elink_set_swap_lanes(params, phy);
6876 struct elink_phy *phy,
6882 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6883 elink_cl22_read(sc, phy,
6886 elink_cl45_read(sc, phy,
6918 params->phy[ELINK_INT_PHY].type !=
6921 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6928 params->phy[ELINK_INT_PHY].type !=
6931 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6955 /* Disable the MI INT ( external phy int ) by writing 1 to the
7082 /* Extract first external phy*/
7084 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
7086 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
7087 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
7093 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
7094 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
7095 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
7099 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
7110 static void elink_set_xgxs_loopback(struct elink_phy *phy,
7116 if (phy->req_line_speed != ELINK_SPEED_1000) {
7130 elink_cl45_write(sc, phy,
7136 elink_cl45_write(sc, phy,
7143 elink_set_aer_mmd(params, phy);
7153 elink_cl45_read(sc, phy, 5,
7157 elink_cl45_write(sc, phy, 5,
7180 if (params->phy[phy_idx].set_link_led) {
7181 params->phy[phy_idx].set_link_led(
7182 ¶ms->phy[phy_idx], params, mode);
7199 if (params->phy[ELINK_EXT_PHY1].type ==
7217 if (((params->phy[ELINK_EXT_PHY1].type ==
7219 (params->phy[ELINK_EXT_PHY1].type ==
7255 } else if ((params->phy[ELINK_EXT_PHY1].type ==
7325 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
7362 /* Link is up only if both local phy and external phy are up */
7375 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
7376 ¶ms->phy[ELINK_EXT_PHY1],
7382 serdes_phy_type = ((params->phy[phy_index].media_type ==
7384 (params->phy[phy_index].media_type ==
7386 (params->phy[phy_index].media_type ==
7388 (params->phy[phy_index].media_type ==
7393 if (params->phy[phy_index].read_status) {
7395 params->phy[phy_index].read_status(
7396 ¶ms->phy[phy_index],
7412 /* In case of external phy existence, the line speed would be the
7413 * line speed linked up by the external phy. In case it is direct
7417 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7419 /* Initialize the internal phy in case this is a direct board
7420 * (no external phys), or this board has external phy which requires
7424 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
7425 /* init ext phy and enable link state int */
7430 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7432 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
7436 elink_set_parallel_detection(phy, params);
7437 if (params->phy[ELINK_INT_PHY].config_init)
7438 params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
7444 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7446 /* Init external phy*/
7448 if (params->phy[ELINK_INT_PHY].supported &
7454 /* No need to initialize second phy in case of first
7455 * phy only selection. In case of second phy, we do
7456 * need to initialize the first phy, since they are
7459 if (params->phy[phy_index].supported &
7467 "Not initializing second phy\n");
7470 params->phy[phy_index].config_init(
7471 ¶ms->phy[phy_index],
7475 /* Reset the interrupt indication after phy was initialized */
7485 static void elink_int_link_reset(struct elink_phy *phy,
7493 static void elink_common_ext_link_reset(struct elink_phy *phy,
7641 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
7674 * phy (XGXS) need to up as well as the external link of the
7675 * phy (PHY_EXT1)
7677 * external phy needs to be up, and at least one of the 2
7678 * external phy link must be up.
7707 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
7730 * vars argument is used since each phy may have different link/
7735 struct elink_phy *phy = ¶ms->phy[phy_index];
7736 if (!phy->read_status)
7738 /* Read link status and params of this ext phy */
7739 cur_link_up = phy->read_status(phy, params,
7742 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n",
7745 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n",
7759 * Its not clear how to reset the link on the second phy
7772 * - FIRST_PHY means that second phy wasn't initialized,
7774 * - SECOND_PHY means that first phy should not be able
7788 * Read the status of the internal phy. In case of
7791 * external phy
7793 if (params->phy[ELINK_INT_PHY].read_status)
7794 params->phy[ELINK_INT_PHY].read_status(
7795 ¶ms->phy[ELINK_INT_PHY],
7799 * Otherwise, the active external phy flow control result is set
7801 * speed is different between the internal phy and external phy.
7807 * the external phy.
7815 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
7818 params->phy[ELINK_EXT_PHY2].phy_specific_func(
7819 ¶ms->phy[ELINK_EXT_PHY2],
7826 if (params->phy[active_external_phy].supported &
7834 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n",
7853 if (params->phy[phy_index].flags &
7890 /* In case external phy link is up, and internal link is down
7901 params->phy[ELINK_EXT_PHY1].flags &
7903 if (!(params->phy[ELINK_EXT_PHY1].flags &
7912 if (params->phy[ELINK_INT_PHY].config_init)
7913 params->phy[ELINK_INT_PHY].config_init(
7914 ¶ms->phy[ELINK_INT_PHY], params,
7918 /* Link is up only if both local phy and external phy (in case of
7927 ELINK_DEBUG_P0(sc, "local phy and external phy are up\n");
7929 ELINK_DEBUG_P0(sc, "either local phy or external phy or both are down\n");
7976 struct elink_phy *phy,
7981 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7983 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7986 phy->ver_addr);
7990 struct elink_phy *phy,
7994 elink_cl45_read(sc, phy,
7997 elink_cl45_read(sc, phy,
8009 static void elink_8073_resolve_fc(struct elink_phy *phy,
8014 if (phy->req_line_speed == ELINK_SPEED_10 ||
8015 phy->req_line_speed == ELINK_SPEED_100) {
8016 vars->flow_ctrl = phy->req_flow_ctrl;
8020 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
8025 elink_cl45_read(sc, phy,
8029 elink_cl45_read(sc, phy,
8037 elink_pause_resolve(phy, params, vars, pause_result);
8043 struct elink_phy *phy,
8052 elink_cl45_write(sc, phy,
8058 elink_cl45_write(sc, phy,
8063 elink_cl45_write(sc, phy,
8068 elink_cl45_write(sc, phy,
8074 elink_cl45_write(sc, phy,
8094 elink_cl45_read(sc, phy,
8097 elink_cl45_read(sc, phy,
8103 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
8107 elink_cl45_write(sc, phy,
8110 elink_save_bcm_spirom_ver(sc, phy, port);
8123 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)
8129 elink_cl45_read(sc, phy,
8138 elink_cl45_read(sc, phy,
8149 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)
8153 elink_cl45_read(sc, phy,
8168 elink_cl45_read(sc, phy,
8187 elink_cl45_read(sc, phy,
8205 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)
8208 elink_cl45_write(sc, phy,
8210 elink_cl45_write(sc, phy,
8212 elink_cl45_write(sc, phy,
8214 elink_cl45_write(sc, phy,
8219 struct elink_phy *phy,
8224 elink_cl45_read(sc, phy,
8229 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8246 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
8248 elink_cl45_write(sc, phy,
8253 static void elink_8073_specific_func(struct elink_phy *phy,
8261 elink_cl45_write(sc, phy,
8263 elink_cl45_write(sc, phy,
8269 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
8289 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
8290 elink_8073_set_pause_cl37(params, phy, vars);
8292 elink_cl45_read(sc, phy,
8295 elink_cl45_read(sc, phy,
8305 elink_cl45_read(sc, phy,
8308 elink_cl45_write(sc, phy,
8321 elink_cl45_read(sc, phy,
8324 elink_cl45_write(sc, phy,
8330 elink_807x_force_10G(sc, phy);
8334 elink_cl45_write(sc, phy,
8337 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
8338 if (phy->req_line_speed == ELINK_SPEED_10000) {
8340 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
8349 if (phy->speed_cap_mask &
8354 if (phy->speed_cap_mask &
8361 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8362 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8364 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
8365 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
8366 (phy->req_line_speed == ELINK_SPEED_2500)) {
8369 elink_cl45_read(sc, phy,
8382 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8385 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8386 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8387 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
8391 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8397 if (elink_8073_is_snr_needed(sc, phy))
8398 elink_cl45_write(sc, phy,
8403 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8405 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8407 elink_ext_phy_set_pause(params, phy, vars);
8411 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8417 static uint8_t elink_8073_read_status(struct elink_phy *phy,
8427 elink_cl45_read(sc, phy,
8433 elink_cl45_read(sc, phy,
8435 elink_cl45_read(sc, phy,
8439 elink_cl45_read(sc, phy,
8443 elink_cl45_read(sc, phy,
8449 elink_cl45_read(sc, phy,
8453 elink_cl45_read(sc, phy,
8455 elink_cl45_read(sc, phy,
8461 ((phy->req_line_speed != ELINK_SPEED_10000))) {
8462 if (elink_8073_xaui_wa(sc, phy) != 0)
8465 elink_cl45_read(sc, phy,
8467 elink_cl45_read(sc, phy,
8471 elink_cl45_read(sc, phy,
8473 elink_cl45_read(sc, phy,
8479 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
8484 elink_cl45_write(sc, phy,
8489 elink_cl45_write(sc, phy,
8493 elink_cl45_read(sc, phy,
8524 elink_cl45_read(sc, phy,
8537 elink_cl45_write(sc, phy,
8542 elink_ext_phy_10G_an_resolve(sc, phy, vars);
8543 elink_8073_resolve_fc(phy, params, vars);
8548 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
8562 static void elink_8073_link_reset(struct elink_phy *phy,
8581 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
8592 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8593 elink_wait_reset_complete(sc, phy, params);
8595 elink_cl45_write(sc, phy,
8597 elink_cl45_write(sc, phy,
8599 elink_cl45_write(sc, phy,
8601 elink_cl45_write(sc, phy,
8608 static uint8_t elink_8705_read_status(struct elink_phy *phy,
8616 elink_cl45_read(sc, phy,
8620 elink_cl45_read(sc, phy,
8624 elink_cl45_read(sc, phy,
8627 elink_cl45_read(sc, phy,
8629 elink_cl45_read(sc, phy,
8636 elink_ext_phy_resolve_fc(phy, params, vars);
8645 struct elink_phy *phy,
8662 elink_cl45_write(sc, phy,
8682 struct elink_phy *phy,
8700 elink_cl45_read(sc, phy,
8710 elink_cl45_write(sc, phy,
8739 struct elink_phy *phy,
8745 elink_sfp_e3_set_transmitter(params, phy, tx_en);
8747 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
8750 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
8764 elink_cl45_write(sc, phy,
8769 elink_cl45_write(sc, phy,
8774 elink_cl45_write(sc, phy,
8780 elink_cl45_read(sc, phy,
8799 elink_cl45_read(sc, phy,
8806 elink_cl45_read(sc, phy,
8838 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
8881 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
8899 elink_cl45_write(sc, phy,
8905 elink_cl45_read(sc, phy,
8911 elink_cl45_write(sc, phy,
8917 elink_cl45_write(sc, phy,
8922 elink_cl45_write(sc, phy,
8928 elink_cl45_write(sc, phy,
8939 elink_cl45_read(sc, phy,
8958 elink_cl45_read(sc, phy,
8965 elink_cl45_read(sc, phy,
8976 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
8990 switch (phy->type) {
9008 rc = read_func(phy, params, dev_addr, addr, xfer_size,
9017 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
9025 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
9027 if (elink_read_sfp_module_eeprom(phy,
9044 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
9052 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9086 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
9087 if (phy->req_line_speed != ELINK_SPEED_1000) {
9089 phy->req_line_speed = ELINK_SPEED_1000;
9105 elink_sfp_set_transmitter(params, phy, 0);
9107 elink_sfp_set_transmitter(params, phy, 1);
9113 if (params->phy[idx].type == phy->type) {
9118 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
9119 phy->req_line_speed = params->req_line_speed[cfg_idx];
9133 if (&(params->phy[phy_idx]) == phy) {
9136 media_types |= ((phy->media_type &
9145 if (elink_read_sfp_module_eeprom(phy,
9166 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
9174 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
9186 /* Use specific phy request */
9190 /* Use first phy request only in case of non-dual media*/
9204 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
9212 if (elink_read_sfp_module_eeprom(phy,
9221 if (elink_read_sfp_module_eeprom(phy,
9236 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
9240 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
9253 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9255 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
9258 rc = elink_read_sfp_module_eeprom(phy, params,
9269 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
9275 struct elink_phy *phy,
9290 if (phy->flags & ELINK_FLAGS_NOC)
9300 elink_cl45_write(sc, phy,
9307 struct elink_phy *phy,
9312 elink_cl45_read(sc, phy,
9321 elink_cl45_write(sc, phy,
9335 elink_cl45_write(sc, phy,
9339 elink_cl45_write(sc, phy,
9343 elink_cl45_write(sc, phy,
9347 elink_cl45_write(sc, phy,
9356 struct elink_phy *phy,
9361 elink_cl45_read(sc, phy,
9366 elink_cl45_write(sc, phy,
9371 elink_cl45_read(sc, phy,
9376 elink_cl45_write(sc, phy,
9381 elink_cl45_write(sc, phy,
9389 static void elink_8727_specific_func(struct elink_phy *phy,
9397 elink_sfp_set_transmitter(params, phy, 0);
9400 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
9401 elink_sfp_set_transmitter(params, phy, 1);
9404 elink_cl45_write(sc, phy,
9407 elink_cl45_write(sc, phy,
9410 elink_cl45_write(sc, phy,
9413 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9417 if (phy->flags & ELINK_FLAGS_NOC)
9422 if (!(phy->flags & ELINK_FLAGS_NOC))
9424 elink_cl45_write(sc, phy,
9497 static void elink_warpcore_hw_reset(struct elink_phy *phy,
9512 struct elink_phy *phy,
9518 switch (phy->type) {
9521 elink_8727_power_module(params->sc, phy, power);
9531 struct elink_phy *phy,
9538 uint8_t lane = elink_get_warpcore_lane(phy, params);
9540 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9558 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
9561 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9565 elink_warpcore_reset_lane(sc, phy, 1);
9566 elink_warpcore_reset_lane(sc, phy, 0);
9571 struct elink_phy *phy,
9574 switch (phy->type) {
9576 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
9580 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
9583 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
9588 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
9599 elink_sfp_set_transmitter(params, phy, 1);
9603 elink_power_sfp_module(params, phy, 1);
9604 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
9607 } else if (elink_verify_sfp_module(phy, params) != 0) {
9619 elink_power_sfp_module(params, phy, 0);
9630 elink_set_limiting_mode(params, phy, edc_mode);
9638 elink_sfp_set_transmitter(params, phy, 0);
9646 struct elink_phy *phy;
9650 phy = ¶ms->phy[ELINK_INT_PHY];
9652 elink_sfp_set_transmitter(params, phy, 1);
9654 phy = ¶ms->phy[ELINK_EXT_PHY1];
9672 elink_set_aer_mmd(params, phy);
9674 elink_power_sfp_module(params, phy, 1);
9678 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
9679 elink_sfp_module_detection(phy, params);
9686 elink_cl45_read(sc, phy,
9693 elink_warpcore_reset_lane(sc, phy, 1);
9694 elink_warpcore_config_sfi(phy, params);
9695 elink_warpcore_reset_lane(sc, phy, 0);
9708 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
9716 struct elink_phy *phy,
9721 elink_cl45_read(sc, phy,
9724 elink_cl45_read(sc, phy,
9728 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9733 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9738 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
9747 elink_cl45_read(sc, phy,
9750 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
9754 elink_cl45_read(sc, phy,
9756 elink_cl45_read(sc, phy,
9760 elink_cl45_read(sc, phy,
9762 elink_cl45_read(sc, phy,
9764 elink_cl45_read(sc, phy,
9766 elink_cl45_read(sc, phy,
9780 elink_ext_phy_resolve_fc(phy, params, vars);
9786 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9788 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9800 static uint8_t elink_8706_config_init(struct elink_phy *phy,
9812 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9813 elink_wait_reset_complete(sc, phy, params);
9817 elink_cl45_read(sc, phy,
9832 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
9836 val |= (phy->rx_preemphasis[i] & 0x7);
9839 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
9843 if (phy->req_line_speed == ELINK_SPEED_10000) {
9846 elink_cl45_write(sc, phy,
9849 elink_cl45_write(sc, phy,
9853 elink_cl45_write(sc, phy,
9860 elink_cl45_write(sc, phy,
9864 elink_cl45_write(sc, phy,
9867 elink_cl45_write(sc, phy,
9870 elink_cl45_write(sc, phy,
9874 elink_cl45_write(sc, phy,
9876 elink_cl45_write(sc, phy,
9879 elink_cl45_write(sc, phy,
9883 elink_save_bcm_spirom_ver(sc, phy, params->port);
9896 elink_cl45_read(sc, phy,
9899 elink_cl45_write(sc, phy,
9906 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
9910 return elink_8706_8726_read_status(phy, params, vars);
9916 static void elink_8726_config_loopback(struct elink_phy *phy,
9921 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9924 static void elink_8726_external_rom_boot(struct elink_phy *phy,
9932 elink_cl45_write(sc, phy,
9936 elink_cl45_write(sc, phy,
9941 elink_cl45_write(sc, phy,
9945 elink_cl45_write(sc, phy,
9954 elink_cl45_write(sc, phy,
9959 elink_save_bcm_spirom_ver(sc, phy, params->port);
9962 static uint8_t elink_8726_read_status(struct elink_phy *phy,
9968 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
9970 elink_cl45_read(sc, phy,
9983 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
9990 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9991 elink_wait_reset_complete(sc, phy, params);
9993 elink_8726_external_rom_boot(phy, params);
10000 elink_sfp_module_detection(phy, params);
10002 if (phy->req_line_speed == ELINK_SPEED_1000) {
10004 elink_cl45_write(sc, phy,
10006 elink_cl45_write(sc, phy,
10008 elink_cl45_write(sc, phy,
10010 elink_cl45_write(sc, phy,
10013 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10014 (phy->speed_cap_mask &
10016 ((phy->speed_cap_mask &
10021 elink_ext_phy_set_pause(params, phy, vars);
10022 elink_cl45_write(sc, phy,
10024 elink_cl45_write(sc, phy,
10026 elink_cl45_write(sc, phy,
10028 elink_cl45_write(sc, phy,
10030 elink_cl45_write(sc, phy,
10035 elink_cl45_write(sc, phy,
10037 elink_cl45_write(sc, phy,
10042 elink_cl45_write(sc, phy,
10051 phy->tx_preemphasis[0],
10052 phy->tx_preemphasis[1]);
10053 elink_cl45_write(sc, phy,
10056 phy->tx_preemphasis[0]);
10058 elink_cl45_write(sc, phy,
10061 phy->tx_preemphasis[1]);
10068 static void elink_8726_link_reset(struct elink_phy *phy,
10074 elink_cl45_write(sc, phy,
10083 static void elink_8727_set_link_led(struct elink_phy *phy,
10091 if (!(phy->flags & ELINK_FLAGS_NOC))
10108 elink_cl45_read(sc, phy,
10114 elink_cl45_write(sc, phy,
10118 elink_cl45_read(sc, phy,
10124 elink_cl45_write(sc, phy,
10129 static void elink_8727_hw_reset(struct elink_phy *phy,
10144 static void elink_8727_config_speed(struct elink_phy *phy,
10150 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
10151 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
10153 elink_cl45_write(sc, phy,
10155 elink_cl45_write(sc, phy,
10157 elink_cl45_read(sc, phy,
10164 elink_cl45_read(sc, phy,
10168 elink_cl45_write(sc, phy,
10172 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10173 ((phy->speed_cap_mask &
10175 ((phy->speed_cap_mask &
10180 elink_cl45_write(sc, phy,
10182 elink_cl45_write(sc, phy,
10188 elink_cl45_write(sc, phy,
10191 elink_cl45_write(sc, phy,
10193 elink_cl45_write(sc, phy,
10195 elink_cl45_write(sc, phy,
10201 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
10210 elink_wait_reset_complete(sc, phy, params);
10214 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
10218 elink_cl45_read(sc, phy,
10225 if (!(phy->flags & ELINK_FLAGS_NOC))
10227 elink_cl45_write(sc, phy,
10231 elink_set_disable_pmd_transmit(params, phy, 0);
10233 elink_8727_power_module(sc, phy, 1);
10235 elink_cl45_read(sc, phy,
10238 elink_cl45_read(sc, phy,
10241 elink_8727_config_speed(phy, params);
10248 phy->tx_preemphasis[0],
10249 phy->tx_preemphasis[1]);
10250 elink_cl45_write(sc, phy,
10252 phy->tx_preemphasis[0]);
10254 elink_cl45_write(sc, phy,
10256 phy->tx_preemphasis[1]);
10270 elink_cl45_read(sc, phy,
10274 elink_cl45_write(sc, phy,
10276 elink_cl45_read(sc, phy,
10279 elink_cl45_write(sc, phy,
10287 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
10296 elink_cl45_read(sc, phy,
10304 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
10313 if (!(phy->flags & ELINK_FLAGS_NOC))
10315 elink_cl45_write(sc, phy,
10322 elink_cl45_read(sc, phy,
10338 if (!(phy->flags & ELINK_FLAGS_NOC))
10340 elink_cl45_write(sc, phy,
10349 elink_cl45_read(sc, phy,
10356 elink_sfp_set_transmitter(params, phy, 0);
10358 if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
10359 elink_sfp_module_detection(phy, params);
10364 elink_8727_config_speed(phy, params);
10372 static uint8_t elink_8727_read_status(struct elink_phy *phy,
10383 elink_cl45_read(sc, phy,
10390 elink_cl45_read(sc, phy,
10396 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
10399 elink_cl45_read(sc, phy,
10405 elink_cl45_read(sc, phy,
10411 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
10413 elink_cl45_read(sc, phy,
10432 elink_cl45_write(sc, phy,
10436 elink_cl45_read(sc, phy,
10441 elink_cl45_write(sc, phy,
10445 elink_cl45_read(sc, phy,
10448 elink_8727_power_module(params->sc, phy, 0);
10455 elink_8727_handle_mod_abs(phy, params);
10457 elink_cl45_write(sc, phy,
10462 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
10464 elink_sfp_set_transmitter(params, phy, 1);
10470 elink_cl45_read(sc, phy,
10495 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10498 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10507 elink_ext_phy_resolve_fc(phy, params, vars);
10513 (phy->req_line_speed == ELINK_SPEED_1000)) {
10514 elink_cl45_read(sc, phy,
10524 elink_cl45_write(sc, phy,
10531 static void elink_8727_link_reset(struct elink_phy *phy,
10537 elink_set_disable_pmd_transmit(params, phy, 1);
10540 elink_sfp_set_transmitter(params, phy, 0);
10542 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10549 static int elink_is_8483x_8485x(struct elink_phy *phy)
10551 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10552 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
10553 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
10556 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
10570 if (elink_is_8483x_8485x(phy)) {
10571 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10573 phy->ver_addr);
10578 elink_cl45_write(sc, phy, reg_set[i].devad,
10582 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10589 "phy fw version(1)\n");
10591 phy->ver_addr);
10597 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10598 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10599 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10601 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10607 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
10610 phy->ver_addr);
10615 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10617 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10620 phy->ver_addr);
10625 struct elink_phy *phy)
10638 elink_cl45_read(sc, phy,
10644 elink_cl45_write(sc, phy,
10649 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
10652 if (elink_is_8483x_8485x(phy))
10658 elink_cl45_read_or_write(sc, phy,
10663 static void elink_848xx_specific_func(struct elink_phy *phy,
10670 if (!elink_is_8483x_8485x(phy)) {
10672 elink_save_848xx_spirom_version(phy, sc, params->port);
10674 /* This phy uses the NIG latch mechanism since link indication
10681 elink_848xx_set_led(sc, phy);
10686 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
10693 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
10694 elink_cl45_write(sc, phy,
10698 elink_cl45_read(sc, phy,
10702 elink_ext_phy_set_pause(params, phy, vars);
10703 elink_cl45_read(sc, phy,
10707 elink_cl45_read(sc, phy,
10714 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10715 (phy->speed_cap_mask &
10717 (phy->req_line_speed == ELINK_SPEED_1000)) {
10720 if (phy->req_duplex == DUPLEX_FULL)
10726 elink_cl45_write(sc, phy,
10731 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10732 if (phy->speed_cap_mask &
10741 if (phy->speed_cap_mask &
10750 if ((phy->speed_cap_mask &
10752 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
10758 if ((phy->speed_cap_mask &
10760 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
10768 if ((phy->req_line_speed == ELINK_SPEED_100) &&
10769 (phy->supported &
10774 elink_cl45_write(sc, phy,
10781 if ((phy->req_line_speed == ELINK_SPEED_10) &&
10782 (phy->supported &
10786 elink_cl45_write(sc, phy,
10792 elink_cl45_write(sc, phy,
10796 if (phy->req_duplex == DUPLEX_FULL)
10802 if (!elink_is_8483x_8485x(phy) ||
10804 elink_cl45_write(sc, phy,
10808 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10809 (phy->speed_cap_mask &
10811 (phy->req_line_speed == ELINK_SPEED_10000)) {
10816 sc, phy,
10820 elink_cl45_write(sc, phy,
10824 elink_cl45_write(sc, phy,
10832 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
10843 elink_wait_reset_complete(sc, phy, params);
10845 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10846 return elink_848xx_cmn_config_init(phy, params, vars);
10852 static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,
10869 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10886 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10894 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10903 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10921 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10929 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
10940 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10946 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10959 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10969 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10976 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10979 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10994 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11001 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11008 static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,
11016 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
11020 return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
11023 return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
11028 static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,
11049 status = elink_848xx_cmd_hdlr(phy, params,
11096 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
11108 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11111 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11129 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
11140 rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
11147 return elink_eee_disable(phy, params, vars);
11150 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
11158 rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
11165 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
11169 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
11187 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11193 elink_cl45_write(sc, phy,
11198 elink_wait_reset_complete(sc, phy, params);
11202 if (!elink_is_8483x_8485x(phy)) {
11209 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
11210 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
11214 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
11217 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11226 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11262 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
11265 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11270 if (elink_is_8483x_8485x(phy)) {
11271 elink_848xx_pair_swap_cfg(phy, params, vars);
11278 rc = elink_848xx_cmd_hdlr(phy, params,
11285 rc = elink_848xx_cmn_config_init(phy, params, vars);
11287 elink_save_848xx_spirom_version(phy, sc, params->port);
11289 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11295 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11301 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11305 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11315 elink_8483x_disable_eee(phy, params, vars);
11319 if ((phy->req_duplex == DUPLEX_FULL) &&
11323 rc = elink_8483x_enable_eee(phy, params, vars);
11325 rc = elink_8483x_disable_eee(phy, params, vars);
11334 if (elink_is_8483x_8485x(phy)) {
11336 elink_cl45_read_and_write(sc, phy,
11344 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
11355 elink_cl45_read(sc, phy,
11357 elink_cl45_read(sc, phy,
11367 elink_ext_phy_10G_an_resolve(sc, phy, vars);
11372 elink_cl45_write(sc, phy,
11377 elink_cl45_read(sc, phy,
11401 elink_cl45_read(sc, phy,
11420 elink_cl45_read(sc, phy,
11427 elink_cl45_read(sc, phy,
11439 elink_ext_phy_resolve_fc(phy, params, vars);
11442 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11460 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11470 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11478 if (elink_is_8483x_8485x(phy))
11479 elink_eee_an_resolve(phy, params, vars);
11494 static void elink_8481_hw_reset(struct elink_phy *phy,
11503 static void elink_8481_link_reset(struct elink_phy *phy,
11506 elink_cl45_write(params->sc, phy,
11508 elink_cl45_write(params->sc, phy,
11512 static void elink_848x3_link_reset(struct elink_phy *phy,
11524 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11529 elink_cl45_read(sc, phy,
11533 elink_cl45_write(sc, phy,
11539 static void elink_848xx_set_link_led(struct elink_phy *phy,
11559 elink_cl45_write(sc, phy,
11564 elink_cl45_write(sc, phy,
11569 elink_cl45_write(sc, phy,
11574 elink_cl45_write(sc, phy,
11580 elink_cl45_write(sc, phy,
11595 elink_cl45_write(sc, phy,
11600 elink_cl45_write(sc, phy,
11605 elink_cl45_write(sc, phy,
11610 elink_cl45_write(sc, phy,
11616 elink_cl45_write(sc, phy,
11620 if (phy->type ==
11637 elink_cl45_write(sc, phy,
11651 elink_cl45_read(sc, phy,
11658 elink_cl45_write(sc, phy,
11664 elink_cl45_write(sc, phy,
11669 elink_cl45_write(sc, phy,
11674 elink_cl45_write(sc, phy,
11679 elink_cl45_write(sc, phy,
11684 elink_cl45_write(sc, phy,
11688 if (phy->type ==
11705 elink_cl45_write(sc, phy,
11721 elink_cl45_read(sc, phy,
11730 elink_cl45_write(sc, phy,
11737 elink_cl45_write(sc, phy,
11742 elink_cl45_write(sc, phy,
11747 elink_cl45_write(sc, phy,
11752 elink_cl45_write(sc, phy,
11766 elink_cl45_write(sc, phy,
11772 elink_cl45_read(sc, phy,
11778 elink_cl45_write(sc, phy,
11782 if (phy->type ==
11787 elink_cl45_write(sc, phy,
11806 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
11814 static void elink_54618se_specific_func(struct elink_phy *phy,
11824 elink_cl22_write(sc, phy,
11827 elink_cl22_read(sc, phy,
11832 elink_cl22_write(sc, phy,
11836 elink_cl22_write(sc, phy,
11843 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
11872 /* reset phy */
11873 elink_cl22_write(sc, phy,
11875 elink_wait_reset_complete(sc, phy, params);
11881 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
11883 elink_cl22_write(sc, phy,
11886 elink_cl22_read(sc, phy,
11890 elink_cl22_write(sc, phy,
11896 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11907 elink_cl22_read(sc, phy,
11911 elink_cl22_read(sc, phy,
11915 elink_cl22_read(sc, phy,
11924 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
11925 (phy->speed_cap_mask &
11927 (phy->req_line_speed == ELINK_SPEED_1000)) {
11930 if (phy->req_duplex == DUPLEX_FULL)
11936 elink_cl22_write(sc, phy,
11939 elink_cl22_read(sc, phy,
11944 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
11945 if (phy->speed_cap_mask &
11951 if (phy->speed_cap_mask &
11957 if (phy->speed_cap_mask &
11963 if (phy->speed_cap_mask &
11972 if (phy->req_line_speed == ELINK_SPEED_100) {
11975 elink_cl22_write(sc, phy,
11980 if (phy->req_line_speed == ELINK_SPEED_10) {
11982 elink_cl22_write(sc, phy,
11988 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
11991 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
11994 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11996 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
12001 elink_eee_disable(phy, params, vars);
12003 (phy->req_duplex == DUPLEX_FULL) &&
12011 elink_eee_advertise(phy, params, vars,
12015 elink_eee_disable(phy, params, vars);
12021 if (phy->flags & ELINK_FLAGS_EEE) {
12031 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
12036 elink_cl22_write(sc, phy,
12040 if (phy->req_duplex == DUPLEX_FULL)
12043 elink_cl22_write(sc, phy,
12050 static void elink_5461x_set_link_led(struct elink_phy *phy,
12056 elink_cl22_write(sc, phy,
12059 elink_cl22_read(sc, phy,
12079 elink_cl22_write(sc, phy,
12086 static void elink_54618se_link_reset(struct elink_phy *phy,
12096 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
12111 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
12121 elink_cl22_read(sc, phy,
12127 elink_cl22_read(sc, phy,
12164 elink_cl22_read(sc, phy,
12170 elink_cl22_read(sc, phy,
12180 elink_ext_phy_resolve_fc(phy, params, vars);
12184 elink_cl22_read(sc, phy, 0x5, &val);
12202 elink_cl22_read(sc, phy, 0xa, &val);
12210 if ((phy->flags & ELINK_FLAGS_EEE) &&
12212 elink_eee_an_resolve(phy, params, vars);
12218 static void elink_54618se_config_loopback(struct elink_phy *phy,
12229 elink_cl22_write(sc, phy, 0x09, 3<<11);
12236 elink_cl22_read(sc, phy, 0x00, &val);
12239 elink_cl22_write(sc, phy, 0x00, val);
12245 elink_cl22_write(sc, phy, 0x18, 7);
12246 elink_cl22_read(sc, phy, 0x18, &val);
12247 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));
12261 static void elink_7101_config_loopback(struct elink_phy *phy,
12266 elink_cl45_write(sc, phy,
12270 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
12283 elink_wait_reset_complete(sc, phy, params);
12285 elink_cl45_write(sc, phy,
12288 elink_cl45_write(sc, phy,
12291 elink_ext_phy_set_pause(params, phy, vars);
12293 elink_cl45_read(sc, phy,
12296 elink_cl45_write(sc, phy,
12300 elink_cl45_read(sc, phy,
12303 elink_cl45_read(sc, phy,
12306 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
12310 static uint8_t elink_7101_read_status(struct elink_phy *phy,
12317 elink_cl45_read(sc, phy,
12319 elink_cl45_read(sc, phy,
12323 elink_cl45_read(sc, phy,
12325 elink_cl45_read(sc, phy,
12332 elink_cl45_read(sc, phy,
12339 elink_ext_phy_10G_an_resolve(sc, phy, vars);
12340 elink_ext_phy_resolve_fc(phy, params, vars);
12363 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)
12367 elink_cl45_read(sc, phy,
12374 elink_cl45_write(sc, phy,
12379 elink_cl45_read(sc, phy,
12388 static void elink_7101_hw_reset(struct elink_phy *phy,
12398 static void elink_7101_set_link_led(struct elink_phy *phy,
12415 elink_cl45_write(sc, phy,
12954 /* Populate the phy according. Main function: elink_populate_phy */
12959 struct elink_phy *phy, uint8_t port,
12987 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12988 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12990 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12991 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12992 ELINK_DEBUG_P2(sc,"phy->rx_preemphasis = %x, phy->tx_preemphasis = %x\n",
12993 phy->rx_preemphasis[i << 1], phy->tx_preemphasis[i << 1]);
13020 struct elink_phy *phy)
13036 *phy = phy_warpcore;
13038 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
13040 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
13051 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
13060 phy->media_type = ELINK_ETH_PHY_BASE_T;
13063 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
13068 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
13071 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
13076 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
13079 phy->media_type = ELINK_ETH_PHY_KR;
13080 phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |
13088 phy->media_type = ELINK_ETH_PHY_KR;
13089 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
13090 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
13096 phy->media_type = ELINK_ETH_PHY_KR;
13097 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
13098 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
13105 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13118 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
13120 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
13122 phy->media_type, phy->flags, phy->supported);
13130 *phy = phy_serdes;
13136 *phy = phy_xgxs;
13143 phy->addr = (uint8_t)phy_addr;
13144 phy->mdio_ctrl = elink_get_emac_base(sc,
13148 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
13150 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
13152 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
13153 port, phy->addr, phy->mdio_ctrl);
13155 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
13164 struct elink_phy *phy)
13171 /* Select the phy type */
13175 *phy = phy_8073;
13178 *phy = phy_8705;
13181 *phy = phy_8706;
13185 *phy = phy_8726;
13190 *phy = phy_8727;
13191 phy->flags |= ELINK_FLAGS_NOC;
13196 *phy = phy_8727;
13199 *phy = phy_8481;
13202 *phy = phy_84823;
13205 *phy = phy_84833;
13208 *phy = phy_84834;
13211 *phy = phy_84858;
13215 *phy = phy_54618se;
13217 phy->flags |= ELINK_FLAGS_EEE;
13220 *phy = phy_7101;
13223 *phy = phy_null;
13226 *phy = phy_null;
13234 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
13235 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
13237 /* The shmem address of the phy version is located on different
13244 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
13256 phy->ver_addr = shmem2_base +
13267 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
13269 if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {
13270 /* Remove 100Mb link supported for BCM84833/4 when phy fw
13273 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
13276 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
13283 phy->addr, phy->mdio_ctrl);
13288 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
13291 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
13293 return elink_populate_int_phy(sc, shmem_base, port, phy);
13295 port, phy);
13300 struct elink_phy *phy,
13305 /* Populate the default phy configuration for MF mode */
13310 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13318 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13324 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
13325 phy_index, link_config, phy->speed_cap_mask);
13327 phy->req_duplex = DUPLEX_FULL;
13330 phy->req_duplex = DUPLEX_HALF;
13332 phy->req_line_speed = ELINK_SPEED_10;
13335 phy->req_duplex = DUPLEX_HALF;
13337 phy->req_line_speed = ELINK_SPEED_100;
13340 phy->req_line_speed = ELINK_SPEED_1000;
13343 phy->req_line_speed = ELINK_SPEED_2500;
13346 phy->req_line_speed = ELINK_SPEED_10000;
13349 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
13353 ELINK_DEBUG_P2(sc, "Default config phy idx %x, req_duplex config %x\n",
13354 phy_index, phy->req_duplex);
13358 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
13361 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
13364 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
13367 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
13370 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
13374 phy->req_duplex, phy->req_line_speed, phy->req_flow_ctrl);
13414 struct elink_phy *phy;
13416 ELINK_DEBUG_P0(sc, "Begin phy probe\n");
13436 phy = ¶ms->phy[actual_phy_idx];
13439 phy) != ELINK_STATUS_OK) {
13441 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n",
13446 *phy = phy_null;
13449 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
13454 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13458 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
13472 media_types |= ((phy->media_type &
13479 elink_phy_def_cfg(params, phy, phy_index);
13483 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys);
13726 elink_set_aer_mmd(params, ¶ms->phy[0]);
13727 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
13728 params->phy[ELINK_INT_PHY].config_loopback(
13729 ¶ms->phy[ELINK_INT_PHY],
13755 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
13789 /* Set external phy loopback */
13793 if (params->phy[phy_index].config_loopback)
13794 params->phy[phy_index].config_loopback(
13795 ¶ms->phy[phy_index],
13838 struct elink_phy *phy = ¶ms->phy[phy_idx];
13839 if (phy->phy_specific_func) {
13841 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
13843 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
13844 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
13845 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
13846 elink_verify_sfp_module(phy, params);
14021 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n");
14132 if (params->phy[phy_index].link_reset) {
14134 ¶ms->phy[phy_index]);
14135 params->phy[phy_index].link_reset(
14136 ¶ms->phy[phy_index],
14139 if (params->phy[phy_index].flags &
14154 if (params->phy[ELINK_INT_PHY].link_reset)
14155 params->phy[ELINK_INT_PHY].link_reset(
14156 ¶ms->phy[ELINK_INT_PHY], params);
14237 struct elink_phy phy[PORT_MAX];
14250 /* In E2, same phy is using for port0 of the two paths */
14261 /* Extract the ext phy address for the port */
14263 port_of_path, &phy[port]) !=
14276 /* Need to take the phy out of low power mode in order
14283 /* Reset the phy */
14284 elink_cl45_write(sc, &phy[port],
14293 if (phy[PORT_0].addr & 0x1) {
14294 phy_blk[PORT_0] = &(phy[PORT_1]);
14295 phy_blk[PORT_1] = &(phy[PORT_0]);
14297 phy_blk[PORT_0] = &(phy[PORT_0]);
14298 phy_blk[PORT_1] = &(phy[PORT_1]);
14308 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14365 struct elink_phy phy;
14378 /* In E2, same phy is using for port0 of the two paths */
14386 /* Extract the ext phy address for the port */
14388 port, &phy) !=
14390 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14394 /* Reset phy*/
14395 elink_cl45_write(sc, &phy,
14460 struct elink_phy phy[PORT_MAX];
14491 /* In E2, same phy is using for port0 of the two paths */
14502 /* Extract the ext phy address for the port */
14504 port_of_path, &phy[port]) !=
14506 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14518 /* Reset the phy */
14519 elink_cl45_write(sc, &phy[port],
14525 if (phy[PORT_0].addr & 0x1) {
14526 phy_blk[PORT_0] = &(phy[PORT_1]);
14527 phy_blk[PORT_1] = &(phy[PORT_0]);
14529 phy_blk[PORT_0] = &(phy[PORT_0]);
14530 phy_blk[PORT_1] = &(phy[PORT_1]);
14538 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14637 ELINK_DEBUG_P0(sc, "Begin common phy init\n");
14648 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",
14838 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
14874 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
14883 struct elink_phy *phy)
14887 elink_warpcore_enable_AN_KR2(phy, params, vars);
14888 elink_warpcore_restart_AN_KR(phy, params);
14893 struct elink_phy *phy)
14909 sigdet = elink_warpcore_get_sigdet(phy, params);
14912 elink_kr2_recovery(params, vars, phy);
14918 lane = elink_get_warpcore_lane(phy, params);
14919 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
14921 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14923 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14925 elink_set_aer_mmd(params, phy);
14930 elink_kr2_recovery(params, vars, phy);
14949 elink_kr2_recovery(params, vars, phy);
14957 elink_disable_kr2(params, vars, phy);
14959 elink_warpcore_restart_AN_KR(phy, params);
14969 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
14970 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
14979 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
14980 elink_set_aer_mmd(params, phy);
14981 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
14982 (phy->speed_cap_mask &
14984 (phy->req_line_speed == ELINK_SPEED_20000))
14985 elink_check_kr2_wa(params, vars, phy);
14988 elink_warpcore_config_runtime(phy, params, vars);
14995 if (elink_is_sfp_module_plugged(phy, params)) {
14996 elink_sfp_tx_fault_detection(phy, params, vars);
15015 struct elink_phy phy;
15019 port, &phy)
15021 ELINK_DEBUG_P0(sc, "populate phy failed\n");
15024 fan_failure_det_req |= (phy.flags &
15043 if (params->phy[phy_index].hw_reset) {
15044 params->phy[phy_index].hw_reset(
15045 ¶ms->phy[phy_index],
15047 params->phy[phy_index] = phy_null;
15067 struct elink_phy phy;
15071 shmem2_base, port, &phy)
15073 ELINK_DEBUG_P0(sc, "populate phy failed\n");
15076 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {