dev/bxe/bxe_elink.c

2612 		/* Use lane 1 (of lanes 0-3) */
2621 		/* Use lane 1 (of lanes 0-3) */
4048 	uint8_t lane = 0;
4079 		lane = (port<<1) + path;
4094 		lane = path << 1 ;
4096 	return lane;
4115 		/* In Dual-lane mode, two lanes are joined together,
4372 		uint8_t lane = elink_get_warpcore_lane(phy, params);
4379 			lane;
4438  * i.e. reset the lane (if needed), set aer for the
4552 	/* Restart autoneg on the leading lane only */
4554 	uint16_t lane = elink_get_warpcore_lane(phy, params);
4556 			  MDIO_AER_BLOCK_AER_REG, lane);
4567 	uint16_t lane, i, cl72_ctrl, an_adv = 0, val;
4620 	lane = elink_get_warpcore_lane(phy, params);
4622 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4624 	/* Configure the next lane if dual mode */
4627 				 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
4672 				  MDIO_AER_BLOCK_AER_REG, lane);
4675 					 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
4691 				MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
4701 		    (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
4706 				 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
4712 	/* Enable Autoneg: only on the main lane */
4721 	uint16_t val16, i, lane;
4739 	lane = elink_get_warpcore_lane(phy, params);
4746 	val16 &= ~(0x0011 << lane);
4752 	val16 |= (0x0303 << (lane << 1));
4789 	uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
4888 	lane = elink_get_warpcore_lane(phy, params);
4893 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4924 	/* Set global registers, so set AER lane to 0 */
4962 	/* Enable sequencer (over lane 0) */
4974 					 uint16_t lane)
5022 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
5034 	/* Clear XFI clock comp in non-10G single lane mode. */
5114 	/* Take lane out of reset after configuration is finished */
5130 				      uint16_t lane)
5158 	lane = elink_get_warpcore_lane(phy, params);
5160 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
5224 	uint16_t gp2_status_reg0, lane;
5227 	lane = elink_get_warpcore_lane(phy, params);
5232 	return (gp2_status_reg0 >> (8+lane)) & 0x1;
5249 		uint16_t lane = elink_get_warpcore_lane(phy, params);
5260 			lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
5262 			lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
5267 				/* Reset the lane to see if link comes up.*/
5291 	uint16_t lane = elink_get_warpcore_lane(phy, params);
5293 	elink_warpcore_clear_regs(phy, params, lane);
5333 	uint16_t lane = elink_get_warpcore_lane(phy, params);
5350 		elink_warpcore_clear_regs(phy, params, lane);
5365 			elink_warpcore_clear_regs(phy, params, lane);
5408 			elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5429 	/* Take lane out of reset after configuration is finished */
5438 	uint16_t val16, lane;
5463 	lane = elink_get_warpcore_lane(phy, params);
5467 	val16 |= (0x11 << lane);
5469 		val16 |= (0x22 << lane);
5475 	val16 &= ~(0x0303 << (lane << 1));
5476 	val16 |= (0x0101 << (lane << 1));
5478 		val16 &= ~(0x0c0c << (lane << 1));
5479 		val16 |= (0x0404 << (lane << 1));
5494 	uint32_t lane;
5509 		/* Set 1G loopback based on lane (1-copy) */
5510 		lane = elink_get_warpcore_lane(phy, params);
5513 		val16 |= (1<<lane);
5515 			val16 |= (2<<lane);
5777 	/* Each two bits represents a lane number:
6544 	uint8_t lane;
6547 	lane = elink_get_warpcore_lane(phy, params);
6579 			(1 << lane);
6597 				if (gp_status4 & ((1<<12)<<lane))
6650 	if (lane < 2) {
6657 	ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6659 	if ((lane & 1) == 0)
7005 				 * the relevant lane in the status register
7347 			uint8_t lane = elink_get_warpcore_lane(int_phy, params);
7353 			link_up = gp_status & (1 << lane);
9538 	uint8_t lane = elink_get_warpcore_lane(phy, params);
9542 	val &= ~(0xf << (lane << 2));
9557 	val |= (mode << (lane << 2));
14896 	uint16_t base_page, next_page, not_kr2_device, lane;
14918 	lane = elink_get_warpcore_lane(phy, params);
14920 			  MDIO_AER_BLOCK_AER_REG, lane);
14958 		/* Restart AN on leading lane */