Lines Matching defs:ah
23 #include "ah.h"
38 ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
40 struct ath_hal_5212 *ahp = AH5212(ah);
46 ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
48 struct ath_hal_5212 *ahp = AH5212(ah);
55 ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
57 struct ath_hal_5212 *ahp = AH5212(ah);
63 ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
65 struct ath_hal_5212 *ahp = AH5212(ah);
70 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
71 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
79 ar5212SetRegulatoryDomain(struct ath_hal *ah,
84 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
88 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
93 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
94 HALDEBUG(ah, HAL_DEBUG_ANY,
97 AH_PRIVATE(ah)->ah_currentRD = regDomain;
115 ar5212GetWirelessModes(struct ath_hal *ah)
119 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
121 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
123 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
125 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
128 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
130 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
131 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
133 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
135 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
137 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
149 ar5212EnableRfKill(struct ath_hal *ah)
151 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
159 ath_hal_gpioCfgInput(ah, select);
160 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
169 ath_hal_gpioSetIntr(ah, select,
170 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
177 ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
191 bits = OS_REG_READ(ah, AR_PCICFG);
192 if (IS_2417(ah)) {
209 OS_REG_WRITE(ah, AR_PCICFG, bits);
219 ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
221 struct ath_hal_5212 *ahp = AH5212(ah);
226 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
227 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
235 ar5212GetTsf64(struct ath_hal *ah)
240 low1 = OS_REG_READ(ah, AR_TSF_L32);
241 u32 = OS_REG_READ(ah, AR_TSF_U32);
242 low2 = OS_REG_READ(ah, AR_TSF_L32);
263 ar5212GetTsf32(struct ath_hal *ah)
265 return OS_REG_READ(ah, AR_TSF_L32);
269 ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64)
271 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
272 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
279 ar5212ResetTsf(struct ath_hal *ah)
282 uint32_t val = OS_REG_READ(ah, AR_BEACON);
284 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
292 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
301 ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
303 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
321 reg = OS_REG_READ(ah, AR_STA_ID1);
323 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
325 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
333 ar5212GetRandomSeed(struct ath_hal *ah)
337 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
340 return (OS_REG_READ(ah, AR_TSF_U32) ^
341 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
348 ar5212DetectCardPresent(struct ath_hal *ah)
358 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
361 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
362 AH_PRIVATE(ah)->ah_macRev == macRev);
366 ar5212EnableMibCounters(struct ath_hal *ah)
369 OS_REG_WRITE(ah, AR_MIBC,
374 ar5212DisableMibCounters(struct ath_hal *ah)
376 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);
383 ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
385 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
386 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
387 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
388 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
389 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
396 ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
405 ar5212GetCurRssi(struct ath_hal *ah)
407 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
411 ar5212GetDefAntenna(struct ath_hal *ah)
413 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
417 ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
419 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
423 ar5212GetAntennaSwitch(struct ath_hal *ah)
425 return AH5212(ah)->ah_antControl;
429 ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
431 struct ath_hal_5212 *ahp = AH5212(ah);
432 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
440 return ar5212SetAntennaSwitchInternal(ah, setting, chan);
444 ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
450 ar5212SetSifsTime(struct ath_hal *ah, u_int us)
452 struct ath_hal_5212 *ahp = AH5212(ah);
454 if (us > ath_hal_mac_usec(ah, 0xffff)) {
455 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
461 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
468 ar5212GetSifsTime(struct ath_hal *ah)
470 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
471 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
475 ar5212SetSlotTime(struct ath_hal *ah, u_int us)
477 struct ath_hal_5212 *ahp = AH5212(ah);
479 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
480 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
486 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
493 ar5212GetSlotTime(struct ath_hal *ah)
495 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
496 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
500 ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
502 struct ath_hal_5212 *ahp = AH5212(ah);
504 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
505 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
511 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
512 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
519 ar5212GetAckTimeout(struct ath_hal *ah)
521 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
522 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
526 ar5212GetAckCTSRate(struct ath_hal *ah)
528 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
532 ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
534 struct ath_hal_5212 *ahp = AH5212(ah);
537 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
540 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
547 ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
549 struct ath_hal_5212 *ahp = AH5212(ah);
551 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
552 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
558 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
559 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
566 ar5212GetCTSTimeout(struct ath_hal *ah)
568 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
569 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
574 ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
576 struct ath_hal_5212 *ahp = AH5212(ah);
580 OS_REG_WRITE(ah, AR_DCM_A, keyidx);
581 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
589 ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
594 AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
597 if (AH_PRIVATE(ah)->ah_coverageClass == 0)
601 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
605 clkRate = ath_hal_mac_clks(ah, 1);
610 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
613 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
630 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
631 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
632 OS_REG_WRITE(ah, AR_TIME_OUT,
639 ar5212SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,
642 OS_REG_WRITE(ah, AR_QUIET2, period | (duration << AR_QUIET2_QUIET_DUR_S));
644 OS_REG_WRITE(ah, AR_QUIET1, nextStart | (1 << 16));
647 OS_REG_WRITE(ah, AR_QUIET1, nextStart);
653 ar5212SetPCUConfig(struct ath_hal *ah)
655 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
665 ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
668 struct ath_hal_5212 *ahp = AH5212(ah);
669 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
683 ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
685 if (ar5212Use32KHzclock(ah, opmode)) {
691 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
692 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
693 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
694 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
695 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
696 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
698 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
699 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);
700 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);
701 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);
702 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);
704 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
706 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);
707 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
708 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
709 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);
710 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
713 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
714 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
716 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */
718 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
719 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
721 if (IS_2417(ah))
722 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
723 else if (IS_HB63(ah))
724 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
726 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
727 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
728 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
729 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
730 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
731 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
732 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
740 ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
742 if (ar5212Use32KHzclock(ah, opmode)) {
744 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
745 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
747 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
748 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
749 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
754 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
755 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
756 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
757 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
758 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
759 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
760 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
769 ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
795 ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
798 #define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion
799 struct ath_hal_5212 *ahp = AH5212(ah);
800 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
839 return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
840 (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
841 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
849 *result = OS_REG_READ(ah, AR_PHY_RESTART);
855 *result = AH_PRIVATE(ah)->ah_diagreg;
868 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
871 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
872 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
912 ani = ar5212AniGetCurrentState(ah);
926 return ath_hal_getcapability(ah, type, capability, result);
932 ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
936 struct ath_hal_5212 *ahp = AH5212(ah);
937 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
956 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
965 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
970 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
979 v = OS_REG_READ(ah, AR_PHY_RESTART);
982 OS_REG_WRITE(ah, AR_PHY_RESTART, v);
993 AH_PRIVATE(ah)->ah_diagreg = setting;
994 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
1017 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
1032 AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) :
1045 return ath_hal_setcapability(ah, type, capability,
1052 ar5212GetDiagState(struct ath_hal *ah, int request,
1056 struct ath_hal_5212 *ahp = AH5212(ah);
1060 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1068 return ath_hal_eepromDiag(ah, request,
1084 *result = ar5212AniGetCurrentState(ah);
1090 astats = ar5212AniGetCurrentStats(ah);
1103 AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0],
1114 ar5212AniGetCurrentState(ah);
1123 return ar5212AniSetParams(ah, args, args);
1137 ar5212IsNFCalInProgress(struct ath_hal *ah)
1139 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1152 ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1158 if (! ar5212IsNFCalInProgress(ah))
1166 ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1169 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
1196 if (IS_5413(ah)) {
1198 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1201 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1205 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1208 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1212 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1215 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1219 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1222 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1226 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
1229 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
1233 OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
1237 OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
1241 OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
1245 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
1270 ar5212GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1273 if (IS_5413(ah)) {
1307 ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1311 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
1332 if (IS_5413(ah)) {
1333 val = OS_REG_READ(ah, AR_PHY_RADAR_2);
1351 ar5212ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,
1379 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n",
1397 ar5212IsFastClockEnabled(struct ath_hal *ah)
1407 ar5212Get11nExtBusy(struct ath_hal *ah)
1416 ar5212GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
1418 struct ath_hal_5212 *ahp = AH5212(ah);
1422 uint32_t rc = OS_REG_READ(ah, AR_RCCNT);
1423 uint32_t rf = OS_REG_READ(ah, AR_RFCNT);
1424 uint32_t tf = OS_REG_READ(ah, AR_TFCNT);
1425 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1433 HALDEBUG(ah, HAL_DEBUG_ANY,
1457 ar5212SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,