Lines Matching refs:uint64_t
56 static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
71 static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
86 static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
101 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
116 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
131 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
146 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
161 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
176 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
191 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
206 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
221 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
236 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
251 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
266 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
281 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
296 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
311 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
326 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
341 static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
356 static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
371 static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
386 static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
409 uint64_t u64;
412 uint64_t reserved_7_63 : 57;
413 uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */
414 uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */
415 uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */
416 uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */
417 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */
418 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */
419 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */
421 uint64_t nof_bis : 1;
422 uint64_t nif_bis : 1;
423 uint64_t usbc_bis : 1;
424 uint64_t n2uf_bis : 1;
425 uint64_t e2hc_bis : 1;
426 uint64_t u2nf_bis : 1;
427 uint64_t u2nc_bis : 1;
428 uint64_t reserved_7_63 : 57;
433 uint64_t reserved_3_63 : 61;
434 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */
435 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */
436 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */
438 uint64_t nof_bis : 1;
439 uint64_t nif_bis : 1;
440 uint64_t usbc_bis : 1;
441 uint64_t reserved_3_63 : 61;
461 uint64_t u64;
464 uint64_t reserved_20_63 : 44;
465 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
472 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
478 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
485 uint64_t reserved_14_15 : 2;
486 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
492 uint64_t p_c_sel : 2; /**< Phy clock speed select.
502 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
503 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
505 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
507 uint64_t por : 1; /**< Power On Reset for the PHY.
509 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
512 uint64_t prst : 1; /**< When this field is '0' the reset associated with
519 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
525 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
535 uint64_t divide : 3;
536 uint64_t hrst : 1;
537 uint64_t prst : 1;
538 uint64_t enable : 1;
539 uint64_t por : 1;
540 uint64_t s_bist : 1;
541 uint64_t sd_mode : 2;
542 uint64_t cdiv_byp : 1;
543 uint64_t p_c_sel : 2;
544 uint64_t p_com_on : 1;
545 uint64_t reserved_14_15 : 2;
546 uint64_t p_x_on : 1;
547 uint64_t hclk_rst : 1;
548 uint64_t divide2 : 2;
549 uint64_t reserved_20_63 : 44;
554 uint64_t reserved_18_63 : 46;
555 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
561 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
568 uint64_t p_rclk : 1; /**< Phy refrence clock enable.
572 uint64_t p_xenbn : 1; /**< Phy external clock enable.
577 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
583 uint64_t p_c_sel : 2; /**< Phy clock speed select.
591 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
592 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
594 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
596 uint64_t por : 1; /**< Power On Reset for the PHY.
598 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
600 uint64_t prst : 1; /**< When this field is '0' the reset associated with
607 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
613 uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived
619 uint64_t divide : 3;
620 uint64_t hrst : 1;
621 uint64_t prst : 1;
622 uint64_t enable : 1;
623 uint64_t por : 1;
624 uint64_t s_bist : 1;
625 uint64_t sd_mode : 2;
626 uint64_t cdiv_byp : 1;
627 uint64_t p_c_sel : 2;
628 uint64_t p_com_on : 1;
629 uint64_t p_xenbn : 1;
630 uint64_t p_rclk : 1;
631 uint64_t p_x_on : 1;
632 uint64_t hclk_rst : 1;
633 uint64_t reserved_18_63 : 46;
639 uint64_t reserved_20_63 : 44;
640 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
647 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
653 uint64_t reserved_16_16 : 1;
654 uint64_t p_rtype : 2; /**< PHY reference clock type
664 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
670 uint64_t p_c_sel : 2; /**< Phy clock speed select.
680 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
681 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
683 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
685 uint64_t por : 1; /**< Power On Reset for the PHY.
687 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
690 uint64_t prst : 1; /**< When this field is '0' the reset associated with
697 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
703 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
713 uint64_t divide : 3;
714 uint64_t hrst : 1;
715 uint64_t prst : 1;
716 uint64_t enable : 1;
717 uint64_t por : 1;
718 uint64_t s_bist : 1;
719 uint64_t sd_mode : 2;
720 uint64_t cdiv_byp : 1;
721 uint64_t p_c_sel : 2;
722 uint64_t p_com_on : 1;
723 uint64_t p_rtype : 2;
724 uint64_t reserved_16_16 : 1;
725 uint64_t hclk_rst : 1;
726 uint64_t divide2 : 2;
727 uint64_t reserved_20_63 : 44;
745 uint64_t u64;
748 uint64_t reserved_6_63 : 58;
749 uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page
751 uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */
752 uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode.
754 uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB
759 uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C.
766 uint64_t l2c_emod : 2;
767 uint64_t inv_a2 : 1;
768 uint64_t dma_test : 1;
769 uint64_t dma_stt : 1;
770 uint64_t dma_0pag : 1;
771 uint64_t reserved_6_63 : 58;
793 uint64_t u64;
796 uint64_t reserved_36_63 : 28;
797 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
799 uint64_t addr : 36;
800 uint64_t reserved_36_63 : 28;
822 uint64_t u64;
825 uint64_t reserved_36_63 : 28;
826 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
828 uint64_t addr : 36;
829 uint64_t reserved_36_63 : 28;
851 uint64_t u64;
854 uint64_t reserved_36_63 : 28;
855 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
857 uint64_t addr : 36;
858 uint64_t reserved_36_63 : 28;
880 uint64_t u64;
883 uint64_t reserved_36_63 : 28;
884 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
886 uint64_t addr : 36;
887 uint64_t reserved_36_63 : 28;
909 uint64_t u64;
912 uint64_t reserved_36_63 : 28;
913 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
915 uint64_t addr : 36;
916 uint64_t reserved_36_63 : 28;
938 uint64_t u64;
941 uint64_t reserved_36_63 : 28;
942 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
944 uint64_t addr : 36;
945 uint64_t reserved_36_63 : 28;
967 uint64_t u64;
970 uint64_t reserved_36_63 : 28;
971 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
973 uint64_t addr : 36;
974 uint64_t reserved_36_63 : 28;
996 uint64_t u64;
999 uint64_t reserved_36_63 : 28;
1000 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
1002 uint64_t addr : 36;
1003 uint64_t reserved_36_63 : 28;
1025 uint64_t u64;
1028 uint64_t reserved_36_63 : 28;
1029 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1031 uint64_t addr : 36;
1032 uint64_t reserved_36_63 : 28;
1054 uint64_t u64;
1057 uint64_t reserved_36_63 : 28;
1058 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1060 uint64_t addr : 36;
1061 uint64_t reserved_36_63 : 28;
1083 uint64_t u64;
1086 uint64_t reserved_36_63 : 28;
1087 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1089 uint64_t addr : 36;
1090 uint64_t reserved_36_63 : 28;
1112 uint64_t u64;
1115 uint64_t reserved_36_63 : 28;
1116 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1118 uint64_t addr : 36;
1119 uint64_t reserved_36_63 : 28;
1141 uint64_t u64;
1144 uint64_t reserved_36_63 : 28;
1145 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1147 uint64_t addr : 36;
1148 uint64_t reserved_36_63 : 28;
1170 uint64_t u64;
1173 uint64_t reserved_36_63 : 28;
1174 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1176 uint64_t addr : 36;
1177 uint64_t reserved_36_63 : 28;
1199 uint64_t u64;
1202 uint64_t reserved_36_63 : 28;
1203 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1205 uint64_t addr : 36;
1206 uint64_t reserved_36_63 : 28;
1228 uint64_t u64;
1231 uint64_t reserved_36_63 : 28;
1232 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
1234 uint64_t addr : 36;
1235 uint64_t reserved_36_63 : 28;
1256 uint64_t u64;
1259 uint64_t reserved_40_63 : 24;
1260 uint64_t done : 1; /**< This field is set when a DMA completes. Writing a
1262 uint64_t req : 1; /**< DMA Request. Writing a 1 to this register
1266 uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */
1267 uint64_t count : 11; /**< DMA Request Count. */
1268 uint64_t channel : 5; /**< DMA Channel/Enpoint. */
1269 uint64_t burst : 4; /**< DMA Burst Size. */
1271 uint64_t burst : 4;
1272 uint64_t channel : 5;
1273 uint64_t count : 11;
1274 uint64_t f_addr : 18;
1275 uint64_t req : 1;
1276 uint64_t done : 1;
1277 uint64_t reserved_40_63 : 24;
1298 uint64_t u64;
1301 uint64_t reserved_38_63 : 26;
1302 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM
1305 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM
1308 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM
1311 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM
1314 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM
1317 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM
1320 uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM
1323 uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM
1326 uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM
1329 uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM
1332 uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM
1335 uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM
1338 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM
1341 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM
1344 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM
1347 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM
1350 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM
1353 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM
1356 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM
1359 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM
1362 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM
1365 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM
1368 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM
1371 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM
1374 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM
1377 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM
1380 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM
1383 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM
1386 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM
1389 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM
1392 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM
1395 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM
1398 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM
1401 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM
1404 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM
1407 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM
1410 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM
1413 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM
1417 uint64_t pr_po_e : 1;
1418 uint64_t pr_pu_f : 1;
1419 uint64_t nr_po_e : 1;
1420 uint64_t nr_pu_f : 1;
1421 uint64_t lr_po_e : 1;
1422 uint64_t lr_pu_f : 1;
1423 uint64_t pt_po_e : 1;
1424 uint64_t pt_pu_f : 1;
1425 uint64_t nt_po_e : 1;
1426 uint64_t nt_pu_f : 1;
1427 uint64_t lt_po_e : 1;
1428 uint64_t lt_pu_f : 1;
1429 uint64_t dcred_e : 1;
1430 uint64_t dcred_f : 1;
1431 uint64_t l2c_s_e : 1;
1432 uint64_t l2c_a_f : 1;
1433 uint64_t l2_fi_e : 1;
1434 uint64_t l2_fi_f : 1;
1435 uint64_t rg_fi_e : 1;
1436 uint64_t rg_fi_f : 1;
1437 uint64_t rq_q2_f : 1;
1438 uint64_t rq_q2_e : 1;
1439 uint64_t rq_q3_f : 1;
1440 uint64_t rq_q3_e : 1;
1441 uint64_t uod_pe : 1;
1442 uint64_t uod_pf : 1;
1443 uint64_t n2u_pf : 1;
1444 uint64_t n2u_pe : 1;
1445 uint64_t u2n_d_pe : 1;
1446 uint64_t u2n_d_pf : 1;
1447 uint64_t u2n_c_pf : 1;
1448 uint64_t u2n_c_pe : 1;
1449 uint64_t ltl_f_pe : 1;
1450 uint64_t ltl_f_pf : 1;
1451 uint64_t nd4o_rpe : 1;
1452 uint64_t nd4o_rpf : 1;
1453 uint64_t nd4o_dpe : 1;
1454 uint64_t nd4o_dpf : 1;
1455 uint64_t reserved_38_63 : 26;
1462 uint64_t reserved_38_63 : 26;
1463 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM
1466 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM
1469 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM
1472 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM
1475 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM
1478 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM
1481 uint64_t reserved_26_31 : 6;
1482 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM
1485 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM
1488 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM
1491 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM
1494 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM
1497 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM
1500 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM
1503 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM
1506 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM
1509 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM
1512 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM
1515 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM
1518 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM
1521 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM
1524 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM
1527 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM
1530 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM
1533 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM
1536 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM
1539 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM
1542 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM
1545 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM
1548 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM
1551 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM
1554 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM
1557 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM
1561 uint64_t pr_po_e : 1;
1562 uint64_t pr_pu_f : 1;
1563 uint64_t nr_po_e : 1;
1564 uint64_t nr_pu_f : 1;
1565 uint64_t lr_po_e : 1;
1566 uint64_t lr_pu_f : 1;
1567 uint64_t pt_po_e : 1;
1568 uint64_t pt_pu_f : 1;
1569 uint64_t nt_po_e : 1;
1570 uint64_t nt_pu_f : 1;
1571 uint64_t lt_po_e : 1;
1572 uint64_t lt_pu_f : 1;
1573 uint64_t dcred_e : 1;
1574 uint64_t dcred_f : 1;
1575 uint64_t l2c_s_e : 1;
1576 uint64_t l2c_a_f : 1;
1577 uint64_t l2_fi_e : 1;
1578 uint64_t l2_fi_f : 1;
1579 uint64_t rg_fi_e : 1;
1580 uint64_t rg_fi_f : 1;
1581 uint64_t rq_q2_f : 1;
1582 uint64_t rq_q2_e : 1;
1583 uint64_t rq_q3_f : 1;
1584 uint64_t rq_q3_e : 1;
1585 uint64_t uod_pe : 1;
1586 uint64_t uod_pf : 1;
1587 uint64_t reserved_26_31 : 6;
1588 uint64_t ltl_f_pe : 1;
1589 uint64_t ltl_f_pf : 1;
1590 uint64_t nd4o_rpe : 1;
1591 uint64_t nd4o_rpf : 1;
1592 uint64_t nd4o_dpe : 1;
1593 uint64_t nd4o_dpf : 1;
1594 uint64_t reserved_38_63 : 26;
1612 uint64_t u64;
1615 uint64_t reserved_38_63 : 26;
1616 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */
1617 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */
1618 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */
1619 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */
1620 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */
1621 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */
1622 uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */
1623 uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */
1624 uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */
1625 uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */
1626 uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */
1627 uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */
1628 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */
1629 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */
1630 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1631 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1632 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1633 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1634 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */
1635 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */
1636 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */
1637 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */
1638 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */
1639 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */
1640 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */
1641 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */
1642 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */
1643 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */
1644 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */
1645 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */
1646 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */
1647 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */
1648 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */
1649 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */
1650 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */
1651 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */
1652 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */
1653 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */
1655 uint64_t pr_po_e : 1;
1656 uint64_t pr_pu_f : 1;
1657 uint64_t nr_po_e : 1;
1658 uint64_t nr_pu_f : 1;
1659 uint64_t lr_po_e : 1;
1660 uint64_t lr_pu_f : 1;
1661 uint64_t pt_po_e : 1;
1662 uint64_t pt_pu_f : 1;
1663 uint64_t nt_po_e : 1;
1664 uint64_t nt_pu_f : 1;
1665 uint64_t lt_po_e : 1;
1666 uint64_t lt_pu_f : 1;
1667 uint64_t dcred_e : 1;
1668 uint64_t dcred_f : 1;
1669 uint64_t l2c_s_e : 1;
1670 uint64_t l2c_a_f : 1;
1671 uint64_t lt_fi_e : 1;
1672 uint64_t lt_fi_f : 1;
1673 uint64_t rg_fi_e : 1;
1674 uint64_t rg_fi_f : 1;
1675 uint64_t rq_q2_f : 1;
1676 uint64_t rq_q2_e : 1;
1677 uint64_t rq_q3_f : 1;
1678 uint64_t rq_q3_e : 1;
1679 uint64_t uod_pe : 1;
1680 uint64_t uod_pf : 1;
1681 uint64_t n2u_pf : 1;
1682 uint64_t n2u_pe : 1;
1683 uint64_t u2n_d_pe : 1;
1684 uint64_t u2n_d_pf : 1;
1685 uint64_t u2n_c_pf : 1;
1686 uint64_t u2n_c_pe : 1;
1687 uint64_t ltl_f_pe : 1;
1688 uint64_t ltl_f_pf : 1;
1689 uint64_t nd4o_rpe : 1;
1690 uint64_t nd4o_rpf : 1;
1691 uint64_t nd4o_dpe : 1;
1692 uint64_t nd4o_dpf : 1;
1693 uint64_t reserved_38_63 : 26;
1700 uint64_t reserved_38_63 : 26;
1701 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */
1702 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */
1703 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */
1704 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */
1705 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */
1706 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */
1707 uint64_t reserved_26_31 : 6;
1708 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */
1709 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */
1710 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1711 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1712 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1713 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1714 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */
1715 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */
1716 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */
1717 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */
1718 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */
1719 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */
1720 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */
1721 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */
1722 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */
1723 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */
1724 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */
1725 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */
1726 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */
1727 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */
1728 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */
1729 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */
1730 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */
1731 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */
1732 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */
1733 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */
1735 uint64_t pr_po_e : 1;
1736 uint64_t pr_pu_f : 1;
1737 uint64_t nr_po_e : 1;
1738 uint64_t nr_pu_f : 1;
1739 uint64_t lr_po_e : 1;
1740 uint64_t lr_pu_f : 1;
1741 uint64_t pt_po_e : 1;
1742 uint64_t pt_pu_f : 1;
1743 uint64_t nt_po_e : 1;
1744 uint64_t nt_pu_f : 1;
1745 uint64_t lt_po_e : 1;
1746 uint64_t lt_pu_f : 1;
1747 uint64_t dcred_e : 1;
1748 uint64_t dcred_f : 1;
1749 uint64_t l2c_s_e : 1;
1750 uint64_t l2c_a_f : 1;
1751 uint64_t lt_fi_e : 1;
1752 uint64_t lt_fi_f : 1;
1753 uint64_t rg_fi_e : 1;
1754 uint64_t rg_fi_f : 1;
1755 uint64_t rq_q2_f : 1;
1756 uint64_t rq_q2_e : 1;
1757 uint64_t rq_q3_f : 1;
1758 uint64_t rq_q3_e : 1;
1759 uint64_t uod_pe : 1;
1760 uint64_t uod_pf : 1;
1761 uint64_t reserved_26_31 : 6;
1762 uint64_t ltl_f_pe : 1;
1763 uint64_t ltl_f_pf : 1;
1764 uint64_t nd4o_rpe : 1;
1765 uint64_t nd4o_rpf : 1;
1766 uint64_t nd4o_dpe : 1;
1767 uint64_t nd4o_dpf : 1;
1768 uint64_t reserved_38_63 : 26;
1786 uint64_t u64;
1789 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
1790 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
1791 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
1792 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
1793 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
1794 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
1795 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
1796 uint64_t otgdisable : 1; /**< OTG Block Disable */
1797 uint64_t portreset : 1; /**< Per_Port Reset */
1798 uint64_t drvvbus : 1; /**< Drive VBUS */
1799 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
1800 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
1801 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
1802 uint64_t bist_done : 1; /**< PHY Bist Done.
1804 uint64_t bist_err : 1; /**< PHY Bist Error.
1807 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1811 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
1818 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
1819 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1823 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1825 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1826 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1827 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1835 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1843 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1846 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
1861 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1864 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1867 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
1873 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
1877 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
1879 uint64_t tdata_sel : 1; /**< Test Data Out Select.
1883 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
1886 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
1890 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
1901 uint64_t ate_reset : 1;
1902 uint64_t tdata_in : 8;
1903 uint64_t taddr_in : 4;
1904 uint64_t tdata_sel : 1;
1905 uint64_t bist_enb : 1;
1906 uint64_t vtest_enb : 1;
1907 uint64_t loop_enb : 1;
1908 uint64_t tx_bs_en : 1;
1909 uint64_t tx_bs_enh : 1;
1910 uint64_t tuning : 4;
1911 uint64_t hst_mode : 1;
1912 uint64_t dm_pulld : 1;
1913 uint64_t dp_pulld : 1;
1914 uint64_t tclk : 1;
1915 uint64_t usbp_bist : 1;
1916 uint64_t usbc_end : 1;
1917 uint64_t dma_bmode : 1;
1918 uint64_t txpreemphasistune : 1;
1919 uint64_t siddq : 1;
1920 uint64_t tdata_out : 4;
1921 uint64_t bist_err : 1;
1922 uint64_t bist_done : 1;
1923 uint64_t hsbist : 1;
1924 uint64_t fsbist : 1;
1925 uint64_t lsbist : 1;
1926 uint64_t drvvbus : 1;
1927 uint64_t portreset : 1;
1928 uint64_t otgdisable : 1;
1929 uint64_t otgtune : 3;
1930 uint64_t compdistune : 3;
1931 uint64_t sqrxtune : 3;
1932 uint64_t txhsxvtune : 2;
1933 uint64_t txfslstune : 4;
1934 uint64_t txvreftune : 4;
1935 uint64_t txrisetune : 1;
1940 uint64_t reserved_38_63 : 26;
1941 uint64_t bist_done : 1; /**< PHY Bist Done.
1943 uint64_t bist_err : 1; /**< PHY Bist Error.
1946 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1950 uint64_t reserved_30_31 : 2;
1951 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1955 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1957 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1958 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1959 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1967 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1975 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1978 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
1993 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1996 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1999 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
2005 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
2009 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
2011 uint64_t tdata_sel : 1; /**< Test Data Out Select.
2015 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
2018 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
2022 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
2033 uint64_t ate_reset : 1;
2034 uint64_t tdata_in : 8;
2035 uint64_t taddr_in : 4;
2036 uint64_t tdata_sel : 1;
2037 uint64_t bist_enb : 1;
2038 uint64_t vtest_enb : 1;
2039 uint64_t loop_enb : 1;
2040 uint64_t tx_bs_en : 1;
2041 uint64_t tx_bs_enh : 1;
2042 uint64_t tuning : 4;
2043 uint64_t hst_mode : 1;
2044 uint64_t dm_pulld : 1;
2045 uint64_t dp_pulld : 1;
2046 uint64_t tclk : 1;
2047 uint64_t usbp_bist : 1;
2048 uint64_t usbc_end : 1;
2049 uint64_t dma_bmode : 1;
2050 uint64_t reserved_30_31 : 2;
2051 uint64_t tdata_out : 4;
2052 uint64_t bist_err : 1;
2053 uint64_t bist_done : 1;
2054 uint64_t reserved_38_63 : 26;
2060 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
2061 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
2062 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
2063 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
2064 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
2065 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
2066 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
2067 uint64_t otgdisable : 1; /**< OTG Block Disable */
2068 uint64_t portreset : 1; /**< Per_Port Reset */
2069 uint64_t drvvbus : 1; /**< Drive VBUS */
2070 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
2071 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
2072 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
2073 uint64_t bist_done : 1; /**< PHY Bist Done.
2075 uint64_t bist_err : 1; /**< PHY Bist Error.
2078 uint64_t tdata_out : 4; /**< PHY Test Data Out.
2082 uint64_t reserved_31_31 : 1;
2083 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
2084 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
2088 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
2090 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
2091 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
2092 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
2100 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
2108 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
2111 uint64_t reserved_19_22 : 4;
2112 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
2115 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
2118 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
2124 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
2128 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
2130 uint64_t tdata_sel : 1; /**< Test Data Out Select.
2134 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
2137 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
2141 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
2152 uint64_t ate_reset : 1;
2153 uint64_t tdata_in : 8;
2154 uint64_t taddr_in : 4;
2155 uint64_t tdata_sel : 1;
2156 uint64_t bist_enb : 1;
2157 uint64_t vtest_enb : 1;
2158 uint64_t loop_enb : 1;
2159 uint64_t tx_bs_en : 1;
2160 uint64_t tx_bs_enh : 1;
2161 uint64_t reserved_19_22 : 4;
2162 uint64_t hst_mode : 1;
2163 uint64_t dm_pulld : 1;
2164 uint64_t dp_pulld : 1;
2165 uint64_t tclk : 1;
2166 uint64_t usbp_bist : 1;
2167 uint64_t usbc_end : 1;
2168 uint64_t dma_bmode : 1;
2169 uint64_t txpreemphasistune : 1;
2170 uint64_t reserved_31_31 : 1;
2171 uint64_t tdata_out : 4;
2172 uint64_t bist_err : 1;
2173 uint64_t bist_done : 1;
2174 uint64_t hsbist : 1;
2175 uint64_t fsbist : 1;
2176 uint64_t lsbist : 1;
2177 uint64_t drvvbus : 1;
2178 uint64_t portreset : 1;
2179 uint64_t otgdisable : 1;
2180 uint64_t otgtune : 3;
2181 uint64_t compdistune : 3;
2182 uint64_t sqrxtune : 3;
2183 uint64_t txhsxvtune : 2;
2184 uint64_t txfslstune : 4;
2185 uint64_t txvreftune : 4;
2186 uint64_t txrisetune : 1;
2191 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
2192 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
2193 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
2194 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
2195 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
2196 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
2197 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
2198 uint64_t otgdisable : 1; /**< OTG Block Disable */
2199 uint64_t portreset : 1; /**< Per_Port Reset */
2200 uint64_t drvvbus : 1; /**< Drive VBUS */
2201 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
2202 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
2203 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
2204 uint64_t bist_done : 1; /**< PHY Bist Done.
2206 uint64_t bist_err : 1; /**< PHY Bist Error.
2209 uint64_t tdata_out : 4; /**< PHY Test Data Out.
2213 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
2220 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
2221 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
2225 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
2227 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
2228 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
2229 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
2237 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
2245 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
2248 uint64_t reserved_19_22 : 4;
2249 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
2252 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
2255 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
2261 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
2265 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
2267 uint64_t tdata_sel : 1; /**< Test Data Out Select.
2271 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
2274 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
2278 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
2289 uint64_t ate_reset : 1;
2290 uint64_t tdata_in : 8;
2291 uint64_t taddr_in : 4;
2292 uint64_t tdata_sel : 1;
2293 uint64_t bist_enb : 1;
2294 uint64_t vtest_enb : 1;
2295 uint64_t loop_enb : 1;
2296 uint64_t tx_bs_en : 1;
2297 uint64_t tx_bs_enh : 1;
2298 uint64_t reserved_19_22 : 4;
2299 uint64_t hst_mode : 1;
2300 uint64_t dm_pulld : 1;
2301 uint64_t dp_pulld : 1;
2302 uint64_t tclk : 1;
2303 uint64_t usbp_bist : 1;
2304 uint64_t usbc_end : 1;
2305 uint64_t dma_bmode : 1;
2306 uint64_t txpreemphasistune : 1;
2307 uint64_t siddq : 1;
2308 uint64_t tdata_out : 4;
2309 uint64_t bist_err : 1;
2310 uint64_t bist_done : 1;
2311 uint64_t hsbist : 1;
2312 uint64_t fsbist : 1;
2313 uint64_t lsbist : 1;
2314 uint64_t drvvbus : 1;
2315 uint64_t portreset : 1;
2316 uint64_t otgdisable : 1;
2317 uint64_t otgtune : 3;
2318 uint64_t compdistune : 3;
2319 uint64_t sqrxtune : 3;
2320 uint64_t txhsxvtune : 2;
2321 uint64_t txfslstune : 4;
2322 uint64_t txvreftune : 4;
2323 uint64_t txrisetune : 1;