Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
67 static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
83 static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
94 static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
105 static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
116 static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
126 static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
141 static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
156 static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
172 static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
182 static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
198 static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
209 static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
220 static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
231 static inline uint64_t CVMX_SLI_LAST_WIN_RDATA2_FUNC(void)
242 static inline uint64_t CVMX_SLI_LAST_WIN_RDATA3_FUNC(void)
253 static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
264 static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void)
275 static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
286 static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
296 static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
312 static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
323 static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
334 static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
345 static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
356 static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
367 static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
378 static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
389 static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
400 static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
411 static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
422 static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
433 static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
444 static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
455 static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
466 static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
477 static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
488 static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
499 static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
510 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
521 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
532 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
543 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
553 static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
568 static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
583 static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
598 static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
613 static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
628 static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
642 static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
657 static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
672 static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
687 static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
703 static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
714 static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
725 static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
736 static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
747 static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
758 static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
769 static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
780 static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
791 static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
802 static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
813 static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
824 static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
835 static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
845 static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
861 static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
872 static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
883 static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
894 static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
905 static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
916 static inline uint64_t CVMX_SLI_PKT_OUT_BP_EN_FUNC(void)
927 static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
938 static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
949 static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
960 static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
971 static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
982 static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
993 static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
1004 static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
1014 static inline uint64_t CVMX_SLI_PORTX_PKIND(unsigned long offset)
1025 static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
1041 static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
1052 static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
1063 static inline uint64_t CVMX_SLI_STATE1_FUNC(void)
1074 static inline uint64_t CVMX_SLI_STATE2_FUNC(void)
1085 static inline uint64_t CVMX_SLI_STATE3_FUNC(void)
1096 static inline uint64_t CVMX_SLI_TX_PIPE_FUNC(void)
1107 static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
1118 static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
1129 static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
1140 static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
1151 static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
1162 static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
1180 uint64_t u64;
1183 uint64_t reserved_32_63 : 32;
1184 uint64_t ncb_req : 1; /**< BIST Status for NCB Request FIFO */
1185 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1186 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1187 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1188 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1189 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1190 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1191 uint64_t reserved_19_24 : 6;
1192 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1193 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1194 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1195 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1196 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1197 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1198 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1199 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1200 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1201 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1202 uint64_t reserved_6_8 : 3;
1203 uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */
1204 uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */
1205 uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */
1206 uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */
1207 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1208 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1210 uint64_t ncb_cmd : 1;
1211 uint64_t msi : 1;
1212 uint64_t dsi0_0 : 1;
1213 uint64_t dsi0_1 : 1;
1214 uint64_t dsi1_0 : 1;
1215 uint64_t dsi1_1 : 1;
1216 uint64_t reserved_6_8 : 3;
1217 uint64_t p2n1_p1 : 1;
1218 uint64_t p2n1_p0 : 1;
1219 uint64_t p2n1_n : 1;
1220 uint64_t p2n1_c1 : 1;
1221 uint64_t p2n1_c0 : 1;
1222 uint64_t p2n0_p1 : 1;
1223 uint64_t p2n0_p0 : 1;
1224 uint64_t p2n0_n : 1;
1225 uint64_t p2n0_c1 : 1;
1226 uint64_t p2n0_c0 : 1;
1227 uint64_t reserved_19_24 : 6;
1228 uint64_t cpl_p1 : 1;
1229 uint64_t cpl_p0 : 1;
1230 uint64_t n2p1_o : 1;
1231 uint64_t n2p1_c : 1;
1232 uint64_t n2p0_o : 1;
1233 uint64_t n2p0_c : 1;
1234 uint64_t ncb_req : 1;
1235 uint64_t reserved_32_63 : 32;
1240 uint64_t reserved_31_63 : 33;
1241 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1242 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1243 uint64_t reserved_27_28 : 2;
1244 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1245 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1246 uint64_t reserved_19_24 : 6;
1247 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1248 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1249 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1250 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1251 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1252 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1253 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1254 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1255 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1256 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1257 uint64_t reserved_6_8 : 3;
1258 uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */
1259 uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */
1260 uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */
1261 uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */
1262 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1263 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1265 uint64_t ncb_cmd : 1;
1266 uint64_t msi : 1;
1267 uint64_t dsi0_0 : 1;
1268 uint64_t dsi0_1 : 1;
1269 uint64_t dsi1_0 : 1;
1270 uint64_t dsi1_1 : 1;
1271 uint64_t reserved_6_8 : 3;
1272 uint64_t p2n1_p1 : 1;
1273 uint64_t p2n1_p0 : 1;
1274 uint64_t p2n1_n : 1;
1275 uint64_t p2n1_c1 : 1;
1276 uint64_t p2n1_c0 : 1;
1277 uint64_t p2n0_p1 : 1;
1278 uint64_t p2n0_p0 : 1;
1279 uint64_t p2n0_n : 1;
1280 uint64_t p2n0_c1 : 1;
1281 uint64_t p2n0_c0 : 1;
1282 uint64_t reserved_19_24 : 6;
1283 uint64_t cpl_p1 : 1;
1284 uint64_t cpl_p0 : 1;
1285 uint64_t reserved_27_28 : 2;
1286 uint64_t n2p0_o : 1;
1287 uint64_t n2p0_c : 1;
1288 uint64_t reserved_31_63 : 33;
1293 uint64_t reserved_31_63 : 33;
1294 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1295 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1296 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1297 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1298 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1299 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1300 uint64_t reserved_19_24 : 6;
1301 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1302 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1303 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1304 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1305 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1306 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1307 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1308 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1309 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1310 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1311 uint64_t reserved_6_8 : 3;
1312 uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */
1313 uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */
1314 uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */
1315 uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */
1316 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1317 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1319 uint64_t ncb_cmd : 1;
1320 uint64_t msi : 1;
1321 uint64_t dsi0_0 : 1;
1322 uint64_t dsi0_1 : 1;
1323 uint64_t dsi1_0 : 1;
1324 uint64_t dsi1_1 : 1;
1325 uint64_t reserved_6_8 : 3;
1326 uint64_t p2n1_p1 : 1;
1327 uint64_t p2n1_p0 : 1;
1328 uint64_t p2n1_n : 1;
1329 uint64_t p2n1_c1 : 1;
1330 uint64_t p2n1_c0 : 1;
1331 uint64_t p2n0_p1 : 1;
1332 uint64_t p2n0_p0 : 1;
1333 uint64_t p2n0_n : 1;
1334 uint64_t p2n0_c1 : 1;
1335 uint64_t p2n0_c0 : 1;
1336 uint64_t reserved_19_24 : 6;
1337 uint64_t cpl_p1 : 1;
1338 uint64_t cpl_p0 : 1;
1339 uint64_t n2p1_o : 1;
1340 uint64_t n2p1_c : 1;
1341 uint64_t n2p0_o : 1;
1342 uint64_t n2p0_c : 1;
1343 uint64_t reserved_31_63 : 33;
1362 uint64_t u64;
1365 uint64_t reserved_22_63 : 42;
1366 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */
1367 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */
1368 uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */
1369 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */
1370 uint64_t dis_port : 1; /**< When set the output to the MAC is disabled. This
1376 uint64_t waitl_com : 1; /**< When set '1' casues the SLI to wait for a commit
1382 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
1384 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
1386 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
1388 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
1390 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */
1391 uint64_t reserved_6_6 : 1;
1392 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */
1393 uint64_t reserved_1_4 : 4;
1394 uint64_t wait_com : 1; /**< When set '1' casues the SLI to wait for a commit
1404 uint64_t wait_com : 1;
1405 uint64_t reserved_1_4 : 4;
1406 uint64_t ptlp_ro : 1;
1407 uint64_t reserved_6_6 : 1;
1408 uint64_t ctlp_ro : 1;
1409 uint64_t inta_map : 2;
1410 uint64_t intb_map : 2;
1411 uint64_t intc_map : 2;
1412 uint64_t intd_map : 2;
1413 uint64_t waitl_com : 1;
1414 uint64_t dis_port : 1;
1415 uint64_t inta : 1;
1416 uint64_t intb : 1;
1417 uint64_t intc : 1;
1418 uint64_t intd : 1;
1419 uint64_t reserved_22_63 : 42;
1442 uint64_t u64;
1445 uint64_t reserved_20_63 : 44;
1446 uint64_t p1_ntags : 6; /**< Number of tags available for MAC Port1.
1454 uint64_t p0_ntags : 6; /**< Number of tags available for outbound TLPs to the
1460 uint64_t chip_rev : 8; /**< The chip revision. */
1462 uint64_t chip_rev : 8;
1463 uint64_t p0_ntags : 6;
1464 uint64_t p1_ntags : 6;
1465 uint64_t reserved_20_63 : 44;
1470 uint64_t reserved_14_63 : 50;
1471 uint64_t p0_ntags : 6; /**< Number of tags available for outbound TLPs to the
1477 uint64_t chip_rev : 8; /**< The chip revision. */
1479 uint64_t chip_rev : 8;
1480 uint64_t p0_ntags : 6;
1481 uint64_t reserved_14_63 : 50;
1501 uint64_t u64;
1504 uint64_t reserved_44_63 : 20;
1505 uint64_t p1_ucnt : 16; /**< SLI Order-FIFO1 Fifo Unload Count. This counter is
1509 uint64_t p1_fcnt : 6; /**< SLI Order-FIFO1 Data Out Fifo Count. Number of
1512 uint64_t p0_ucnt : 16; /**< SLI Order-FIFO0 Fifo Unload Count. This counter is
1516 uint64_t p0_fcnt : 6; /**< SLI Order-FIFO0 Data Out Fifo Count. Number of
1520 uint64_t p0_fcnt : 6;
1521 uint64_t p0_ucnt : 16;
1522 uint64_t p1_fcnt : 6;
1523 uint64_t p1_ucnt : 16;
1524 uint64_t reserved_44_63 : 20;
1545 uint64_t u64;
1548 uint64_t reserved_18_63 : 46;
1549 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
1551 uint64_t data : 17; /**< Value on the debug data lines. */
1553 uint64_t data : 17;
1554 uint64_t dsel_ext : 1;
1555 uint64_t reserved_18_63 : 46;
1576 uint64_t u64;
1579 uint64_t reserved_33_63 : 31;
1580 uint64_t adbg_sel : 1; /**< When set '1' the SLI_DBG_DATA[DATA] will only be
1584 uint64_t dbg_sel : 32; /**< When this register is written the RML will write
1597 uint64_t dbg_sel : 32;
1598 uint64_t adbg_sel : 1;
1599 uint64_t reserved_33_63 : 31;
1620 uint64_t u64;
1623 uint64_t reserved_32_63 : 32;
1624 uint64_t cnt : 32; /**< The DMA counter.
1632 uint64_t cnt : 32;
1633 uint64_t reserved_32_63 : 32;
1654 uint64_t u64;
1657 uint64_t time : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds
1663 uint64_t cnt : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value,
1666 uint64_t cnt : 32;
1667 uint64_t time : 32;
1688 uint64_t u64;
1691 uint64_t reserved_32_63 : 32;
1692 uint64_t tim : 32; /**< The DMA timer value.
1696 uint64_t tim : 32;
1697 uint64_t reserved_32_63 : 32;
1718 uint64_t u64;
1721 uint64_t reserved_62_63 : 2;
1722 uint64_t pipe_err : 1; /**< Illegal packet csr address. */
1723 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
1724 uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */
1725 uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */
1726 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
1727 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
1728 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
1729 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
1730 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
1731 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
1732 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
1733 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
1734 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
1735 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
1736 uint64_t reserved_38_47 : 10;
1737 uint64_t dtime : 2; /**< DMA Timer Interrupts */
1738 uint64_t dcnt : 2; /**< DMA Count Interrupts */
1739 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
1740 uint64_t reserved_28_31 : 4;
1741 uint64_t m3_un_wi : 1; /**< Reserved. */
1742 uint64_t m3_un_b0 : 1; /**< Reserved. */
1743 uint64_t m3_up_wi : 1; /**< Reserved. */
1744 uint64_t m3_up_b0 : 1; /**< Reserved. */
1745 uint64_t m2_un_wi : 1; /**< Reserved. */
1746 uint64_t m2_un_b0 : 1; /**< Reserved. */
1747 uint64_t m2_up_wi : 1; /**< Reserved. */
1748 uint64_t m2_up_b0 : 1; /**< Reserved. */
1749 uint64_t reserved_18_19 : 2;
1750 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
1753 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
1756 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
1758 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
1760 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
1762 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
1764 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
1766 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
1768 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
1770 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
1772 uint64_t reserved_6_7 : 2;
1773 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
1775 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
1777 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
1779 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
1781 uint64_t reserved_1_1 : 1;
1782 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
1785 uint64_t rml_to : 1;
1786 uint64_t reserved_1_1 : 1;
1787 uint64_t bar0_to : 1;
1788 uint64_t iob2big : 1;
1789 uint64_t pcnt : 1;
1790 uint64_t ptime : 1;
1791 uint64_t reserved_6_7 : 2;
1792 uint64_t m0_up_b0 : 1;
1793 uint64_t m0_up_wi : 1;
1794 uint64_t m0_un_b0 : 1;
1795 uint64_t m0_un_wi : 1;
1796 uint64_t m1_up_b0 : 1;
1797 uint64_t m1_up_wi : 1;
1798 uint64_t m1_un_b0 : 1;
1799 uint64_t m1_un_wi : 1;
1800 uint64_t mio_int0 : 1;
1801 uint64_t mio_int1 : 1;
1802 uint64_t reserved_18_19 : 2;
1803 uint64_t m2_up_b0 : 1;
1804 uint64_t m2_up_wi : 1;
1805 uint64_t m2_un_b0 : 1;
1806 uint64_t m2_un_wi : 1;
1807 uint64_t m3_up_b0 : 1;
1808 uint64_t m3_up_wi : 1;
1809 uint64_t m3_un_b0 : 1;
1810 uint64_t m3_un_wi : 1;
1811 uint64_t reserved_28_31 : 4;
1812 uint64_t dmafi : 2;
1813 uint64_t dcnt : 2;
1814 uint64_t dtime : 2;
1815 uint64_t reserved_38_47 : 10;
1816 uint64_t pidbof : 1;
1817 uint64_t psldbof : 1;
1818 uint64_t pout_err : 1;
1819 uint64_t pin_bp : 1;
1820 uint64_t pgl_err : 1;
1821 uint64_t pdi_err : 1;
1822 uint64_t pop_err : 1;
1823 uint64_t pins_err : 1;
1824 uint64_t sprt0_err : 1;
1825 uint64_t sprt1_err : 1;
1826 uint64_t sprt2_err : 1;
1827 uint64_t sprt3_err : 1;
1828 uint64_t ill_pad : 1;
1829 uint64_t pipe_err : 1;
1830 uint64_t reserved_62_63 : 2;
1835 uint64_t reserved_61_63 : 3;
1836 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
1837 uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */
1838 uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */
1839 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
1840 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
1841 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
1842 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
1843 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
1844 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
1845 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
1846 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
1847 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
1848 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
1849 uint64_t reserved_38_47 : 10;
1850 uint64_t dtime : 2; /**< DMA Timer Interrupts */
1851 uint64_t dcnt : 2; /**< DMA Count Interrupts */
1852 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
1853 uint64_t reserved_28_31 : 4;
1854 uint64_t m3_un_wi : 1; /**< Reserved. */
1855 uint64_t m3_un_b0 : 1; /**< Reserved. */
1856 uint64_t m3_up_wi : 1; /**< Reserved. */
1857 uint64_t m3_up_b0 : 1; /**< Reserved. */
1858 uint64_t m2_un_wi : 1; /**< Reserved. */
1859 uint64_t m2_un_b0 : 1; /**< Reserved. */
1860 uint64_t m2_up_wi : 1; /**< Reserved. */
1861 uint64_t m2_up_b0 : 1; /**< Reserved. */
1862 uint64_t reserved_18_19 : 2;
1863 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
1866 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
1869 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
1871 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
1873 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
1875 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
1877 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
1879 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
1881 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
1883 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
1885 uint64_t reserved_6_7 : 2;
1886 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
1888 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
1890 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
1892 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
1894 uint64_t reserved_1_1 : 1;
1895 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
1898 uint64_t rml_to : 1;
1899 uint64_t reserved_1_1 : 1;
1900 uint64_t bar0_to : 1;
1901 uint64_t iob2big : 1;
1902 uint64_t pcnt : 1;
1903 uint64_t ptime : 1;
1904 uint64_t reserved_6_7 : 2;
1905 uint64_t m0_up_b0 : 1;
1906 uint64_t m0_up_wi : 1;
1907 uint64_t m0_un_b0 : 1;
1908 uint64_t m0_un_wi : 1;
1909 uint64_t m1_up_b0 : 1;
1910 uint64_t m1_up_wi : 1;
1911 uint64_t m1_un_b0 : 1;
1912 uint64_t m1_un_wi : 1;
1913 uint64_t mio_int0 : 1;
1914 uint64_t mio_int1 : 1;
1915 uint64_t reserved_18_19 : 2;
1916 uint64_t m2_up_b0 : 1;
1917 uint64_t m2_up_wi : 1;
1918 uint64_t m2_un_b0 : 1;
1919 uint64_t m2_un_wi : 1;
1920 uint64_t m3_up_b0 : 1;
1921 uint64_t m3_up_wi : 1;
1922 uint64_t m3_un_b0 : 1;
1923 uint64_t m3_un_wi : 1;
1924 uint64_t reserved_28_31 : 4;
1925 uint64_t dmafi : 2;
1926 uint64_t dcnt : 2;
1927 uint64_t dtime : 2;
1928 uint64_t reserved_38_47 : 10;
1929 uint64_t pidbof : 1;
1930 uint64_t psldbof : 1;
1931 uint64_t pout_err : 1;
1932 uint64_t pin_bp : 1;
1933 uint64_t pgl_err : 1;
1934 uint64_t pdi_err : 1;
1935 uint64_t pop_err : 1;
1936 uint64_t pins_err : 1;
1937 uint64_t sprt0_err : 1;
1938 uint64_t sprt1_err : 1;
1939 uint64_t sprt2_err : 1;
1940 uint64_t sprt3_err : 1;
1941 uint64_t ill_pad : 1;
1942 uint64_t reserved_61_63 : 3;
1947 uint64_t reserved_61_63 : 3;
1948 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
1949 uint64_t reserved_58_59 : 2;
1950 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
1951 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
1952 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
1953 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
1954 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
1955 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
1956 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
1957 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
1958 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
1959 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
1960 uint64_t reserved_38_47 : 10;
1961 uint64_t dtime : 2; /**< DMA Timer Interrupts */
1962 uint64_t dcnt : 2; /**< DMA Count Interrupts */
1963 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
1964 uint64_t reserved_18_31 : 14;
1965 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
1968 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
1971 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
1973 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
1975 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
1977 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
1979 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
1981 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
1983 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
1985 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
1987 uint64_t reserved_6_7 : 2;
1988 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
1990 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
1992 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
1994 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
1996 uint64_t reserved_1_1 : 1;
1997 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
2000 uint64_t rml_to : 1;
2001 uint64_t reserved_1_1 : 1;
2002 uint64_t bar0_to : 1;
2003 uint64_t iob2big : 1;
2004 uint64_t pcnt : 1;
2005 uint64_t ptime : 1;
2006 uint64_t reserved_6_7 : 2;
2007 uint64_t m0_up_b0 : 1;
2008 uint64_t m0_up_wi : 1;
2009 uint64_t m0_un_b0 : 1;
2010 uint64_t m0_un_wi : 1;
2011 uint64_t m1_up_b0 : 1;
2012 uint64_t m1_up_wi : 1;
2013 uint64_t m1_un_b0 : 1;
2014 uint64_t m1_un_wi : 1;
2015 uint64_t mio_int0 : 1;
2016 uint64_t mio_int1 : 1;
2017 uint64_t reserved_18_31 : 14;
2018 uint64_t dmafi : 2;
2019 uint64_t dcnt : 2;
2020 uint64_t dtime : 2;
2021 uint64_t reserved_38_47 : 10;
2022 uint64_t pidbof : 1;
2023 uint64_t psldbof : 1;
2024 uint64_t pout_err : 1;
2025 uint64_t pin_bp : 1;
2026 uint64_t pgl_err : 1;
2027 uint64_t pdi_err : 1;
2028 uint64_t pop_err : 1;
2029 uint64_t pins_err : 1;
2030 uint64_t sprt0_err : 1;
2031 uint64_t sprt1_err : 1;
2032 uint64_t reserved_58_59 : 2;
2033 uint64_t ill_pad : 1;
2034 uint64_t reserved_61_63 : 3;
2041 uint64_t reserved_62_63 : 2;
2042 uint64_t pipe_err : 1; /**< Illegal packet csr address. */
2043 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2044 uint64_t reserved_58_59 : 2;
2045 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
2046 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
2047 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
2048 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
2049 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
2050 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
2051 uint64_t reserved_51_51 : 1;
2052 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
2053 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
2054 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
2055 uint64_t reserved_38_47 : 10;
2056 uint64_t dtime : 2; /**< DMA Timer Interrupts */
2057 uint64_t dcnt : 2; /**< DMA Count Interrupts */
2058 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
2059 uint64_t reserved_18_31 : 14;
2060 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
2063 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
2066 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
2068 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
2070 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
2072 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
2074 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
2076 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
2078 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
2080 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
2082 uint64_t reserved_6_7 : 2;
2083 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
2085 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
2087 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
2089 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
2091 uint64_t reserved_1_1 : 1;
2092 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
2095 uint64_t rml_to : 1;
2096 uint64_t reserved_1_1 : 1;
2097 uint64_t bar0_to : 1;
2098 uint64_t iob2big : 1;
2099 uint64_t pcnt : 1;
2100 uint64_t ptime : 1;
2101 uint64_t reserved_6_7 : 2;
2102 uint64_t m0_up_b0 : 1;
2103 uint64_t m0_up_wi : 1;
2104 uint64_t m0_un_b0 : 1;
2105 uint64_t m0_un_wi : 1;
2106 uint64_t m1_up_b0 : 1;
2107 uint64_t m1_up_wi : 1;
2108 uint64_t m1_un_b0 : 1;
2109 uint64_t m1_un_wi : 1;
2110 uint64_t mio_int0 : 1;
2111 uint64_t mio_int1 : 1;
2112 uint64_t reserved_18_31 : 14;
2113 uint64_t dmafi : 2;
2114 uint64_t dcnt : 2;
2115 uint64_t dtime : 2;
2116 uint64_t reserved_38_47 : 10;
2117 uint64_t pidbof : 1;
2118 uint64_t psldbof : 1;
2119 uint64_t pout_err : 1;
2120 uint64_t reserved_51_51 : 1;
2121 uint64_t pgl_err : 1;
2122 uint64_t pdi_err : 1;
2123 uint64_t pop_err : 1;
2124 uint64_t pins_err : 1;
2125 uint64_t sprt0_err : 1;
2126 uint64_t sprt1_err : 1;
2127 uint64_t reserved_58_59 : 2;
2128 uint64_t ill_pad : 1;
2129 uint64_t pipe_err : 1;
2130 uint64_t reserved_62_63 : 2;
2150 uint64_t u64;
2153 uint64_t reserved_62_63 : 2;
2154 uint64_t pipe_err : 1; /**< Out of range PIPE value. */
2155 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2156 uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */
2157 uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */
2158 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
2159 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
2160 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
2161 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
2162 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
2163 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
2164 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
2165 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
2166 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
2167 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
2168 uint64_t reserved_38_47 : 10;
2169 uint64_t dtime : 2; /**< DMA Timer Interrupts */
2170 uint64_t dcnt : 2; /**< DMA Count Interrupts */
2171 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
2172 uint64_t reserved_28_31 : 4;
2173 uint64_t m3_un_wi : 1; /**< Reserved. */
2174 uint64_t m3_un_b0 : 1; /**< Reserved. */
2175 uint64_t m3_up_wi : 1; /**< Reserved. */
2176 uint64_t m3_up_b0 : 1; /**< Reserved. */
2177 uint64_t m2_un_wi : 1; /**< Reserved. */
2178 uint64_t m2_un_b0 : 1; /**< Reserved. */
2179 uint64_t m2_up_wi : 1; /**< Reserved. */
2180 uint64_t m2_up_b0 : 1; /**< Reserved. */
2181 uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an
2185 uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an
2189 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
2192 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
2195 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
2197 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
2199 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
2201 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
2203 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
2205 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
2207 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
2209 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
2211 uint64_t reserved_6_7 : 2;
2212 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
2214 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
2216 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
2218 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
2220 uint64_t reserved_1_1 : 1;
2221 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
2224 uint64_t rml_to : 1;
2225 uint64_t reserved_1_1 : 1;
2226 uint64_t bar0_to : 1;
2227 uint64_t iob2big : 1;
2228 uint64_t pcnt : 1;
2229 uint64_t ptime : 1;
2230 uint64_t reserved_6_7 : 2;
2231 uint64_t m0_up_b0 : 1;
2232 uint64_t m0_up_wi : 1;
2233 uint64_t m0_un_b0 : 1;
2234 uint64_t m0_un_wi : 1;
2235 uint64_t m1_up_b0 : 1;
2236 uint64_t m1_up_wi : 1;
2237 uint64_t m1_un_b0 : 1;
2238 uint64_t m1_un_wi : 1;
2239 uint64_t mio_int0 : 1;
2240 uint64_t mio_int1 : 1;
2241 uint64_t mac0_int : 1;
2242 uint64_t mac1_int : 1;
2243 uint64_t m2_up_b0 : 1;
2244 uint64_t m2_up_wi : 1;
2245 uint64_t m2_un_b0 : 1;
2246 uint64_t m2_un_wi : 1;
2247 uint64_t m3_up_b0 : 1;
2248 uint64_t m3_up_wi : 1;
2249 uint64_t m3_un_b0 : 1;
2250 uint64_t m3_un_wi : 1;
2251 uint64_t reserved_28_31 : 4;
2252 uint64_t dmafi : 2;
2253 uint64_t dcnt : 2;
2254 uint64_t dtime : 2;
2255 uint64_t reserved_38_47 : 10;
2256 uint64_t pidbof : 1;
2257 uint64_t psldbof : 1;
2258 uint64_t pout_err : 1;
2259 uint64_t pin_bp : 1;
2260 uint64_t pgl_err : 1;
2261 uint64_t pdi_err : 1;
2262 uint64_t pop_err : 1;
2263 uint64_t pins_err : 1;
2264 uint64_t sprt0_err : 1;
2265 uint64_t sprt1_err : 1;
2266 uint64_t sprt2_err : 1;
2267 uint64_t sprt3_err : 1;
2268 uint64_t ill_pad : 1;
2269 uint64_t pipe_err : 1;
2270 uint64_t reserved_62_63 : 2;
2275 uint64_t reserved_61_63 : 3;
2276 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2277 uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */
2278 uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */
2279 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
2280 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
2281 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
2282 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
2283 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
2284 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
2285 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
2286 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
2287 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
2288 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
2289 uint64_t reserved_38_47 : 10;
2290 uint64_t dtime : 2; /**< DMA Timer Interrupts */
2291 uint64_t dcnt : 2; /**< DMA Count Interrupts */
2292 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
2293 uint64_t reserved_28_31 : 4;
2294 uint64_t m3_un_wi : 1; /**< Reserved. */
2295 uint64_t m3_un_b0 : 1; /**< Reserved. */
2296 uint64_t m3_up_wi : 1; /**< Reserved. */
2297 uint64_t m3_up_b0 : 1; /**< Reserved. */
2298 uint64_t m2_un_wi : 1; /**< Reserved. */
2299 uint64_t m2_un_b0 : 1; /**< Reserved. */
2300 uint64_t m2_up_wi : 1; /**< Reserved. */
2301 uint64_t m2_up_b0 : 1; /**< Reserved. */
2302 uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an
2306 uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an
2310 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
2313 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
2316 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
2318 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
2320 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
2322 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
2324 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
2326 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
2328 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
2330 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
2332 uint64_t reserved_6_7 : 2;
2333 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
2335 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
2337 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
2339 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
2341 uint64_t reserved_1_1 : 1;
2342 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
2345 uint64_t rml_to : 1;
2346 uint64_t reserved_1_1 : 1;
2347 uint64_t bar0_to : 1;
2348 uint64_t iob2big : 1;
2349 uint64_t pcnt : 1;
2350 uint64_t ptime : 1;
2351 uint64_t reserved_6_7 : 2;
2352 uint64_t m0_up_b0 : 1;
2353 uint64_t m0_up_wi : 1;
2354 uint64_t m0_un_b0 : 1;
2355 uint64_t m0_un_wi : 1;
2356 uint64_t m1_up_b0 : 1;
2357 uint64_t m1_up_wi : 1;
2358 uint64_t m1_un_b0 : 1;
2359 uint64_t m1_un_wi : 1;
2360 uint64_t mio_int0 : 1;
2361 uint64_t mio_int1 : 1;
2362 uint64_t mac0_int : 1;
2363 uint64_t mac1_int : 1;
2364 uint64_t m2_up_b0 : 1;
2365 uint64_t m2_up_wi : 1;
2366 uint64_t m2_un_b0 : 1;
2367 uint64_t m2_un_wi : 1;
2368 uint64_t m3_up_b0 : 1;
2369 uint64_t m3_up_wi : 1;
2370 uint64_t m3_un_b0 : 1;
2371 uint64_t m3_un_wi : 1;
2372 uint64_t reserved_28_31 : 4;
2373 uint64_t dmafi : 2;
2374 uint64_t dcnt : 2;
2375 uint64_t dtime : 2;
2376 uint64_t reserved_38_47 : 10;
2377 uint64_t pidbof : 1;
2378 uint64_t psldbof : 1;
2379 uint64_t pout_err : 1;
2380 uint64_t pin_bp : 1;
2381 uint64_t pgl_err : 1;
2382 uint64_t pdi_err : 1;
2383 uint64_t pop_err : 1;
2384 uint64_t pins_err : 1;
2385 uint64_t sprt0_err : 1;
2386 uint64_t sprt1_err : 1;
2387 uint64_t sprt2_err : 1;
2388 uint64_t sprt3_err : 1;
2389 uint64_t ill_pad : 1;
2390 uint64_t reserved_61_63 : 3;
2395 uint64_t reserved_61_63 : 3;
2396 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2397 uint64_t reserved_58_59 : 2;
2398 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
2399 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
2400 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
2401 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
2402 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
2403 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
2404 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
2405 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
2406 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
2407 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
2408 uint64_t reserved_38_47 : 10;
2409 uint64_t dtime : 2; /**< DMA Timer Interrupts */
2410 uint64_t dcnt : 2; /**< DMA Count Interrupts */
2411 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
2412 uint64_t reserved_20_31 : 12;
2413 uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an
2417 uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an
2421 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
2424 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
2427 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
2429 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
2431 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
2433 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
2435 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
2437 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
2439 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
2441 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
2443 uint64_t reserved_6_7 : 2;
2444 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
2446 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
2448 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
2450 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
2452 uint64_t reserved_1_1 : 1;
2453 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
2456 uint64_t rml_to : 1;
2457 uint64_t reserved_1_1 : 1;
2458 uint64_t bar0_to : 1;
2459 uint64_t iob2big : 1;
2460 uint64_t pcnt : 1;
2461 uint64_t ptime : 1;
2462 uint64_t reserved_6_7 : 2;
2463 uint64_t m0_up_b0 : 1;
2464 uint64_t m0_up_wi : 1;
2465 uint64_t m0_un_b0 : 1;
2466 uint64_t m0_un_wi : 1;
2467 uint64_t m1_up_b0 : 1;
2468 uint64_t m1_up_wi : 1;
2469 uint64_t m1_un_b0 : 1;
2470 uint64_t m1_un_wi : 1;
2471 uint64_t mio_int0 : 1;
2472 uint64_t mio_int1 : 1;
2473 uint64_t mac0_int : 1;
2474 uint64_t mac1_int : 1;
2475 uint64_t reserved_20_31 : 12;
2476 uint64_t dmafi : 2;
2477 uint64_t dcnt : 2;
2478 uint64_t dtime : 2;
2479 uint64_t reserved_38_47 : 10;
2480 uint64_t pidbof : 1;
2481 uint64_t psldbof : 1;
2482 uint64_t pout_err : 1;
2483 uint64_t pin_bp : 1;
2484 uint64_t pgl_err : 1;
2485 uint64_t pdi_err : 1;
2486 uint64_t pop_err : 1;
2487 uint64_t pins_err : 1;
2488 uint64_t sprt0_err : 1;
2489 uint64_t sprt1_err : 1;
2490 uint64_t reserved_58_59 : 2;
2491 uint64_t ill_pad : 1;
2492 uint64_t reserved_61_63 : 3;
2499 uint64_t reserved_62_63 : 2;
2500 uint64_t pipe_err : 1; /**< Out of range PIPE value. */
2501 uint64_t ill_pad : 1; /**< Illegal packet csr address. */
2502 uint64_t reserved_58_59 : 2;
2503 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
2504 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
2505 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
2506 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
2507 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
2508 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
2509 uint64_t reserved_51_51 : 1;
2510 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
2511 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
2512 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
2513 uint64_t reserved_38_47 : 10;
2514 uint64_t dtime : 2; /**< DMA Timer Interrupts */
2515 uint64_t dcnt : 2; /**< DMA Count Interrupts */
2516 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
2517 uint64_t reserved_20_31 : 12;
2518 uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an
2522 uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an
2526 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
2529 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
2532 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
2534 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
2536 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
2538 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
2540 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
2542 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
2544 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
2546 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
2548 uint64_t reserved_6_7 : 2;
2549 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
2551 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
2553 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
2555 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
2557 uint64_t reserved_1_1 : 1;
2558 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
2561 uint64_t rml_to : 1;
2562 uint64_t reserved_1_1 : 1;
2563 uint64_t bar0_to : 1;
2564 uint64_t iob2big : 1;
2565 uint64_t pcnt : 1;
2566 uint64_t ptime : 1;
2567 uint64_t reserved_6_7 : 2;
2568 uint64_t m0_up_b0 : 1;
2569 uint64_t m0_up_wi : 1;
2570 uint64_t m0_un_b0 : 1;
2571 uint64_t m0_un_wi : 1;
2572 uint64_t m1_up_b0 : 1;
2573 uint64_t m1_up_wi : 1;
2574 uint64_t m1_un_b0 : 1;
2575 uint64_t m1_un_wi : 1;
2576 uint64_t mio_int0 : 1;
2577 uint64_t mio_int1 : 1;
2578 uint64_t mac0_int : 1;
2579 uint64_t mac1_int : 1;
2580 uint64_t reserved_20_31 : 12;
2581 uint64_t dmafi : 2;
2582 uint64_t dcnt : 2;
2583 uint64_t dtime : 2;
2584 uint64_t reserved_38_47 : 10;
2585 uint64_t pidbof : 1;
2586 uint64_t psldbof : 1;
2587 uint64_t pout_err : 1;
2588 uint64_t reserved_51_51 : 1;
2589 uint64_t pgl_err : 1;
2590 uint64_t pdi_err : 1;
2591 uint64_t pop_err : 1;
2592 uint64_t pins_err : 1;
2593 uint64_t sprt0_err : 1;
2594 uint64_t sprt1_err : 1;
2595 uint64_t reserved_58_59 : 2;
2596 uint64_t ill_pad : 1;
2597 uint64_t pipe_err : 1;
2598 uint64_t reserved_62_63 : 2;
2614 uint64_t u64;
2617 uint64_t reserved_62_63 : 2;
2618 uint64_t pipe_err : 1; /**< Set when a PIPE value outside range is received. */
2619 uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress
2622 uint64_t sprt3_err : 1; /**< Reserved. */
2623 uint64_t sprt2_err : 1; /**< Reserved. */
2624 uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1
2626 uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0
2628 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
2630 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
2632 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
2634 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
2636 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK.
2638 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
2640 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
2642 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
2644 uint64_t reserved_38_47 : 10;
2645 uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
2653 uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
2657 uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */
2658 uint64_t reserved_28_31 : 4;
2659 uint64_t m3_un_wi : 1; /**< Reserved. */
2660 uint64_t m3_un_b0 : 1; /**< Reserved. */
2661 uint64_t m3_up_wi : 1; /**< Reserved. */
2662 uint64_t m3_up_b0 : 1; /**< Reserved. */
2663 uint64_t m2_un_wi : 1; /**< Reserved. */
2664 uint64_t m2_un_b0 : 1; /**< Reserved. */
2665 uint64_t m2_up_wi : 1; /**< Reserved. */
2666 uint64_t m2_up_b0 : 1; /**< Reserved. */
2667 uint64_t mac1_int : 1; /**< Interrupt from MAC1.
2669 uint64_t mac0_int : 1; /**< Interrupt from MAC0.
2671 uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1.
2674 uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0.
2677 uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
2680 uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1.
2683 uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
2686 uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1.
2689 uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
2692 uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0.
2695 uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
2698 uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0.
2701 uint64_t reserved_6_7 : 2;
2702 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
2704 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
2706 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
2707 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
2709 uint64_t reserved_1_1 : 1;
2710 uint64_t rml_to : 1; /**< A read or write transfer did not complete
2713 uint64_t rml_to : 1;
2714 uint64_t reserved_1_1 : 1;
2715 uint64_t bar0_to : 1;
2716 uint64_t iob2big : 1;
2717 uint64_t pcnt : 1;
2718 uint64_t ptime : 1;
2719 uint64_t reserved_6_7 : 2;
2720 uint64_t m0_up_b0 : 1;
2721 uint64_t m0_up_wi : 1;
2722 uint64_t m0_un_b0 : 1;
2723 uint64_t m0_un_wi : 1;
2724 uint64_t m1_up_b0 : 1;
2725 uint64_t m1_up_wi : 1;
2726 uint64_t m1_un_b0 : 1;
2727 uint64_t m1_un_wi : 1;
2728 uint64_t mio_int0 : 1;
2729 uint64_t mio_int1 : 1;
2730 uint64_t mac0_int : 1;
2731 uint64_t mac1_int : 1;
2732 uint64_t m2_up_b0 : 1;
2733 uint64_t m2_up_wi : 1;
2734 uint64_t m2_un_b0 : 1;
2735 uint64_t m2_un_wi : 1;
2736 uint64_t m3_up_b0 : 1;
2737 uint64_t m3_up_wi : 1;
2738 uint64_t m3_un_b0 : 1;
2739 uint64_t m3_un_wi : 1;
2740 uint64_t reserved_28_31 : 4;
2741 uint64_t dmafi : 2;
2742 uint64_t dcnt : 2;
2743 uint64_t dtime : 2;
2744 uint64_t reserved_38_47 : 10;
2745 uint64_t pidbof : 1;
2746 uint64_t psldbof : 1;
2747 uint64_t pout_err : 1;
2748 uint64_t pin_bp : 1;
2749 uint64_t pgl_err : 1;
2750 uint64_t pdi_err : 1;
2751 uint64_t pop_err : 1;
2752 uint64_t pins_err : 1;
2753 uint64_t sprt0_err : 1;
2754 uint64_t sprt1_err : 1;
2755 uint64_t sprt2_err : 1;
2756 uint64_t sprt3_err : 1;
2757 uint64_t ill_pad : 1;
2758 uint64_t pipe_err : 1;
2759 uint64_t reserved_62_63 : 2;
2764 uint64_t reserved_61_63 : 3;
2765 uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress
2768 uint64_t sprt3_err : 1; /**< Reserved. */
2769 uint64_t sprt2_err : 1; /**< Reserved. */
2770 uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1
2772 uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0
2774 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
2776 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
2778 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
2780 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
2782 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK.
2784 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
2786 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
2788 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
2790 uint64_t reserved_38_47 : 10;
2791 uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
2799 uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
2803 uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */
2804 uint64_t reserved_28_31 : 4;
2805 uint64_t m3_un_wi : 1; /**< Reserved. */
2806 uint64_t m3_un_b0 : 1; /**< Reserved. */
2807 uint64_t m3_up_wi : 1; /**< Reserved. */
2808 uint64_t m3_up_b0 : 1; /**< Reserved. */
2809 uint64_t m2_un_wi : 1; /**< Reserved. */
2810 uint64_t m2_un_b0 : 1; /**< Reserved. */
2811 uint64_t m2_up_wi : 1; /**< Reserved. */
2812 uint64_t m2_up_b0 : 1; /**< Reserved. */
2813 uint64_t mac1_int : 1; /**< Interrupt from MAC1.
2815 uint64_t mac0_int : 1; /**< Interrupt from MAC0.
2817 uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1.
2820 uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0.
2823 uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
2826 uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1.
2829 uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
2832 uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1.
2835 uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
2838 uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0.
2841 uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
2844 uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0.
2847 uint64_t reserved_6_7 : 2;
2848 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
2850 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
2852 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
2853 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
2855 uint64_t reserved_1_1 : 1;
2856 uint64_t rml_to : 1; /**< A read or write transfer did not complete
2859 uint64_t rml_to : 1;
2860 uint64_t reserved_1_1 : 1;
2861 uint64_t bar0_to : 1;
2862 uint64_t iob2big : 1;
2863 uint64_t pcnt : 1;
2864 uint64_t ptime : 1;
2865 uint64_t reserved_6_7 : 2;
2866 uint64_t m0_up_b0 : 1;
2867 uint64_t m0_up_wi : 1;
2868 uint64_t m0_un_b0 : 1;
2869 uint64_t m0_un_wi : 1;
2870 uint64_t m1_up_b0 : 1;
2871 uint64_t m1_up_wi : 1;
2872 uint64_t m1_un_b0 : 1;
2873 uint64_t m1_un_wi : 1;
2874 uint64_t mio_int0 : 1;
2875 uint64_t mio_int1 : 1;
2876 uint64_t mac0_int : 1;
2877 uint64_t mac1_int : 1;
2878 uint64_t m2_up_b0 : 1;
2879 uint64_t m2_up_wi : 1;
2880 uint64_t m2_un_b0 : 1;
2881 uint64_t m2_un_wi : 1;
2882 uint64_t m3_up_b0 : 1;
2883 uint64_t m3_up_wi : 1;
2884 uint64_t m3_un_b0 : 1;
2885 uint64_t m3_un_wi : 1;
2886 uint64_t reserved_28_31 : 4;
2887 uint64_t dmafi : 2;
2888 uint64_t dcnt : 2;
2889 uint64_t dtime : 2;
2890 uint64_t reserved_38_47 : 10;
2891 uint64_t pidbof : 1;
2892 uint64_t psldbof : 1;
2893 uint64_t pout_err : 1;
2894 uint64_t pin_bp : 1;
2895 uint64_t pgl_err : 1;
2896 uint64_t pdi_err : 1;
2897 uint64_t pop_err : 1;
2898 uint64_t pins_err : 1;
2899 uint64_t sprt0_err : 1;
2900 uint64_t sprt1_err : 1;
2901 uint64_t sprt2_err : 1;
2902 uint64_t sprt3_err : 1;
2903 uint64_t ill_pad : 1;
2904 uint64_t reserved_61_63 : 3;
2909 uint64_t reserved_61_63 : 3;
2910 uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress
2913 uint64_t reserved_58_59 : 2;
2914 uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1
2916 uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0
2918 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
2920 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
2922 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
2924 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
2926 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK.
2928 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
2930 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
2932 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
2934 uint64_t reserved_38_47 : 10;
2935 uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
2943 uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
2947 uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */
2948 uint64_t reserved_20_31 : 12;
2949 uint64_t mac1_int : 1; /**< Interrupt from MAC1.
2951 uint64_t mac0_int : 1; /**< Interrupt from MAC0.
2953 uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1.
2956 uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0.
2959 uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
2962 uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1.
2965 uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
2968 uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1.
2971 uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
2974 uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0.
2977 uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
2980 uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0.
2983 uint64_t reserved_6_7 : 2;
2984 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
2986 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
2988 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
2989 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
2991 uint64_t reserved_1_1 : 1;
2992 uint64_t rml_to : 1; /**< A read or write transfer did not complete
2995 uint64_t rml_to : 1;
2996 uint64_t reserved_1_1 : 1;
2997 uint64_t bar0_to : 1;
2998 uint64_t iob2big : 1;
2999 uint64_t pcnt : 1;
3000 uint64_t ptime : 1;
3001 uint64_t reserved_6_7 : 2;
3002 uint64_t m0_up_b0 : 1;
3003 uint64_t m0_up_wi : 1;
3004 uint64_t m0_un_b0 : 1;
3005 uint64_t m0_un_wi : 1;
3006 uint64_t m1_up_b0 : 1;
3007 uint64_t m1_up_wi : 1;
3008 uint64_t m1_un_b0 : 1;
3009 uint64_t m1_un_wi : 1;
3010 uint64_t mio_int0 : 1;
3011 uint64_t mio_int1 : 1;
3012 uint64_t mac0_int : 1;
3013 uint64_t mac1_int : 1;
3014 uint64_t reserved_20_31 : 12;
3015 uint64_t dmafi : 2;
3016 uint64_t dcnt : 2;
3017 uint64_t dtime : 2;
3018 uint64_t reserved_38_47 : 10;
3019 uint64_t pidbof : 1;
3020 uint64_t psldbof : 1;
3021 uint64_t pout_err : 1;
3022 uint64_t pin_bp : 1;
3023 uint64_t pgl_err : 1;
3024 uint64_t pdi_err : 1;
3025 uint64_t pop_err : 1;
3026 uint64_t pins_err : 1;
3027 uint64_t sprt0_err : 1;
3028 uint64_t sprt1_err : 1;
3029 uint64_t reserved_58_59 : 2;
3030 uint64_t ill_pad : 1;
3031 uint64_t reserved_61_63 : 3;
3038 uint64_t reserved_62_63 : 2;
3039 uint64_t pipe_err : 1; /**< Set when a PIPE value outside range is received. */
3040 uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress
3043 uint64_t reserved_58_59 : 2;
3044 uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1
3046 uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0
3048 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
3050 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
3052 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
3054 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
3056 uint64_t reserved_51_51 : 1;
3057 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
3059 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
3061 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
3063 uint64_t reserved_38_47 : 10;
3064 uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
3072 uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
3076 uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */
3077 uint64_t reserved_20_31 : 12;
3078 uint64_t mac1_int : 1; /**< Interrupt from MAC1.
3080 uint64_t mac0_int : 1; /**< Interrupt from MAC0.
3082 uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1.
3085 uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0.
3088 uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
3091 uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1.
3094 uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
3097 uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1.
3100 uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
3103 uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0.
3106 uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
3109 uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0.
3112 uint64_t reserved_6_7 : 2;
3113 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
3115 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
3117 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
3118 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
3120 uint64_t reserved_1_1 : 1;
3121 uint64_t rml_to : 1; /**< A read or write transfer did not complete
3124 uint64_t rml_to : 1;
3125 uint64_t reserved_1_1 : 1;
3126 uint64_t bar0_to : 1;
3127 uint64_t iob2big : 1;
3128 uint64_t pcnt : 1;
3129 uint64_t ptime : 1;
3130 uint64_t reserved_6_7 : 2;
3131 uint64_t m0_up_b0 : 1;
3132 uint64_t m0_up_wi : 1;
3133 uint64_t m0_un_b0 : 1;
3134 uint64_t m0_un_wi : 1;
3135 uint64_t m1_up_b0 : 1;
3136 uint64_t m1_up_wi : 1;
3137 uint64_t m1_un_b0 : 1;
3138 uint64_t m1_un_wi : 1;
3139 uint64_t mio_int0 : 1;
3140 uint64_t mio_int1 : 1;
3141 uint64_t mac0_int : 1;
3142 uint64_t mac1_int : 1;
3143 uint64_t reserved_20_31 : 12;
3144 uint64_t dmafi : 2;
3145 uint64_t dcnt : 2;
3146 uint64_t dtime : 2;
3147 uint64_t reserved_38_47 : 10;
3148 uint64_t pidbof : 1;
3149 uint64_t psldbof : 1;
3150 uint64_t pout_err : 1;
3151 uint64_t reserved_51_51 : 1;
3152 uint64_t pgl_err : 1;
3153 uint64_t pdi_err : 1;
3154 uint64_t pop_err : 1;
3155 uint64_t pins_err : 1;
3156 uint64_t sprt0_err : 1;
3157 uint64_t sprt1_err : 1;
3158 uint64_t reserved_58_59 : 2;
3159 uint64_t ill_pad : 1;
3160 uint64_t pipe_err : 1;
3161 uint64_t reserved_62_63 : 2;
3177 uint64_t u64;
3180 uint64_t data : 64; /**< Last window read data. */
3182 uint64_t data : 64;
3203 uint64_t u64;
3206 uint64_t data : 64; /**< Last window read data. */
3208 uint64_t data : 64;
3229 uint64_t u64;
3232 uint64_t data : 64; /**< Last window read data. */
3234 uint64_t data : 64;
3251 uint64_t u64;
3254 uint64_t data : 64; /**< Last window read data. */
3256 uint64_t data : 64;
3275 uint64_t u64;
3278 uint64_t reserved_54_63 : 10;
3279 uint64_t p1_c_d : 1; /**< When set does not allow writing of P1_CCNT. */
3280 uint64_t p1_n_d : 1; /**< When set does not allow writing of P1_NCNT. */
3281 uint64_t p1_p_d : 1; /**< When set does not allow writing of P1_PCNT. */
3282 uint64_t p0_c_d : 1; /**< When set does not allow writing of P0_CCNT. */
3283 uint64_t p0_n_d : 1; /**< When set does not allow writing of P0_NCNT. */
3284 uint64_t p0_p_d : 1; /**< When set does not allow writing of P0_PCNT. */
3285 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits.
3287 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits.
3289 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits.
3291 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits.
3293 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits.
3295 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits.
3298 uint64_t p0_pcnt : 8;
3299 uint64_t p0_ncnt : 8;
3300 uint64_t p0_ccnt : 8;
3301 uint64_t p1_pcnt : 8;
3302 uint64_t p1_ncnt : 8;
3303 uint64_t p1_ccnt : 8;
3304 uint64_t p0_p_d : 1;
3305 uint64_t p0_n_d : 1;
3306 uint64_t p0_c_d : 1;
3307 uint64_t p1_p_d : 1;
3308 uint64_t p1_n_d : 1;
3309 uint64_t p1_c_d : 1;
3310 uint64_t reserved_54_63 : 10;
3317 uint64_t reserved_48_63 : 16;
3318 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits.
3320 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits.
3322 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits.
3324 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits.
3326 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits.
3328 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits.
3331 uint64_t p0_pcnt : 8;
3332 uint64_t p0_ncnt : 8;
3333 uint64_t p0_ccnt : 8;
3334 uint64_t p1_pcnt : 8;
3335 uint64_t p1_ncnt : 8;
3336 uint64_t p1_ccnt : 8;
3337 uint64_t reserved_48_63 : 16;
3357 uint64_t u64;
3360 uint64_t reserved_54_63 : 10;
3361 uint64_t p3_c_d : 1; /**< When set does not allow writing of P3_CCNT. */
3362 uint64_t p3_n_d : 1; /**< When set does not allow writing of P3_NCNT. */
3363 uint64_t p3_p_d : 1; /**< When set does not allow writing of P3_PCNT. */
3364 uint64_t p2_c_d : 1; /**< When set does not allow writing of P2_CCNT. */
3365 uint64_t p2_n_d : 1; /**< When set does not allow writing of P2_NCNT. */
3366 uint64_t p2_p_d : 1; /**< When set does not allow writing of P2_PCNT. */
3367 uint64_t p3_ccnt : 8; /**< Port3 C-TLP FIFO Credits.
3369 uint64_t p3_ncnt : 8; /**< Port3 N-TLP FIFO Credits.
3371 uint64_t p3_pcnt : 8; /**< Port3 P-TLP FIFO Credits.
3373 uint64_t p2_ccnt : 8; /**< Port2 C-TLP FIFO Credits.
3375 uint64_t p2_ncnt : 8; /**< Port2 N-TLP FIFO Credits.
3377 uint64_t p2_pcnt : 8; /**< Port2 P-TLP FIFO Credits.
3380 uint64_t p2_pcnt : 8;
3381 uint64_t p2_ncnt : 8;
3382 uint64_t p2_ccnt : 8;
3383 uint64_t p3_pcnt : 8;
3384 uint64_t p3_ncnt : 8;
3385 uint64_t p3_ccnt : 8;
3386 uint64_t p2_p_d : 1;
3387 uint64_t p2_n_d : 1;
3388 uint64_t p2_c_d : 1;
3389 uint64_t p3_p_d : 1;
3390 uint64_t p3_n_d : 1;
3391 uint64_t p3_c_d : 1;
3392 uint64_t reserved_54_63 : 10;
3411 uint64_t u64;
3414 uint64_t reserved_9_63 : 55;
3415 uint64_t a_mode : 1; /**< SLI in Authenticate Mode. */
3416 uint64_t num : 8; /**< The mac number. */
3418 uint64_t num : 8;
3419 uint64_t a_mode : 1;
3420 uint64_t reserved_9_63 : 55;
3426 uint64_t reserved_8_63 : 56;
3427 uint64_t num : 8; /**< The mac number. */
3429 uint64_t num : 8;
3430 uint64_t reserved_8_63 : 56;
3448 uint64_t u64;
3451 uint64_t reserved_14_63 : 50;
3452 uint64_t max_word : 4; /**< The maximum number of words to merge into a single
3455 uint64_t timer : 10; /**< When the SLI starts a PP to MAC write it waits
3461 uint64_t timer : 10;
3462 uint64_t max_word : 4;
3463 uint64_t reserved_14_63 : 50;
3491 uint64_t u64;
3494 uint64_t reserved_43_63 : 21;
3495 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads.
3498 uint64_t port : 3; /**< Physical MAC Port that reads/writes to
3501 uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */
3502 uint64_t esr : 2; /**< ES<1:0> for reads to this subid.
3505 uint64_t esw : 2; /**< ES<1:0> for writes to this subid.
3508 uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid
3515 uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid
3522 uint64_t reserved_0_29 : 30;
3524 uint64_t reserved_0_29 : 30;
3525 uint64_t rtype : 2;
3526 uint64_t wtype : 2;
3527 uint64_t esw : 2;
3528 uint64_t esr : 2;
3529 uint64_t nmerge : 1;
3530 uint64_t port : 3;
3531 uint64_t zero : 1;
3532 uint64_t reserved_43_63 : 21;
3537 uint64_t reserved_43_63 : 21;
3538 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads.
3541 uint64_t port : 3; /**< Physical MAC Port that reads/writes to
3544 uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */
3545 uint64_t esr : 2; /**< ES<1:0> for reads to this subid.
3548 uint64_t esw : 2; /**< ES<1:0> for writes to this subid.
3551 uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid
3558 uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid
3565 uint64_t ba : 30; /**< Address Bits <63:34> for reads/writes that use
3568 uint64_t ba : 30;
3569 uint64_t rtype : 2;
3570 uint64_t wtype : 2;
3571 uint64_t esw : 2;
3572 uint64_t esr : 2;
3573 uint64_t nmerge : 1;
3574 uint64_t port : 3;
3575 uint64_t zero : 1;
3576 uint64_t reserved_43_63 : 21;
3584 uint64_t reserved_43_63 : 21;
3585 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads.
3588 uint64_t port : 3; /**< Physical MAC Port that reads/writes to
3591 uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */
3592 uint64_t esr : 2; /**< ES<1:0> for reads to this subid.
3595 uint64_t esw : 2; /**< ES<1:0> for writes to this subid.
3598 uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid
3602 uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid
3606 uint64_t ba : 28; /**< Address Bits <63:36> for reads/writes that use
3608 uint64_t reserved_0_1 : 2;
3610 uint64_t reserved_0_1 : 2;
3611 uint64_t ba : 28;
3612 uint64_t rtype : 2;
3613 uint64_t wtype : 2;
3614 uint64_t esw : 2;
3615 uint64_t esr : 2;
3616 uint64_t nmerge : 1;
3617 uint64_t port : 3;
3618 uint64_t zero : 1;
3619 uint64_t reserved_43_63 : 21;
3635 uint64_t u64;
3638 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */
3640 uint64_t enb : 64;
3661 uint64_t u64;
3664 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */
3666 uint64_t enb : 64;
3687 uint64_t u64;
3690 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */
3692 uint64_t enb : 64;
3713 uint64_t u64;
3716 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */
3718 uint64_t enb : 64;
3739 uint64_t u64;
3742 uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
3744 uint64_t intr : 64;
3765 uint64_t u64;
3768 uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
3770 uint64_t intr : 64;
3791 uint64_t u64;
3794 uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
3796 uint64_t intr : 64;
3817 uint64_t u64;
3820 uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
3822 uint64_t intr : 64;
3843 uint64_t u64;
3846 uint64_t reserved_16_63 : 48;
3847 uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY
3849 uint64_t msi_int : 8; /**< Selects the value that would be received when the
3852 uint64_t msi_int : 8;
3853 uint64_t rd_int : 8;
3854 uint64_t reserved_16_63 : 48;
3875 uint64_t u64;
3878 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
3882 uint64_t clr : 64;
3903 uint64_t u64;
3906 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
3910 uint64_t clr : 64;
3931 uint64_t u64;
3934 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
3938 uint64_t clr : 64;
3959 uint64_t u64;
3962 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
3966 uint64_t clr : 64;
3987 uint64_t u64;
3990 uint64_t set : 64; /**< A write of '1' to a vector will set the
3994 uint64_t set : 64;
4015 uint64_t u64;
4018 uint64_t set : 64; /**< A write of '1' to a vector will set the
4022 uint64_t set : 64;
4043 uint64_t u64;
4046 uint64_t set : 64; /**< A write of '1' to a vector will set the
4050 uint64_t set : 64;
4071 uint64_t u64;
4074 uint64_t set : 64; /**< A write of '1' to a vector will set the
4078 uint64_t set : 64;
4099 uint64_t u64;
4102 uint64_t reserved_16_63 : 48;
4103 uint64_t ciu_int : 8; /**< Selects which bit in the SLI_MSI_RCV# (0-255)
4107 uint64_t msi_int : 8; /**< Selects the value that would be received when the
4110 uint64_t msi_int : 8;
4111 uint64_t ciu_int : 8;
4112 uint64_t reserved_16_63 : 48;
4133 uint64_t u64;
4136 uint64_t reserved_8_63 : 56;
4137 uint64_t intr : 8; /**< A write to this register will result in a bit in
4143 uint64_t intr : 8;
4144 uint64_t reserved_8_63 : 56;
4169 uint64_t u64;
4172 uint64_t reserved_16_63 : 48;
4173 uint64_t intr : 8; /**< A write to this register will result in a bit in
4178 uint64_t reserved_0_7 : 8;
4180 uint64_t reserved_0_7 : 8;
4181 uint64_t intr : 8;
4182 uint64_t reserved_16_63 : 48;
4207 uint64_t u64;
4210 uint64_t reserved_24_63 : 40;
4211 uint64_t intr : 8; /**< A write to this register will result in a bit in
4216 uint64_t reserved_0_15 : 16;
4218 uint64_t reserved_0_15 : 16;
4219 uint64_t intr : 8;
4220 uint64_t reserved_24_63 : 40;
4245 uint64_t u64;
4248 uint64_t reserved_32_63 : 32;
4249 uint64_t intr : 8; /**< A write to this register will result in a bit in
4254 uint64_t reserved_0_23 : 24;
4256 uint64_t reserved_0_23 : 24;
4257 uint64_t intr : 8;
4258 uint64_t reserved_32_63 : 32;
4279 uint64_t u64;
4282 uint64_t reserved_54_63 : 10;
4283 uint64_t timer : 22; /**< Timer incremented every 1024 core clocks
4290 uint64_t cnt : 32; /**< ring counter. This field is incremented as
4300 uint64_t cnt : 32;
4301 uint64_t timer : 22;
4302 uint64_t reserved_54_63 : 10;
4323 uint64_t u64;
4326 uint64_t wmark : 32; /**< When CNT is greater than this threshold no more
4331 uint64_t cnt : 32; /**< ring counter. This field is incremented by one
4340 uint64_t cnt : 32;
4341 uint64_t wmark : 32;
4360 uint64_t u64;
4363 uint64_t addr : 61; /**< Base address for Instructions. */
4364 uint64_t reserved_0_2 : 3;
4366 uint64_t reserved_0_2 : 3;
4367 uint64_t addr : 61;
4388 uint64_t u64;
4391 uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR
4393 uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field
4398 uint64_t dbell : 32;
4399 uint64_t aoff : 32;
4420 uint64_t u64;
4423 uint64_t max : 9; /**< Max Fifo Size. */
4424 uint64_t rrp : 9; /**< Fifo read pointer. */
4425 uint64_t wrp : 9; /**< Fifo write pointer. */
4426 uint64_t fcnt : 5; /**< Fifo count. */
4427 uint64_t rsize : 32; /**< Instruction ring size. */
4429 uint64_t rsize : 32;
4430 uint64_t fcnt : 5;
4431 uint64_t wrp : 9;
4432 uint64_t rrp : 9;
4433 uint64_t max : 9;
4454 uint64_t u64;
4457 uint64_t reserved_44_63 : 20;
4458 uint64_t pbp : 1; /**< Enable Packet-by-packet mode.
4462 uint64_t reserved_38_42 : 5;
4463 uint64_t rparmode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4465 uint64_t reserved_35_35 : 1;
4466 uint64_t rskp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL]
4468 uint64_t rngrpext : 2; /**< Becomes PKT_INST_HDR[GRPEXT]
4470 uint64_t rnqos : 1; /**< Becomes PKT_INST_HDR[NQOS]
4472 uint64_t rngrp : 1; /**< Becomes PKT_INST_HDR[NGRP]
4474 uint64_t rntt : 1; /**< Becomes PKT_INST_HDR[NTT]
4476 uint64_t rntag : 1; /**< Becomes PKT_INST_HDR[NTAG]
4478 uint64_t use_ihdr : 1; /**< When set '1' DPI always prepends a PKT_INST_HDR
4483 uint64_t reserved_16_20 : 5;
4484 uint64_t par_mode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4486 uint64_t reserved_13_13 : 1;
4487 uint64_t skp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL]
4489 uint64_t ngrpext : 2; /**< Becomes PKT_INST_HDR[GRPEXT]
4491 uint64_t nqos : 1; /**< Becomes PKT_INST_HDR[NQOS]
4493 uint64_t ngrp : 1; /**< Becomes PKT_INST_HDR[NGRP]
4495 uint64_t ntt : 1; /**< Becomes PKT_INST_HDR[NTT]
4497 uint64_t ntag : 1; /**< Becomes PKT_INST_HDR[NTAG]
4500 uint64_t ntag : 1;
4501 uint64_t ntt : 1;
4502 uint64_t ngrp : 1;
4503 uint64_t nqos : 1;
4504 uint64_t ngrpext : 2;
4505 uint64_t skp_len : 7;
4506 uint64_t reserved_13_13 : 1;
4507 uint64_t par_mode : 2;
4508 uint64_t reserved_16_20 : 5;
4509 uint64_t use_ihdr : 1;
4510 uint64_t rntag : 1;
4511 uint64_t rntt : 1;
4512 uint64_t rngrp : 1;
4513 uint64_t rnqos : 1;
4514 uint64_t rngrpext : 2;
4515 uint64_t rskp_len : 7;
4516 uint64_t reserved_35_35 : 1;
4517 uint64_t rparmode : 2;
4518 uint64_t reserved_38_42 : 5;
4519 uint64_t pbp : 1;
4520 uint64_t reserved_44_63 : 20;
4525 uint64_t reserved_44_63 : 20;
4526 uint64_t pbp : 1; /**< Enable Packet-by-packet mode.
4530 uint64_t reserved_38_42 : 5;
4531 uint64_t rparmode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4533 uint64_t reserved_35_35 : 1;
4534 uint64_t rskp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL]
4536 uint64_t reserved_26_27 : 2;
4537 uint64_t rnqos : 1; /**< Becomes PKT_INST_HDR[NQOS]
4539 uint64_t rngrp : 1; /**< Becomes PKT_INST_HDR[NGRP]
4541 uint64_t rntt : 1; /**< Becomes PKT_INST_HDR[NTT]
4543 uint64_t rntag : 1; /**< Becomes PKT_INST_HDR[NTAG]
4545 uint64_t use_ihdr : 1; /**< When set '1' DPI always prepends a PKT_INST_HDR
4550 uint64_t reserved_16_20 : 5;
4551 uint64_t par_mode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4553 uint64_t reserved_13_13 : 1;
4554 uint64_t skp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL]
4556 uint64_t reserved_4_5 : 2;
4557 uint64_t nqos : 1; /**< Becomes PKT_INST_HDR[NQOS]
4559 uint64_t ngrp : 1; /**< Becomes PKT_INST_HDR[NGRP]
4561 uint64_t ntt : 1; /**< Becomes PKT_INST_HDR[NTT]
4563 uint64_t ntag : 1; /**< Becomes PKT_INST_HDR[NTAG]
4566 uint64_t ntag : 1;
4567 uint64_t ntt : 1;
4568 uint64_t ngrp : 1;
4569 uint64_t nqos : 1;
4570 uint64_t reserved_4_5 : 2;
4571 uint64_t skp_len : 7;
4572 uint64_t reserved_13_13 : 1;
4573 uint64_t par_mode : 2;
4574 uint64_t reserved_16_20 : 5;
4575 uint64_t use_ihdr : 1;
4576 uint64_t rntag : 1;
4577 uint64_t rntt : 1;
4578 uint64_t rngrp : 1;
4579 uint64_t rnqos : 1;
4580 uint64_t reserved_26_27 : 2;
4581 uint64_t rskp_len : 7;
4582 uint64_t reserved_35_35 : 1;
4583 uint64_t rparmode : 2;
4584 uint64_t reserved_38_42 : 5;
4585 uint64_t pbp : 1;
4586 uint64_t reserved_44_63 : 20;
4606 uint64_t u64;
4609 uint64_t reserved_23_63 : 41;
4610 uint64_t isize : 7; /**< INFO BYTES size (bytes) for ring X. Legal sizes
4612 uint64_t bsize : 16; /**< BUFFER SIZE (bytes) for ring X. */
4614 uint64_t bsize : 16;
4615 uint64_t isize : 7;
4616 uint64_t reserved_23_63 : 41;
4637 uint64_t u64;
4640 uint64_t addr : 60; /**< Base address for scatter list pointers. */
4641 uint64_t reserved_0_3 : 4;
4643 uint64_t reserved_0_3 : 4;
4644 uint64_t addr : 60;
4665 uint64_t u64;
4668 uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR
4672 uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field
4679 uint64_t dbell : 32;
4680 uint64_t aoff : 32;
4701 uint64_t u64;
4704 uint64_t reserved_32_63 : 32;
4705 uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in
4708 uint64_t rsize : 32;
4709 uint64_t reserved_32_63 : 32;
4730 uint64_t u64;
4733 uint64_t reserved_32_63 : 32;
4734 uint64_t port : 32; /**< Output ring packet counter interrupt bits
4740 uint64_t port : 32;
4741 uint64_t reserved_32_63 : 32;
4762 uint64_t u64;
4765 uint64_t reserved_32_63 : 32;
4766 uint64_t port : 32; /**< Output ring packet counter interrupt enables
4772 uint64_t port : 32;
4773 uint64_t reserved_32_63 : 32;
4794 uint64_t u64;
4797 uint64_t reserved_5_63 : 59;
4798 uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received
4804 uint64_t pkt_bp : 4; /**< When set '1' enable the port level backpressure for
4807 uint64_t pkt_bp : 4;
4808 uint64_t ring_en : 1;
4809 uint64_t reserved_5_63 : 59;
4830 uint64_t u64;
4833 uint64_t es : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes.
4843 uint64_t es : 64;
4864 uint64_t u64;
4867 uint64_t reserved_32_63 : 32;
4868 uint64_t nsr : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes.
4878 uint64_t nsr : 32;
4879 uint64_t reserved_32_63 : 32;
4900 uint64_t u64;
4903 uint64_t reserved_32_63 : 32;
4904 uint64_t ror : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes.
4914 uint64_t ror : 32;
4915 uint64_t reserved_32_63 : 32;
4936 uint64_t u64;
4939 uint64_t reserved_32_63 : 32;
4940 uint64_t dptr : 32; /**< Determines whether buffer/info pointers are
4953 uint64_t dptr : 32;
4954 uint64_t reserved_32_63 : 32;
4975 uint64_t u64;
4978 uint64_t reserved_32_63 : 32;
4979 uint64_t bp : 32; /**< A packet input ring that has its count greater
4986 uint64_t bp : 32;
4987 uint64_t reserved_32_63 : 32;
5006 uint64_t u64;
5009 uint64_t reserved_32_63 : 32;
5010 uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction
5014 uint64_t cnt : 32;
5015 uint64_t reserved_32_63 : 32;
5036 uint64_t u64;
5039 uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */
5040 uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads
5044 uint64_t rd_cnt : 32;
5045 uint64_t wr_cnt : 32;
5066 uint64_t u64;
5069 uint64_t pp : 64; /**< The MAC port that the Packet ring number is
5075 uint64_t pp : 64;
5096 uint64_t u64;
5099 uint64_t prd_erst : 1; /**< PRD Error Reset */
5100 uint64_t prd_rds : 7; /**< PRD Reads Out */
5101 uint64_t gii_erst : 1; /**< GII Error Reset */
5102 uint64_t gii_rds : 7; /**< GII Reads Out */
5103 uint64_t reserved_41_47 : 7;
5104 uint64_t prc_idle : 1; /**< PRC In IDLE */
5105 uint64_t reserved_24_39 : 16;
5106 uint64_t pin_rst : 1; /**< Packet In Reset. When a gather-list read receives
5115 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
5119 uint64_t pbp_dhi : 13; /**< PBP_DHI replaces address bits that are used
5128 uint64_t d_nsr : 1; /**< ADDRTYPE<1> or MACADD<61> for packet input data
5137 uint64_t d_esr : 2; /**< ES<1:0> or MACADD<63:62> for packet input data
5146 uint64_t d_ror : 1; /**< ADDRTYPE<0> or MACADD<60> for packet input data
5155 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
5160 uint64_t nsr : 1; /**< ADDRTYPE<1> for packet input instruction reads and
5165 uint64_t esr : 2; /**< ES<1:0> for packet input instruction reads and
5170 uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and
5176 uint64_t ror : 1;
5177 uint64_t esr : 2;
5178 uint64_t nsr : 1;
5179 uint64_t use_csr : 1;
5180 uint64_t d_ror : 1;
5181 uint64_t d_esr : 2;
5182 uint64_t d_nsr : 1;
5183 uint64_t pbp_dhi : 13;
5184 uint64_t pkt_rr : 1;
5185 uint64_t pin_rst : 1;
5186 uint64_t reserved_24_39 : 16;
5187 uint64_t prc_idle : 1;
5188 uint64_t reserved_41_47 : 7;
5189 uint64_t gii_rds : 7;
5190 uint64_t gii_erst : 1;
5191 uint64_t prd_rds : 7;
5192 uint64_t prd_erst : 1;
5198 uint64_t reserved_23_63 : 41;
5199 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
5203 uint64_t pbp_dhi : 13; /**< PBP_DHI replaces address bits that are used
5212 uint64_t d_nsr : 1; /**< ADDRTYPE<1> or MACADD<61> for packet input data
5221 uint64_t d_esr : 2; /**< ES<1:0> or MACADD<63:62> for packet input data
5230 uint64_t d_ror : 1; /**< ADDRTYPE<0> or MACADD<60> for packet input data
5239 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
5244 uint64_t nsr : 1; /**< ADDRTYPE<1> for packet input instruction reads and
5249 uint64_t esr : 2; /**< ES<1:0> for packet input instruction reads and
5254 uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and
5260 uint64_t ror : 1;
5261 uint64_t esr : 2;
5262 uint64_t nsr : 1;
5263 uint64_t use_csr : 1;
5264 uint64_t d_ror : 1;
5265 uint64_t d_esr : 2;
5266 uint64_t d_nsr : 1;
5267 uint64_t pbp_dhi : 13;
5268 uint64_t pkt_rr : 1;
5269 uint64_t reserved_23_63 : 41;
5288 uint64_t u64;
5291 uint64_t reserved_32_63 : 32;
5292 uint64_t enb : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */
5294 uint64_t enb : 32;
5295 uint64_t reserved_32_63 : 32;
5316 uint64_t u64;
5319 uint64_t rdsize : 64; /**< Number of instructions to be read in one MAC read
5331 uint64_t rdsize : 64;
5352 uint64_t u64;
5355 uint64_t reserved_32_63 : 32;
5356 uint64_t is_64b : 32; /**< When IS_64B<i>=1, instruction input ring i uses 64B
5359 uint64_t is_64b : 32;
5360 uint64_t reserved_32_63 : 32;
5384 uint64_t u64;
5387 uint64_t reserved_54_63 : 10;
5388 uint64_t time : 22; /**< Output ring counter time interrupt threshold
5391 uint64_t cnt : 32; /**< Output ring counter interrupt threshold
5395 uint64_t cnt : 32;
5396 uint64_t time : 22;
5397 uint64_t reserved_54_63 : 10;
5418 uint64_t u64;
5421 uint64_t reserved_32_63 : 32;
5422 uint64_t iptr : 32; /**< When IPTR<i>=1, packet output ring i is in info-
5425 uint64_t iptr : 32;
5426 uint64_t reserved_32_63 : 32;
5447 uint64_t u64;
5450 uint64_t reserved_32_63 : 32;
5451 uint64_t bmode : 32; /**< Determines whether SLI_PKTi_CNTS[CNT] is a byte or
5457 uint64_t bmode : 32;
5458 uint64_t reserved_32_63 : 32;
5479 uint64_t u64;
5482 uint64_t reserved_32_63 : 32;
5483 uint64_t bp_en : 32; /**< When set '1' enable the ring level backpressure
5488 uint64_t bp_en : 32;
5489 uint64_t reserved_32_63 : 32;
5505 uint64_t u64;
5508 uint64_t reserved_32_63 : 32;
5509 uint64_t enb : 32; /**< When ENB<i>=1, packet output ring i is enabled.
5514 uint64_t enb : 32;
5515 uint64_t reserved_32_63 : 32;
5536 uint64_t u64;
5539 uint64_t reserved_32_63 : 32;
5540 uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure
5543 uint64_t wmark : 32;
5544 uint64_t reserved_32_63 : 32;
5565 uint64_t u64;
5568 uint64_t pp : 64; /**< The physical MAC port that the output ring uses.
5574 uint64_t pp : 64;
5600 uint64_t u64;
5603 uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding
5605 uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding
5608 uint64_t out_rst : 32;
5609 uint64_t in_rst : 32;
5630 uint64_t u64;
5633 uint64_t es : 64; /**< ES<1:0> for the packet output ring reads that
5642 uint64_t es : 64;
5663 uint64_t u64;
5666 uint64_t reserved_32_63 : 32;
5667 uint64_t nsr : 32; /**< ADDRTYPE<1> for the packet output ring reads that
5676 uint64_t nsr : 32;
5677 uint64_t reserved_32_63 : 32;
5698 uint64_t u64;
5701 uint64_t reserved_32_63 : 32;
5702 uint64_t ror : 32; /**< ADDRTYPE<0> for the packet output ring reads that
5711 uint64_t ror : 32;
5712 uint64_t reserved_32_63 : 32;
5733 uint64_t u64;
5736 uint64_t reserved_32_63 : 32;
5737 uint64_t port : 32; /**< Output ring packet timer interrupt bits
5743 uint64_t port : 32;
5744 uint64_t reserved_32_63 : 32;
5765 uint64_t u64;
5768 uint64_t reserved_32_63 : 32;
5769 uint64_t port : 32; /**< Output ring packet timer interrupt enables
5775 uint64_t port : 32;
5776 uint64_t reserved_32_63 : 32;
5797 uint64_t u64;
5800 uint64_t reserved_25_63 : 39;
5801 uint64_t rpk_enb : 1; /**< Alternate PKT_INST_HDR PKind Enable for this ring.
5814 uint64_t reserved_22_23 : 2;
5815 uint64_t pkindr : 6; /**< Port Kind For this Ring used with packets
5818 uint64_t reserved_14_15 : 2;
5819 uint64_t bpkind : 6; /**< Back-pressure pkind for this Ring. */
5820 uint64_t reserved_6_7 : 2;
5821 uint64_t pkind : 6; /**< Port Kind For this Ring. */
5823 uint64_t pkind : 6;
5824 uint64_t reserved_6_7 : 2;
5825 uint64_t bpkind : 6;
5826 uint64_t reserved_14_15 : 2;
5827 uint64_t pkindr : 6;
5828 uint64_t reserved_22_23 : 2;
5829 uint64_t rpk_enb : 1;
5830 uint64_t reserved_25_63 : 39;
5836 uint64_t reserved_14_63 : 50;
5837 uint64_t bpkind : 6; /**< Back-pressure pkind for this Ring. */
5838 uint64_t reserved_6_7 : 2;
5839 uint64_t pkind : 6; /**< Port Kind For this Ring. */
5841 uint64_t pkind : 6;
5842 uint64_t reserved_6_7 : 2;
5843 uint64_t bpkind : 6;
5844 uint64_t reserved_14_63 : 50;
5861 uint64_t u64;
5864 uint64_t reserved_5_63 : 59;
5865 uint64_t wind_d : 1; /**< When set '1' disables access to the Window
5869 uint64_t bar0_d : 1; /**< When set '1' disables access from MAC to
5875 uint64_t mrrs : 3; /**< Max Read Request Size
5890 uint64_t mrrs : 3;
5891 uint64_t bar0_d : 1;
5892 uint64_t wind_d : 1;
5893 uint64_t reserved_5_63 : 59;
5914 uint64_t u64;
5917 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */
5919 uint64_t data : 64;
5940 uint64_t u64;
5943 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */
5945 uint64_t data : 64;
5966 uint64_t u64;
5969 uint64_t cpl1 : 12; /**< CPL1 State */
5970 uint64_t cpl0 : 12; /**< CPL0 State */
5971 uint64_t arb : 1; /**< ARB State */
5972 uint64_t csr : 39; /**< CSR State */
5974 uint64_t csr : 39;
5975 uint64_t arb : 1;
5976 uint64_t cpl0 : 12;
5977 uint64_t cpl1 : 12;
5998 uint64_t u64;
6001 uint64_t reserved_56_63 : 8;
6002 uint64_t nnp1 : 8; /**< NNP1 State */
6003 uint64_t reserved_47_47 : 1;
6004 uint64_t rac : 1; /**< RAC State */
6005 uint64_t csm1 : 15; /**< CSM1 State */
6006 uint64_t csm0 : 15; /**< CSM0 State */
6007 uint64_t nnp0 : 8; /**< NNP0 State */
6008 uint64_t nnd : 8; /**< NND State */
6010 uint64_t nnd : 8;
6011 uint64_t nnp0 : 8;
6012 uint64_t csm0 : 15;
6013 uint64_t csm1 : 15;
6014 uint64_t rac : 1;
6015 uint64_t reserved_47_47 : 1;
6016 uint64_t nnp1 : 8;
6017 uint64_t reserved_56_63 : 8;
6038 uint64_t u64;
6041 uint64_t reserved_56_63 : 8;
6042 uint64_t psm1 : 15; /**< PSM1 State */
6043 uint64_t psm0 : 15; /**< PSM0 State */
6044 uint64_t nsm1 : 13; /**< NSM1 State */
6045 uint64_t nsm0 : 13; /**< NSM0 State */
6047 uint64_t nsm0 : 13;
6048 uint64_t nsm1 : 13;
6049 uint64_t psm0 : 15;
6050 uint64_t psm1 : 15;
6051 uint64_t reserved_56_63 : 8;
6076 uint64_t u64;
6079 uint64_t reserved_24_63 : 40;
6080 uint64_t nump : 8; /**< Number of pipes the the SLI/DPI supports.
6085 uint64_t reserved_7_15 : 9;
6086 uint64_t base : 7; /**< When NUMP is non-zero, indicates the base pipe
6099 uint64_t base : 7;
6100 uint64_t reserved_7_15 : 9;
6101 uint64_t nump : 8;
6102 uint64_t reserved_24_63 : 40;
6119 uint64_t u64;
6122 uint64_t reserved_51_63 : 13;
6123 uint64_t ld_cmd : 2; /**< The load command sent wit hthe read.
6126 uint64_t iobit : 1; /**< A 1 or 0 can be written here but will not be used
6128 uint64_t rd_addr : 48; /**< The address to be read from.
6136 uint64_t rd_addr : 48;
6137 uint64_t iobit : 1;
6138 uint64_t ld_cmd : 2;
6139 uint64_t reserved_51_63 : 13;
6161 uint64_t u64;
6164 uint64_t rd_data : 64; /**< The read data. */
6166 uint64_t rd_data : 64;
6198 uint64_t u64;
6201 uint64_t reserved_49_63 : 15;
6202 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
6204 uint64_t wr_addr : 45; /**< The address that will be written to when the
6212 uint64_t reserved_0_2 : 3;
6214 uint64_t reserved_0_2 : 3;
6215 uint64_t wr_addr : 45;
6216 uint64_t iobit : 1;
6217 uint64_t reserved_49_63 : 15;
6239 uint64_t u64;
6242 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this
6246 uint64_t wr_data : 64;
6267 uint64_t u64;
6270 uint64_t reserved_8_63 : 56;
6271 uint64_t wr_mask : 8; /**< The data to be written. When a bit is '1'
6277 uint64_t wr_mask : 8;
6278 uint64_t reserved_8_63 : 56;
6306 uint64_t u64;
6309 uint64_t reserved_32_63 : 32;
6310 uint64_t time : 32; /**< Time to wait in core clocks for a
6316 uint64_t time : 32;
6317 uint64_t reserved_32_63 : 32;