Lines Matching refs:uint64_t
60 static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
79 static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
95 static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
109 static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
125 static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
136 static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
147 static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
158 static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
169 static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
180 static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
191 static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
202 static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
213 static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
224 static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
235 static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
246 static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
257 static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
268 static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
279 static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
293 static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
309 static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
320 static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
334 static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
350 static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
376 static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
392 static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
403 static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
414 static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
425 static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
436 static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
447 static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
458 static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
469 static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
480 static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
491 static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
502 static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
513 static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
524 static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
535 static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
546 static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
557 static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
568 static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
579 static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
590 static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
601 static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
612 static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
623 static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
634 static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
645 static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
656 static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
667 static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
678 static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
689 static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
700 static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
711 static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
722 static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
733 static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
744 static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
755 static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
766 static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
777 static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
788 static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
799 static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
810 static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
821 static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
832 static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
843 static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
854 static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
865 static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
876 static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
887 static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
898 static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
909 static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
919 static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
934 static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
949 static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
964 static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
980 static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
994 static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
1010 static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
1028 uint64_t u64;
1031 uint64_t baddr : 61; /**< The address to read Instruction from for output 0.
1034 uint64_t reserved_0_2 : 3;
1036 uint64_t reserved_0_2 : 3;
1037 uint64_t baddr : 61;
1058 uint64_t u64;
1061 uint64_t baddr : 61; /**< The address to read Instruction from for output 0.
1064 uint64_t reserved_0_2 : 3;
1066 uint64_t reserved_0_2 : 3;
1067 uint64_t baddr : 61;
1088 uint64_t u64;
1091 uint64_t reserved_20_63 : 44;
1092 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */
1093 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */
1094 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */
1095 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */
1096 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */
1097 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */
1098 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */
1099 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */
1100 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */
1101 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */
1102 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */
1103 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */
1104 uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */
1105 uint64_t pof2_bs : 1; /**< BIST Status for the pof2_fifo */
1106 uint64_t pof3_bs : 1; /**< BIST Status for the pof3_fifo */
1107 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */
1108 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */
1109 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */
1110 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */
1111 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */
1113 uint64_t dpi_bs : 1;
1114 uint64_t pdf_bs : 1;
1115 uint64_t dob_bs : 1;
1116 uint64_t nus_bs : 1;
1117 uint64_t pos_bs : 1;
1118 uint64_t pof3_bs : 1;
1119 uint64_t pof2_bs : 1;
1120 uint64_t pof1_bs : 1;
1121 uint64_t pof0_bs : 1;
1122 uint64_t pig_bs : 1;
1123 uint64_t pgf_bs : 1;
1124 uint64_t rdnl_bs : 1;
1125 uint64_t pcad_bs : 1;
1126 uint64_t pcac_bs : 1;
1127 uint64_t rdn_bs : 1;
1128 uint64_t pcn_bs : 1;
1129 uint64_t pcnc_bs : 1;
1130 uint64_t rdp_bs : 1;
1131 uint64_t dif_bs : 1;
1132 uint64_t csr_bs : 1;
1133 uint64_t reserved_20_63 : 44;
1138 uint64_t reserved_20_63 : 44;
1139 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */
1140 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */
1141 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */
1142 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */
1143 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */
1144 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */
1145 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */
1146 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */
1147 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */
1148 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */
1149 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */
1150 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */
1151 uint64_t reserved_5_7 : 3;
1152 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */
1153 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */
1154 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */
1155 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */
1156 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */
1158 uint64_t dpi_bs : 1;
1159 uint64_t pdf_bs : 1;
1160 uint64_t dob_bs : 1;
1161 uint64_t nus_bs : 1;
1162 uint64_t pos_bs : 1;
1163 uint64_t reserved_5_7 : 3;
1164 uint64_t pof0_bs : 1;
1165 uint64_t pig_bs : 1;
1166 uint64_t pgf_bs : 1;
1167 uint64_t rdnl_bs : 1;
1168 uint64_t pcad_bs : 1;
1169 uint64_t pcac_bs : 1;
1170 uint64_t rdn_bs : 1;
1171 uint64_t pcn_bs : 1;
1172 uint64_t pcnc_bs : 1;
1173 uint64_t rdp_bs : 1;
1174 uint64_t dif_bs : 1;
1175 uint64_t csr_bs : 1;
1176 uint64_t reserved_20_63 : 44;
1184 uint64_t reserved_20_63 : 44;
1185 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */
1186 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */
1187 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */
1188 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */
1189 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */
1190 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */
1191 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */
1192 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */
1193 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */
1194 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */
1195 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */
1196 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */
1197 uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */
1198 uint64_t reserved_5_6 : 2;
1199 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */
1200 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */
1201 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */
1202 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */
1203 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */
1205 uint64_t dpi_bs : 1;
1206 uint64_t pdf_bs : 1;
1207 uint64_t dob_bs : 1;
1208 uint64_t nus_bs : 1;
1209 uint64_t pos_bs : 1;
1210 uint64_t reserved_5_6 : 2;
1211 uint64_t pof1_bs : 1;
1212 uint64_t pof0_bs : 1;
1213 uint64_t pig_bs : 1;
1214 uint64_t pgf_bs : 1;
1215 uint64_t rdnl_bs : 1;
1216 uint64_t pcad_bs : 1;
1217 uint64_t pcac_bs : 1;
1218 uint64_t rdn_bs : 1;
1219 uint64_t pcn_bs : 1;
1220 uint64_t pcnc_bs : 1;
1221 uint64_t rdp_bs : 1;
1222 uint64_t dif_bs : 1;
1223 uint64_t csr_bs : 1;
1224 uint64_t reserved_20_63 : 44;
1240 uint64_t u64;
1243 uint64_t reserved_23_63 : 41;
1244 uint64_t isize : 7; /**< The number of bytes to move to the Info-Pointer
1247 uint64_t bsize : 16; /**< The size in bytes of the area pointed to by
1250 uint64_t bsize : 16;
1251 uint64_t isize : 7;
1252 uint64_t reserved_23_63 : 41;
1273 uint64_t u64;
1276 uint64_t reserved_10_63 : 54;
1277 uint64_t pctl : 5; /**< Bypass value for PCTL */
1278 uint64_t nctl : 5; /**< Bypass value for NCTL */
1280 uint64_t nctl : 5;
1281 uint64_t pctl : 5;
1282 uint64_t reserved_10_63 : 54;
1302 uint64_t u64;
1305 uint64_t reserved_63_63 : 1;
1306 uint64_t chip_rev : 8; /**< The revision of the N3. */
1307 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window
1309 uint64_t out3_enb : 1; /**< When asserted '1' the output3 engine is enabled.
1312 uint64_t out2_enb : 1; /**< When asserted '1' the output2 engine is enabled.
1315 uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled.
1318 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled.
1321 uint64_t ins3_enb : 1; /**< When asserted '1' the gather3 engine is enabled.
1324 uint64_t ins2_enb : 1; /**< When asserted '1' the gather2 engine is enabled.
1327 uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled.
1330 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled.
1333 uint64_t ins3_64b : 1; /**< When asserted '1' the instructions read by the
1336 uint64_t ins2_64b : 1; /**< When asserted '1' the instructions read by the
1339 uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the
1342 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the
1345 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in
1347 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1350 uint64_t reserved_37_39 : 3;
1351 uint64_t max_word : 5; /**< The maximum number of words to merge into a single
1354 uint64_t reserved_10_31 : 22;
1355 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait
1361 uint64_t timer : 10;
1362 uint64_t reserved_10_31 : 22;
1363 uint64_t max_word : 5;
1364 uint64_t reserved_37_39 : 3;
1365 uint64_t wait_com : 1;
1366 uint64_t pci_wdis : 1;
1367 uint64_t ins0_64b : 1;
1368 uint64_t ins1_64b : 1;
1369 uint64_t ins2_64b : 1;
1370 uint64_t ins3_64b : 1;
1371 uint64_t ins0_enb : 1;
1372 uint64_t ins1_enb : 1;
1373 uint64_t ins2_enb : 1;
1374 uint64_t ins3_enb : 1;
1375 uint64_t out0_enb : 1;
1376 uint64_t out1_enb : 1;
1377 uint64_t out2_enb : 1;
1378 uint64_t out3_enb : 1;
1379 uint64_t dis_pniw : 1;
1380 uint64_t chip_rev : 8;
1381 uint64_t reserved_63_63 : 1;
1386 uint64_t reserved_63_63 : 1;
1387 uint64_t chip_rev : 8; /**< The revision of the N3. */
1388 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window
1390 uint64_t reserved_51_53 : 3;
1391 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled.
1394 uint64_t reserved_47_49 : 3;
1395 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled.
1398 uint64_t reserved_43_45 : 3;
1399 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the
1402 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in
1404 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1407 uint64_t reserved_37_39 : 3;
1408 uint64_t max_word : 5; /**< The maximum number of words to merge into a single
1411 uint64_t reserved_10_31 : 22;
1412 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait
1418 uint64_t timer : 10;
1419 uint64_t reserved_10_31 : 22;
1420 uint64_t max_word : 5;
1421 uint64_t reserved_37_39 : 3;
1422 uint64_t wait_com : 1;
1423 uint64_t pci_wdis : 1;
1424 uint64_t ins0_64b : 1;
1425 uint64_t reserved_43_45 : 3;
1426 uint64_t ins0_enb : 1;
1427 uint64_t reserved_47_49 : 3;
1428 uint64_t out0_enb : 1;
1429 uint64_t reserved_51_53 : 3;
1430 uint64_t dis_pniw : 1;
1431 uint64_t chip_rev : 8;
1432 uint64_t reserved_63_63 : 1;
1437 uint64_t reserved_63_63 : 1;
1438 uint64_t chip_rev : 8; /**< The revision of the N3.
1440 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window
1442 uint64_t reserved_52_53 : 2;
1443 uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled.
1446 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled.
1449 uint64_t reserved_48_49 : 2;
1450 uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled.
1453 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled.
1456 uint64_t reserved_44_45 : 2;
1457 uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the
1460 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the
1463 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in
1465 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1468 uint64_t reserved_37_39 : 3;
1469 uint64_t max_word : 5; /**< The maximum number of words to merge into a single
1472 uint64_t reserved_10_31 : 22;
1473 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait
1479 uint64_t timer : 10;
1480 uint64_t reserved_10_31 : 22;
1481 uint64_t max_word : 5;
1482 uint64_t reserved_37_39 : 3;
1483 uint64_t wait_com : 1;
1484 uint64_t pci_wdis : 1;
1485 uint64_t ins0_64b : 1;
1486 uint64_t ins1_64b : 1;
1487 uint64_t reserved_44_45 : 2;
1488 uint64_t ins0_enb : 1;
1489 uint64_t ins1_enb : 1;
1490 uint64_t reserved_48_49 : 2;
1491 uint64_t out0_enb : 1;
1492 uint64_t out1_enb : 1;
1493 uint64_t reserved_52_53 : 2;
1494 uint64_t dis_pniw : 1;
1495 uint64_t chip_rev : 8;
1496 uint64_t reserved_63_63 : 1;
1515 uint64_t u64;
1518 uint64_t reserved_16_63 : 48;
1519 uint64_t dbg_sel : 16; /**< When this register is written its value is sent to
1522 uint64_t dbg_sel : 16;
1523 uint64_t reserved_16_63 : 48;
1544 uint64_t u64;
1547 uint64_t reserved_36_63 : 28;
1548 uint64_t b0_lend : 1; /**< When set '1' and the NPI is in the mode to write
1552 uint64_t dwb_denb : 1; /**< When set '1' the NPI will send a value in the DWB
1555 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
1558 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
1560 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
1563 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
1564 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
1565 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
1566 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
1571 uint64_t hp_enb : 1; /**< Enables the High Priority DMA.
1577 uint64_t lp_enb : 1; /**< Enables the Low Priority DMA.
1584 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
1590 uint64_t csize : 14;
1591 uint64_t lp_enb : 1;
1592 uint64_t hp_enb : 1;
1593 uint64_t o_mode : 1;
1594 uint64_t o_es : 2;
1595 uint64_t o_ns : 1;
1596 uint64_t o_ro : 1;
1597 uint64_t o_add1 : 1;
1598 uint64_t fpa_que : 3;
1599 uint64_t dwb_ichk : 9;
1600 uint64_t dwb_denb : 1;
1601 uint64_t b0_lend : 1;
1602 uint64_t reserved_36_63 : 28;
1623 uint64_t u64;
1626 uint64_t reserved_39_63 : 25;
1627 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */
1628 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */
1630 uint64_t dbell : 32;
1631 uint64_t fcnt : 7;
1632 uint64_t reserved_39_63 : 25;
1653 uint64_t u64;
1656 uint64_t reserved_40_63 : 24;
1657 uint64_t state : 4; /**< The DMA instruction engine state vector.
1659 uint64_t addr : 36; /**< The next L2C address to read DMA instructions
1662 uint64_t addr : 36;
1663 uint64_t state : 4;
1664 uint64_t reserved_40_63 : 24;
1685 uint64_t u64;
1688 uint64_t reserved_39_63 : 25;
1689 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */
1690 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */
1692 uint64_t dbell : 32;
1693 uint64_t fcnt : 7;
1694 uint64_t reserved_39_63 : 25;
1715 uint64_t u64;
1718 uint64_t reserved_40_63 : 24;
1719 uint64_t state : 4; /**< The DMA instruction engine state vector.
1721 uint64_t addr : 36; /**< The next L2C address to read DMA instructions
1724 uint64_t addr : 36;
1725 uint64_t state : 4;
1726 uint64_t reserved_40_63 : 24;
1747 uint64_t u64;
1750 uint64_t reserved_16_63 : 48;
1751 uint64_t dbell : 16; /**< The value written to this register is added to the
1755 uint64_t dbell : 16;
1756 uint64_t reserved_16_63 : 48;
1777 uint64_t u64;
1780 uint64_t reserved_36_63 : 28;
1781 uint64_t saddr : 36; /**< The starting address to read the first instruction. */
1783 uint64_t saddr : 36;
1784 uint64_t reserved_36_63 : 28;
1805 uint64_t u64;
1808 uint64_t reserved_23_63 : 41;
1809 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
1814 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in
1816 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of
1818 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of
1820 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1822 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
1827 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of
1829 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of
1831 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1834 uint64_t ror : 1;
1835 uint64_t esr : 2;
1836 uint64_t nsr : 1;
1837 uint64_t use_csr : 1;
1838 uint64_t d_ror : 1;
1839 uint64_t d_esr : 2;
1840 uint64_t d_nsr : 1;
1841 uint64_t pbp_dhi : 13;
1842 uint64_t pkt_rr : 1;
1843 uint64_t reserved_23_63 : 41;
1848 uint64_t reserved_22_63 : 42;
1849 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in
1851 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of
1853 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of
1855 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1857 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
1862 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of
1864 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of
1866 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1869 uint64_t ror : 1;
1870 uint64_t esr : 2;
1871 uint64_t nsr : 1;
1872 uint64_t use_csr : 1;
1873 uint64_t d_ror : 1;
1874 uint64_t d_esr : 2;
1875 uint64_t d_nsr : 1;
1876 uint64_t pbp_dhi : 13;
1877 uint64_t reserved_22_63 : 42;
1897 uint64_t u64;
1900 uint64_t reserved_62_63 : 2;
1901 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
1903 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
1905 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
1907 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
1909 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
1911 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
1913 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
1915 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
1917 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
1919 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
1921 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an
1923 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an
1925 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
1927 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
1929 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
1931 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
1933 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
1935 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
1937 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
1939 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
1941 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
1943 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
1945 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
1947 uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
1949 uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
1951 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
1953 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
1955 uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
1957 uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
1959 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
1961 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
1963 uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
1965 uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
1967 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
1969 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
1971 uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
1973 uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
1975 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
1977 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
1979 uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an
1981 uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an
1983 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an
1985 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
1987 uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
1989 uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
1991 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
1993 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
1995 uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
1997 uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
1999 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
2001 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2003 uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
2005 uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
2007 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
2009 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2011 uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
2013 uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
2015 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
2017 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2019 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2021 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2023 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2026 uint64_t rml_rto : 1;
2027 uint64_t rml_wto : 1;
2028 uint64_t pci_rsl : 1;
2029 uint64_t po0_2sml : 1;
2030 uint64_t po1_2sml : 1;
2031 uint64_t po2_2sml : 1;
2032 uint64_t po3_2sml : 1;
2033 uint64_t i0_rtout : 1;
2034 uint64_t i1_rtout : 1;
2035 uint64_t i2_rtout : 1;
2036 uint64_t i3_rtout : 1;
2037 uint64_t i0_overf : 1;
2038 uint64_t i1_overf : 1;
2039 uint64_t i2_overf : 1;
2040 uint64_t i3_overf : 1;
2041 uint64_t p0_rtout : 1;
2042 uint64_t p1_rtout : 1;
2043 uint64_t p2_rtout : 1;
2044 uint64_t p3_rtout : 1;
2045 uint64_t p0_perr : 1;
2046 uint64_t p1_perr : 1;
2047 uint64_t p2_perr : 1;
2048 uint64_t p3_perr : 1;
2049 uint64_t g0_rtout : 1;
2050 uint64_t g1_rtout : 1;
2051 uint64_t g2_rtout : 1;
2052 uint64_t g3_rtout : 1;
2053 uint64_t p0_pperr : 1;
2054 uint64_t p1_pperr : 1;
2055 uint64_t p2_pperr : 1;
2056 uint64_t p3_pperr : 1;
2057 uint64_t p0_ptout : 1;
2058 uint64_t p1_ptout : 1;
2059 uint64_t p2_ptout : 1;
2060 uint64_t p3_ptout : 1;
2061 uint64_t i0_pperr : 1;
2062 uint64_t i1_pperr : 1;
2063 uint64_t i2_pperr : 1;
2064 uint64_t i3_pperr : 1;
2065 uint64_t win_rto : 1;
2066 uint64_t p_dperr : 1;
2067 uint64_t iobdma : 1;
2068 uint64_t fcr_s_e : 1;
2069 uint64_t fcr_a_f : 1;
2070 uint64_t pcr_s_e : 1;
2071 uint64_t pcr_a_f : 1;
2072 uint64_t q2_s_e : 1;
2073 uint64_t q2_a_f : 1;
2074 uint64_t q3_s_e : 1;
2075 uint64_t q3_a_f : 1;
2076 uint64_t com_s_e : 1;
2077 uint64_t com_a_f : 1;
2078 uint64_t pnc_s_e : 1;
2079 uint64_t pnc_a_f : 1;
2080 uint64_t rwx_s_e : 1;
2081 uint64_t rdx_s_e : 1;
2082 uint64_t pcf_p_e : 1;
2083 uint64_t pcf_p_f : 1;
2084 uint64_t pdf_p_e : 1;
2085 uint64_t pdf_p_f : 1;
2086 uint64_t q1_s_e : 1;
2087 uint64_t q1_a_f : 1;
2088 uint64_t reserved_62_63 : 2;
2093 uint64_t reserved_62_63 : 2;
2094 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
2096 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
2098 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
2100 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
2102 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
2104 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
2106 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
2108 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
2110 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
2112 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
2114 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an
2116 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an
2118 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
2120 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
2122 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
2124 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
2126 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
2128 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
2130 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
2132 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
2134 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
2136 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
2138 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
2140 uint64_t reserved_36_38 : 3;
2141 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
2143 uint64_t reserved_32_34 : 3;
2144 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
2146 uint64_t reserved_28_30 : 3;
2147 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
2149 uint64_t reserved_24_26 : 3;
2150 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
2152 uint64_t reserved_20_22 : 3;
2153 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
2155 uint64_t reserved_16_18 : 3;
2156 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
2158 uint64_t reserved_12_14 : 3;
2159 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2161 uint64_t reserved_8_10 : 3;
2162 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2164 uint64_t reserved_4_6 : 3;
2165 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2167 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2169 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2171 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2174 uint64_t rml_rto : 1;
2175 uint64_t rml_wto : 1;
2176 uint64_t pci_rsl : 1;
2177 uint64_t po0_2sml : 1;
2178 uint64_t reserved_4_6 : 3;
2179 uint64_t i0_rtout : 1;
2180 uint64_t reserved_8_10 : 3;
2181 uint64_t i0_overf : 1;
2182 uint64_t reserved_12_14 : 3;
2183 uint64_t p0_rtout : 1;
2184 uint64_t reserved_16_18 : 3;
2185 uint64_t p0_perr : 1;
2186 uint64_t reserved_20_22 : 3;
2187 uint64_t g0_rtout : 1;
2188 uint64_t reserved_24_26 : 3;
2189 uint64_t p0_pperr : 1;
2190 uint64_t reserved_28_30 : 3;
2191 uint64_t p0_ptout : 1;
2192 uint64_t reserved_32_34 : 3;
2193 uint64_t i0_pperr : 1;
2194 uint64_t reserved_36_38 : 3;
2195 uint64_t win_rto : 1;
2196 uint64_t p_dperr : 1;
2197 uint64_t iobdma : 1;
2198 uint64_t fcr_s_e : 1;
2199 uint64_t fcr_a_f : 1;
2200 uint64_t pcr_s_e : 1;
2201 uint64_t pcr_a_f : 1;
2202 uint64_t q2_s_e : 1;
2203 uint64_t q2_a_f : 1;
2204 uint64_t q3_s_e : 1;
2205 uint64_t q3_a_f : 1;
2206 uint64_t com_s_e : 1;
2207 uint64_t com_a_f : 1;
2208 uint64_t pnc_s_e : 1;
2209 uint64_t pnc_a_f : 1;
2210 uint64_t rwx_s_e : 1;
2211 uint64_t rdx_s_e : 1;
2212 uint64_t pcf_p_e : 1;
2213 uint64_t pcf_p_f : 1;
2214 uint64_t pdf_p_e : 1;
2215 uint64_t pdf_p_f : 1;
2216 uint64_t q1_s_e : 1;
2217 uint64_t q1_a_f : 1;
2218 uint64_t reserved_62_63 : 2;
2223 uint64_t reserved_62_63 : 2;
2224 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
2226 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
2228 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
2230 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
2232 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
2234 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
2236 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
2238 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
2240 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
2242 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
2244 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an
2246 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an
2248 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
2250 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
2252 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
2254 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
2256 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
2258 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
2260 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
2262 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
2264 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
2266 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
2268 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
2270 uint64_t reserved_37_38 : 2;
2271 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
2273 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
2275 uint64_t reserved_33_34 : 2;
2276 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
2278 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
2280 uint64_t reserved_29_30 : 2;
2281 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
2283 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
2285 uint64_t reserved_25_26 : 2;
2286 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
2288 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
2290 uint64_t reserved_21_22 : 2;
2291 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an
2293 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
2295 uint64_t reserved_17_18 : 2;
2296 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
2298 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
2300 uint64_t reserved_13_14 : 2;
2301 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
2303 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2305 uint64_t reserved_9_10 : 2;
2306 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
2308 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2310 uint64_t reserved_5_6 : 2;
2311 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
2313 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2315 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2317 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2319 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2322 uint64_t rml_rto : 1;
2323 uint64_t rml_wto : 1;
2324 uint64_t pci_rsl : 1;
2325 uint64_t po0_2sml : 1;
2326 uint64_t po1_2sml : 1;
2327 uint64_t reserved_5_6 : 2;
2328 uint64_t i0_rtout : 1;
2329 uint64_t i1_rtout : 1;
2330 uint64_t reserved_9_10 : 2;
2331 uint64_t i0_overf : 1;
2332 uint64_t i1_overf : 1;
2333 uint64_t reserved_13_14 : 2;
2334 uint64_t p0_rtout : 1;
2335 uint64_t p1_rtout : 1;
2336 uint64_t reserved_17_18 : 2;
2337 uint64_t p0_perr : 1;
2338 uint64_t p1_perr : 1;
2339 uint64_t reserved_21_22 : 2;
2340 uint64_t g0_rtout : 1;
2341 uint64_t g1_rtout : 1;
2342 uint64_t reserved_25_26 : 2;
2343 uint64_t p0_pperr : 1;
2344 uint64_t p1_pperr : 1;
2345 uint64_t reserved_29_30 : 2;
2346 uint64_t p0_ptout : 1;
2347 uint64_t p1_ptout : 1;
2348 uint64_t reserved_33_34 : 2;
2349 uint64_t i0_pperr : 1;
2350 uint64_t i1_pperr : 1;
2351 uint64_t reserved_37_38 : 2;
2352 uint64_t win_rto : 1;
2353 uint64_t p_dperr : 1;
2354 uint64_t iobdma : 1;
2355 uint64_t fcr_s_e : 1;
2356 uint64_t fcr_a_f : 1;
2357 uint64_t pcr_s_e : 1;
2358 uint64_t pcr_a_f : 1;
2359 uint64_t q2_s_e : 1;
2360 uint64_t q2_a_f : 1;
2361 uint64_t q3_s_e : 1;
2362 uint64_t q3_a_f : 1;
2363 uint64_t com_s_e : 1;
2364 uint64_t com_a_f : 1;
2365 uint64_t pnc_s_e : 1;
2366 uint64_t pnc_a_f : 1;
2367 uint64_t rwx_s_e : 1;
2368 uint64_t rdx_s_e : 1;
2369 uint64_t pcf_p_e : 1;
2370 uint64_t pcf_p_f : 1;
2371 uint64_t pdf_p_e : 1;
2372 uint64_t pdf_p_f : 1;
2373 uint64_t q1_s_e : 1;
2374 uint64_t q1_a_f : 1;
2375 uint64_t reserved_62_63 : 2;
2381 uint64_t reserved_42_63 : 22;
2382 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
2384 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
2386 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
2388 uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
2390 uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
2392 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
2394 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
2396 uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
2398 uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
2400 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
2402 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
2404 uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
2406 uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
2408 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
2410 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
2412 uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
2414 uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
2416 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
2418 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
2420 uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an
2422 uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an
2424 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an
2426 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
2428 uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
2430 uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
2432 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
2434 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
2436 uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
2438 uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
2440 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
2442 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2444 uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
2446 uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
2448 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
2450 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2452 uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
2454 uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
2456 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
2458 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2460 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2462 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2464 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2467 uint64_t rml_rto : 1;
2468 uint64_t rml_wto : 1;
2469 uint64_t pci_rsl : 1;
2470 uint64_t po0_2sml : 1;
2471 uint64_t po1_2sml : 1;
2472 uint64_t po2_2sml : 1;
2473 uint64_t po3_2sml : 1;
2474 uint64_t i0_rtout : 1;
2475 uint64_t i1_rtout : 1;
2476 uint64_t i2_rtout : 1;
2477 uint64_t i3_rtout : 1;
2478 uint64_t i0_overf : 1;
2479 uint64_t i1_overf : 1;
2480 uint64_t i2_overf : 1;
2481 uint64_t i3_overf : 1;
2482 uint64_t p0_rtout : 1;
2483 uint64_t p1_rtout : 1;
2484 uint64_t p2_rtout : 1;
2485 uint64_t p3_rtout : 1;
2486 uint64_t p0_perr : 1;
2487 uint64_t p1_perr : 1;
2488 uint64_t p2_perr : 1;
2489 uint64_t p3_perr : 1;
2490 uint64_t g0_rtout : 1;
2491 uint64_t g1_rtout : 1;
2492 uint64_t g2_rtout : 1;
2493 uint64_t g3_rtout : 1;
2494 uint64_t p0_pperr : 1;
2495 uint64_t p1_pperr : 1;
2496 uint64_t p2_pperr : 1;
2497 uint64_t p3_pperr : 1;
2498 uint64_t p0_ptout : 1;
2499 uint64_t p1_ptout : 1;
2500 uint64_t p2_ptout : 1;
2501 uint64_t p3_ptout : 1;
2502 uint64_t i0_pperr : 1;
2503 uint64_t i1_pperr : 1;
2504 uint64_t i2_pperr : 1;
2505 uint64_t i3_pperr : 1;
2506 uint64_t win_rto : 1;
2507 uint64_t p_dperr : 1;
2508 uint64_t iobdma : 1;
2509 uint64_t reserved_42_63 : 22;
2526 uint64_t u64;
2529 uint64_t reserved_62_63 : 2;
2530 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full.
2532 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty.
2534 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO.
2536 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO.
2538 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO.
2540 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO.
2542 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0.
2544 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0.
2546 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max.
2548 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0.
2550 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max.
2552 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0.
2554 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full.
2556 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty.
2558 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full.
2560 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty.
2562 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full.
2564 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty.
2566 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full.
2568 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty.
2570 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2571 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2573 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2574 uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction
2576 uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction
2578 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction
2580 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2582 uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO
2584 uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO
2586 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO
2588 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2590 uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2592 uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2594 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2596 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2598 uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to
2600 uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to
2602 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2604 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2606 uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet
2608 uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet
2610 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet
2612 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
2614 uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to
2616 uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to
2618 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2620 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2622 uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the
2624 uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the
2626 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the
2628 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
2630 uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to
2632 uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to
2634 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2636 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2638 uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller
2640 uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller
2642 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller
2644 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
2646 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
2648 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
2651 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
2655 uint64_t rml_rto : 1;
2656 uint64_t rml_wto : 1;
2657 uint64_t pci_rsl : 1;
2658 uint64_t po0_2sml : 1;
2659 uint64_t po1_2sml : 1;
2660 uint64_t po2_2sml : 1;
2661 uint64_t po3_2sml : 1;
2662 uint64_t i0_rtout : 1;
2663 uint64_t i1_rtout : 1;
2664 uint64_t i2_rtout : 1;
2665 uint64_t i3_rtout : 1;
2666 uint64_t i0_overf : 1;
2667 uint64_t i1_overf : 1;
2668 uint64_t i2_overf : 1;
2669 uint64_t i3_overf : 1;
2670 uint64_t p0_rtout : 1;
2671 uint64_t p1_rtout : 1;
2672 uint64_t p2_rtout : 1;
2673 uint64_t p3_rtout : 1;
2674 uint64_t p0_perr : 1;
2675 uint64_t p1_perr : 1;
2676 uint64_t p2_perr : 1;
2677 uint64_t p3_perr : 1;
2678 uint64_t g0_rtout : 1;
2679 uint64_t g1_rtout : 1;
2680 uint64_t g2_rtout : 1;
2681 uint64_t g3_rtout : 1;
2682 uint64_t p0_pperr : 1;
2683 uint64_t p1_pperr : 1;
2684 uint64_t p2_pperr : 1;
2685 uint64_t p3_pperr : 1;
2686 uint64_t p0_ptout : 1;
2687 uint64_t p1_ptout : 1;
2688 uint64_t p2_ptout : 1;
2689 uint64_t p3_ptout : 1;
2690 uint64_t i0_pperr : 1;
2691 uint64_t i1_pperr : 1;
2692 uint64_t i2_pperr : 1;
2693 uint64_t i3_pperr : 1;
2694 uint64_t win_rto : 1;
2695 uint64_t p_dperr : 1;
2696 uint64_t iobdma : 1;
2697 uint64_t fcr_s_e : 1;
2698 uint64_t fcr_a_f : 1;
2699 uint64_t pcr_s_e : 1;
2700 uint64_t pcr_a_f : 1;
2701 uint64_t q2_s_e : 1;
2702 uint64_t q2_a_f : 1;
2703 uint64_t q3_s_e : 1;
2704 uint64_t q3_a_f : 1;
2705 uint64_t com_s_e : 1;
2706 uint64_t com_a_f : 1;
2707 uint64_t pnc_s_e : 1;
2708 uint64_t pnc_a_f : 1;
2709 uint64_t rwx_s_e : 1;
2710 uint64_t rdx_s_e : 1;
2711 uint64_t pcf_p_e : 1;
2712 uint64_t pcf_p_f : 1;
2713 uint64_t pdf_p_e : 1;
2714 uint64_t pdf_p_f : 1;
2715 uint64_t q1_s_e : 1;
2716 uint64_t q1_a_f : 1;
2717 uint64_t reserved_62_63 : 2;
2722 uint64_t reserved_62_63 : 2;
2723 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */
2724 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */
2725 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */
2726 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */
2727 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */
2728 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */
2729 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
2730 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
2731 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */
2732 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */
2733 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */
2734 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */
2735 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */
2736 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */
2737 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */
2738 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */
2739 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */
2740 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */
2741 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */
2742 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */
2743 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2744 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2746 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2747 uint64_t reserved_36_38 : 3;
2748 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2750 uint64_t reserved_32_34 : 3;
2751 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2753 uint64_t reserved_28_30 : 3;
2754 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2756 uint64_t reserved_24_26 : 3;
2757 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2759 uint64_t reserved_20_22 : 3;
2760 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
2762 uint64_t reserved_16_18 : 3;
2763 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2765 uint64_t reserved_12_14 : 3;
2766 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
2768 uint64_t reserved_8_10 : 3;
2769 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2771 uint64_t reserved_4_6 : 3;
2772 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
2774 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
2776 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
2779 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
2783 uint64_t rml_rto : 1;
2784 uint64_t rml_wto : 1;
2785 uint64_t pci_rsl : 1;
2786 uint64_t po0_2sml : 1;
2787 uint64_t reserved_4_6 : 3;
2788 uint64_t i0_rtout : 1;
2789 uint64_t reserved_8_10 : 3;
2790 uint64_t i0_overf : 1;
2791 uint64_t reserved_12_14 : 3;
2792 uint64_t p0_rtout : 1;
2793 uint64_t reserved_16_18 : 3;
2794 uint64_t p0_perr : 1;
2795 uint64_t reserved_20_22 : 3;
2796 uint64_t g0_rtout : 1;
2797 uint64_t reserved_24_26 : 3;
2798 uint64_t p0_pperr : 1;
2799 uint64_t reserved_28_30 : 3;
2800 uint64_t p0_ptout : 1;
2801 uint64_t reserved_32_34 : 3;
2802 uint64_t i0_pperr : 1;
2803 uint64_t reserved_36_38 : 3;
2804 uint64_t win_rto : 1;
2805 uint64_t p_dperr : 1;
2806 uint64_t iobdma : 1;
2807 uint64_t fcr_s_e : 1;
2808 uint64_t fcr_a_f : 1;
2809 uint64_t pcr_s_e : 1;
2810 uint64_t pcr_a_f : 1;
2811 uint64_t q2_s_e : 1;
2812 uint64_t q2_a_f : 1;
2813 uint64_t q3_s_e : 1;
2814 uint64_t q3_a_f : 1;
2815 uint64_t com_s_e : 1;
2816 uint64_t com_a_f : 1;
2817 uint64_t pnc_s_e : 1;
2818 uint64_t pnc_a_f : 1;
2819 uint64_t rwx_s_e : 1;
2820 uint64_t rdx_s_e : 1;
2821 uint64_t pcf_p_e : 1;
2822 uint64_t pcf_p_f : 1;
2823 uint64_t pdf_p_e : 1;
2824 uint64_t pdf_p_f : 1;
2825 uint64_t q1_s_e : 1;
2826 uint64_t q1_a_f : 1;
2827 uint64_t reserved_62_63 : 2;
2832 uint64_t reserved_62_63 : 2;
2833 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */
2834 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */
2835 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */
2836 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */
2837 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */
2838 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */
2839 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
2840 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
2841 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */
2842 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */
2843 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */
2844 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */
2845 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */
2846 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */
2847 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */
2848 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */
2849 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */
2850 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */
2851 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */
2852 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */
2853 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2854 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2856 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2857 uint64_t reserved_37_38 : 2;
2858 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction
2860 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2862 uint64_t reserved_33_34 : 2;
2863 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO
2865 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2867 uint64_t reserved_29_30 : 2;
2868 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2870 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2872 uint64_t reserved_25_26 : 2;
2873 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2875 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2877 uint64_t reserved_21_22 : 2;
2878 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet
2880 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
2882 uint64_t reserved_17_18 : 2;
2883 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2885 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2887 uint64_t reserved_13_14 : 2;
2888 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the
2890 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
2892 uint64_t reserved_9_10 : 2;
2893 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2895 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2897 uint64_t reserved_5_6 : 2;
2898 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller
2900 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
2902 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
2904 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
2907 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
2911 uint64_t rml_rto : 1;
2912 uint64_t rml_wto : 1;
2913 uint64_t pci_rsl : 1;
2914 uint64_t po0_2sml : 1;
2915 uint64_t po1_2sml : 1;
2916 uint64_t reserved_5_6 : 2;
2917 uint64_t i0_rtout : 1;
2918 uint64_t i1_rtout : 1;
2919 uint64_t reserved_9_10 : 2;
2920 uint64_t i0_overf : 1;
2921 uint64_t i1_overf : 1;
2922 uint64_t reserved_13_14 : 2;
2923 uint64_t p0_rtout : 1;
2924 uint64_t p1_rtout : 1;
2925 uint64_t reserved_17_18 : 2;
2926 uint64_t p0_perr : 1;
2927 uint64_t p1_perr : 1;
2928 uint64_t reserved_21_22 : 2;
2929 uint64_t g0_rtout : 1;
2930 uint64_t g1_rtout : 1;
2931 uint64_t reserved_25_26 : 2;
2932 uint64_t p0_pperr : 1;
2933 uint64_t p1_pperr : 1;
2934 uint64_t reserved_29_30 : 2;
2935 uint64_t p0_ptout : 1;
2936 uint64_t p1_ptout : 1;
2937 uint64_t reserved_33_34 : 2;
2938 uint64_t i0_pperr : 1;
2939 uint64_t i1_pperr : 1;
2940 uint64_t reserved_37_38 : 2;
2941 uint64_t win_rto : 1;
2942 uint64_t p_dperr : 1;
2943 uint64_t iobdma : 1;
2944 uint64_t fcr_s_e : 1;
2945 uint64_t fcr_a_f : 1;
2946 uint64_t pcr_s_e : 1;
2947 uint64_t pcr_a_f : 1;
2948 uint64_t q2_s_e : 1;
2949 uint64_t q2_a_f : 1;
2950 uint64_t q3_s_e : 1;
2951 uint64_t q3_a_f : 1;
2952 uint64_t com_s_e : 1;
2953 uint64_t com_a_f : 1;
2954 uint64_t pnc_s_e : 1;
2955 uint64_t pnc_a_f : 1;
2956 uint64_t rwx_s_e : 1;
2957 uint64_t rdx_s_e : 1;
2958 uint64_t pcf_p_e : 1;
2959 uint64_t pcf_p_f : 1;
2960 uint64_t pdf_p_e : 1;
2961 uint64_t pdf_p_f : 1;
2962 uint64_t q1_s_e : 1;
2963 uint64_t q1_a_f : 1;
2964 uint64_t reserved_62_63 : 2;
2970 uint64_t reserved_42_63 : 22;
2971 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2972 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2974 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2975 uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction
2977 uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction
2979 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction
2981 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2983 uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO
2985 uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO
2987 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO
2989 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2991 uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2993 uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2995 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2997 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2999 uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to
3001 uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to
3003 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to
3005 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
3007 uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet
3009 uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet
3011 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet
3013 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
3015 uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to
3017 uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to
3019 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to
3021 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
3023 uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the
3025 uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the
3027 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the
3029 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
3031 uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to
3033 uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to
3035 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to
3037 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
3039 uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller
3041 uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller
3043 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller
3045 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
3047 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
3049 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
3052 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
3056 uint64_t rml_rto : 1;
3057 uint64_t rml_wto : 1;
3058 uint64_t pci_rsl : 1;
3059 uint64_t po0_2sml : 1;
3060 uint64_t po1_2sml : 1;
3061 uint64_t po2_2sml : 1;
3062 uint64_t po3_2sml : 1;
3063 uint64_t i0_rtout : 1;
3064 uint64_t i1_rtout : 1;
3065 uint64_t i2_rtout : 1;
3066 uint64_t i3_rtout : 1;
3067 uint64_t i0_overf : 1;
3068 uint64_t i1_overf : 1;
3069 uint64_t i2_overf : 1;
3070 uint64_t i3_overf : 1;
3071 uint64_t p0_rtout : 1;
3072 uint64_t p1_rtout : 1;
3073 uint64_t p2_rtout : 1;
3074 uint64_t p3_rtout : 1;
3075 uint64_t p0_perr : 1;
3076 uint64_t p1_perr : 1;
3077 uint64_t p2_perr : 1;
3078 uint64_t p3_perr : 1;
3079 uint64_t g0_rtout : 1;
3080 uint64_t g1_rtout : 1;
3081 uint64_t g2_rtout : 1;
3082 uint64_t g3_rtout : 1;
3083 uint64_t p0_pperr : 1;
3084 uint64_t p1_pperr : 1;
3085 uint64_t p2_pperr : 1;
3086 uint64_t p3_pperr : 1;
3087 uint64_t p0_ptout : 1;
3088 uint64_t p1_ptout : 1;
3089 uint64_t p2_ptout : 1;
3090 uint64_t p3_ptout : 1;
3091 uint64_t i0_pperr : 1;
3092 uint64_t i1_pperr : 1;
3093 uint64_t i2_pperr : 1;
3094 uint64_t i3_pperr : 1;
3095 uint64_t win_rto : 1;
3096 uint64_t p_dperr : 1;
3097 uint64_t iobdma : 1;
3098 uint64_t reserved_42_63 : 22;
3115 uint64_t u64;
3118 uint64_t reserved_16_63 : 48;
3119 uint64_t dbell : 16; /**< The value written to this register is added to the
3123 uint64_t dbell : 16;
3124 uint64_t reserved_16_63 : 48;
3145 uint64_t u64;
3148 uint64_t reserved_36_63 : 28;
3149 uint64_t saddr : 36; /**< The starting address to read the first instruction. */
3151 uint64_t saddr : 36;
3152 uint64_t reserved_36_63 : 28;
3176 uint64_t u64;
3179 uint64_t reserved_38_63 : 26;
3180 uint64_t shortl : 1; /**< Generate CMD-6 on PCI(x) when '1'.
3191 uint64_t nmerge : 1; /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */
3192 uint64_t esr : 2; /**< Endian-Swap on read. */
3193 uint64_t esw : 2; /**< Endian-Swap on write. */
3194 uint64_t nsr : 1; /**< No-Snoop on read. */
3195 uint64_t nsw : 1; /**< No-Snoop on write. */
3196 uint64_t ror : 1; /**< Relax Read on read. */
3197 uint64_t row : 1; /**< Relax Order on write. */
3198 uint64_t ba : 28; /**< PCI Address bits [63:36]. */
3200 uint64_t ba : 28;
3201 uint64_t row : 1;
3202 uint64_t ror : 1;
3203 uint64_t nsw : 1;
3204 uint64_t nsr : 1;
3205 uint64_t esw : 2;
3206 uint64_t esr : 2;
3207 uint64_t nmerge : 1;
3208 uint64_t shortl : 1;
3209 uint64_t reserved_38_63 : 26;
3215 uint64_t reserved_36_63 : 28;
3216 uint64_t esr : 2; /**< Endian-Swap on read. */
3217 uint64_t esw : 2; /**< Endian-Swap on write. */
3218 uint64_t nsr : 1; /**< No-Snoop on read. */
3219 uint64_t nsw : 1; /**< No-Snoop on write. */
3220 uint64_t ror : 1; /**< Relax Read on read. */
3221 uint64_t row : 1; /**< Relax Order on write. */
3222 uint64_t ba : 28; /**< PCI Address bits [63:36]. */
3224 uint64_t ba : 28;
3225 uint64_t row : 1;
3226 uint64_t ror : 1;
3227 uint64_t nsw : 1;
3228 uint64_t nsr : 1;
3229 uint64_t esw : 2;
3230 uint64_t esr : 2;
3231 uint64_t reserved_36_63 : 28;
3250 uint64_t u64;
3253 uint64_t int_vec : 64; /**< Refer to PCI_MSI_RCV */
3255 uint64_t int_vec : 64;
3276 uint64_t u64;
3279 uint64_t reserved_32_63 : 32;
3280 uint64_t size : 32; /**< The size of the Buffer/Info Pointer Pair ring. */
3282 uint64_t size : 32;
3283 uint64_t reserved_32_63 : 32;
3304 uint64_t u64;
3307 uint64_t reserved_49_63 : 15;
3308 uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be
3313 uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be
3317 uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be
3321 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3325 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3329 uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */
3330 uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */
3331 uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */
3332 uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */
3333 uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */
3334 uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */
3335 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3336 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3337 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3338 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3339 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3340 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3341 uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3348 uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3355 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3362 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3369 uint64_t reserved_20_23 : 4;
3370 uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data
3372 uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data
3374 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3376 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3378 uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */
3379 uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */
3380 uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */
3381 uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */
3382 uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */
3383 uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */
3384 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3385 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3386 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3387 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3388 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3389 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3391 uint64_t ror_sl0 : 1;
3392 uint64_t nsr_sl0 : 1;
3393 uint64_t esr_sl0 : 2;
3394 uint64_t ror_sl1 : 1;
3395 uint64_t nsr_sl1 : 1;
3396 uint64_t esr_sl1 : 2;
3397 uint64_t ror_sl2 : 1;
3398 uint64_t nsr_sl2 : 1;
3399 uint64_t esr_sl2 : 2;
3400 uint64_t ror_sl3 : 1;
3401 uint64_t nsr_sl3 : 1;
3402 uint64_t esr_sl3 : 2;
3403 uint64_t iptr_o0 : 1;
3404 uint64_t iptr_o1 : 1;
3405 uint64_t iptr_o2 : 1;
3406 uint64_t iptr_o3 : 1;
3407 uint64_t reserved_20_23 : 4;
3408 uint64_t o0_csrm : 1;
3409 uint64_t o1_csrm : 1;
3410 uint64_t o2_csrm : 1;
3411 uint64_t o3_csrm : 1;
3412 uint64_t o0_ro : 1;
3413 uint64_t o0_ns : 1;
3414 uint64_t o0_es : 2;
3415 uint64_t o1_ro : 1;
3416 uint64_t o1_ns : 1;
3417 uint64_t o1_es : 2;
3418 uint64_t o2_ro : 1;
3419 uint64_t o2_ns : 1;
3420 uint64_t o2_es : 2;
3421 uint64_t o3_ro : 1;
3422 uint64_t o3_ns : 1;
3423 uint64_t o3_es : 2;
3424 uint64_t p0_bmode : 1;
3425 uint64_t p1_bmode : 1;
3426 uint64_t p2_bmode : 1;
3427 uint64_t p3_bmode : 1;
3428 uint64_t pkt_rr : 1;
3429 uint64_t reserved_49_63 : 15;
3434 uint64_t reserved_45_63 : 19;
3435 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3439 uint64_t reserved_32_43 : 12;
3440 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3441 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3442 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3443 uint64_t reserved_25_27 : 3;
3444 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3451 uint64_t reserved_17_23 : 7;
3452 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3454 uint64_t reserved_4_15 : 12;
3455 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3456 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3457 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3459 uint64_t ror_sl0 : 1;
3460 uint64_t nsr_sl0 : 1;
3461 uint64_t esr_sl0 : 2;
3462 uint64_t reserved_4_15 : 12;
3463 uint64_t iptr_o0 : 1;
3464 uint64_t reserved_17_23 : 7;
3465 uint64_t o0_csrm : 1;
3466 uint64_t reserved_25_27 : 3;
3467 uint64_t o0_ro : 1;
3468 uint64_t o0_ns : 1;
3469 uint64_t o0_es : 2;
3470 uint64_t reserved_32_43 : 12;
3471 uint64_t p0_bmode : 1;
3472 uint64_t reserved_45_63 : 19;
3477 uint64_t reserved_46_63 : 18;
3478 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3482 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3486 uint64_t reserved_36_43 : 8;
3487 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3488 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3489 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3490 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3491 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3492 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3493 uint64_t reserved_26_27 : 2;
3494 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3501 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3508 uint64_t reserved_18_23 : 6;
3509 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3511 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3513 uint64_t reserved_8_15 : 8;
3514 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3515 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3516 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3517 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3518 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3519 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3521 uint64_t ror_sl0 : 1;
3522 uint64_t nsr_sl0 : 1;
3523 uint64_t esr_sl0 : 2;
3524 uint64_t ror_sl1 : 1;
3525 uint64_t nsr_sl1 : 1;
3526 uint64_t esr_sl1 : 2;
3527 uint64_t reserved_8_15 : 8;
3528 uint64_t iptr_o0 : 1;
3529 uint64_t iptr_o1 : 1;
3530 uint64_t reserved_18_23 : 6;
3531 uint64_t o0_csrm : 1;
3532 uint64_t o1_csrm : 1;
3533 uint64_t reserved_26_27 : 2;
3534 uint64_t o0_ro : 1;
3535 uint64_t o0_ns : 1;
3536 uint64_t o0_es : 2;
3537 uint64_t o1_ro : 1;
3538 uint64_t o1_ns : 1;
3539 uint64_t o1_es : 2;
3540 uint64_t reserved_36_43 : 8;
3541 uint64_t p0_bmode : 1;
3542 uint64_t p1_bmode : 1;
3543 uint64_t reserved_46_63 : 18;
3549 uint64_t reserved_48_63 : 16;
3550 uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be
3554 uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be
3558 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3562 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3566 uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */
3567 uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */
3568 uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */
3569 uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */
3570 uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */
3571 uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */
3572 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3573 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3574 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3575 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3576 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3577 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3578 uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3585 uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3592 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3599 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3606 uint64_t reserved_20_23 : 4;
3607 uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data
3609 uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data
3611 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3613 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3615 uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */
3616 uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */
3617 uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */
3618 uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */
3619 uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */
3620 uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */
3621 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3622 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3623 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3624 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3625 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3626 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3628 uint64_t ror_sl0 : 1;
3629 uint64_t nsr_sl0 : 1;
3630 uint64_t esr_sl0 : 2;
3631 uint64_t ror_sl1 : 1;
3632 uint64_t nsr_sl1 : 1;
3633 uint64_t esr_sl1 : 2;
3634 uint64_t ror_sl2 : 1;
3635 uint64_t nsr_sl2 : 1;
3636 uint64_t esr_sl2 : 2;
3637 uint64_t ror_sl3 : 1;
3638 uint64_t nsr_sl3 : 1;
3639 uint64_t esr_sl3 : 2;
3640 uint64_t iptr_o0 : 1;
3641 uint64_t iptr_o1 : 1;
3642 uint64_t iptr_o2 : 1;
3643 uint64_t iptr_o3 : 1;
3644 uint64_t reserved_20_23 : 4;
3645 uint64_t o0_csrm : 1;
3646 uint64_t o1_csrm : 1;
3647 uint64_t o2_csrm : 1;
3648 uint64_t o3_csrm : 1;
3649 uint64_t o0_ro : 1;
3650 uint64_t o0_ns : 1;
3651 uint64_t o0_es : 2;
3652 uint64_t o1_ro : 1;
3653 uint64_t o1_ns : 1;
3654 uint64_t o1_es : 2;
3655 uint64_t o2_ro : 1;
3656 uint64_t o2_ns : 1;
3657 uint64_t o2_es : 2;
3658 uint64_t o3_ro : 1;
3659 uint64_t o3_ns : 1;
3660 uint64_t o3_es : 2;
3661 uint64_t p0_bmode : 1;
3662 uint64_t p1_bmode : 1;
3663 uint64_t p2_bmode : 1;
3664 uint64_t p3_bmode : 1;
3665 uint64_t reserved_48_63 : 16;
3670 uint64_t reserved_49_63 : 15;
3671 uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be
3676 uint64_t reserved_46_47 : 2;
3677 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3681 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3685 uint64_t reserved_36_43 : 8;
3686 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3687 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3688 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3689 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3690 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3691 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3692 uint64_t reserved_26_27 : 2;
3693 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3700 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3707 uint64_t reserved_18_23 : 6;
3708 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3710 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3712 uint64_t reserved_8_15 : 8;
3713 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3714 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3715 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3716 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3717 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3718 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3720 uint64_t ror_sl0 : 1;
3721 uint64_t nsr_sl0 : 1;
3722 uint64_t esr_sl0 : 2;
3723 uint64_t ror_sl1 : 1;
3724 uint64_t nsr_sl1 : 1;
3725 uint64_t esr_sl1 : 2;
3726 uint64_t reserved_8_15 : 8;
3727 uint64_t iptr_o0 : 1;
3728 uint64_t iptr_o1 : 1;
3729 uint64_t reserved_18_23 : 6;
3730 uint64_t o0_csrm : 1;
3731 uint64_t o1_csrm : 1;
3732 uint64_t reserved_26_27 : 2;
3733 uint64_t o0_ro : 1;
3734 uint64_t o0_ns : 1;
3735 uint64_t o0_es : 2;
3736 uint64_t o1_ro : 1;
3737 uint64_t o1_ns : 1;
3738 uint64_t o1_es : 2;
3739 uint64_t reserved_36_43 : 8;
3740 uint64_t p0_bmode : 1;
3741 uint64_t p1_bmode : 1;
3742 uint64_t reserved_46_47 : 2;
3743 uint64_t pkt_rr : 1;
3744 uint64_t reserved_49_63 : 15;
3760 uint64_t u64;
3763 uint64_t reserved_63_63 : 1;
3764 uint64_t state : 2; /**< POS state machine vector. Used to tell when NADDR
3766 uint64_t naddr : 61; /**< Bits [63:3] of the next Data-Info Pair to read.
3769 uint64_t naddr : 61;
3770 uint64_t state : 2;
3771 uint64_t reserved_63_63 : 1;
3792 uint64_t u64;
3795 uint64_t state : 3; /**< Gather engine state vector. Used to tell when
3797 uint64_t naddr : 61; /**< Bits [63:3] of the next Instruction to read.
3800 uint64_t naddr : 61;
3801 uint64_t state : 3;
3822 uint64_t u64;
3825 uint64_t reserved_38_63 : 26;
3826 uint64_t fcnt : 6; /**< Number entries in the Instruction FIFO. */
3827 uint64_t avail : 32; /**< Doorbell count to be read. */
3829 uint64_t avail : 32;
3830 uint64_t fcnt : 6;
3831 uint64_t reserved_38_63 : 26;
3852 uint64_t u64;
3855 uint64_t reserved_37_63 : 27;
3856 uint64_t fcnt : 5; /**< 16 - number entries in the D/I Pair FIFO. */
3857 uint64_t avail : 32; /**< Doorbell count to be read. */
3859 uint64_t avail : 32;
3860 uint64_t fcnt : 5;
3861 uint64_t reserved_37_63 : 27;
3882 uint64_t u64;
3885 uint64_t reserved_14_63 : 50;
3886 uint64_t wr_brst : 7; /**< The number of 8B words to write to PCI in any one
3890 uint64_t rd_brst : 7; /**< Number of 8B words to read from PCI in any one
3898 uint64_t rd_brst : 7;
3899 uint64_t wr_brst : 7;
3900 uint64_t reserved_14_63 : 50;
3923 uint64_t u64;
3926 uint64_t reserved_13_63 : 51;
3927 uint64_t hostmode : 1; /**< PCI Host Mode Pin (sampled for use by software).
3931 uint64_t pci_ovr : 4; /**< PCI Host Mode Bus Speed/Type Override
3981 uint64_t reserved_5_7 : 3;
3982 uint64_t en : 1; /**< Internal arbiter enable. */
3983 uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */
3984 uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */
3986 uint64_t park_dev : 3;
3987 uint64_t park_mod : 1;
3988 uint64_t en : 1;
3989 uint64_t reserved_5_7 : 3;
3990 uint64_t pci_ovr : 4;
3991 uint64_t hostmode : 1;
3992 uint64_t reserved_13_63 : 51;
3997 uint64_t reserved_5_63 : 59;
3998 uint64_t en : 1; /**< Internal arbiter enable. */
3999 uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */
4000 uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */
4002 uint64_t park_dev : 3;
4003 uint64_t park_mod : 1;
4004 uint64_t en : 1;
4005 uint64_t reserved_5_63 : 59;
4030 uint64_t u64;
4033 uint64_t reserved_11_63 : 53;
4034 uint64_t cmd_size : 11; /**< Number bytes to be read is equal to or exceeds this
4040 uint64_t cmd_size : 11;
4041 uint64_t reserved_11_63 : 53;
4062 uint64_t u64;
4065 uint64_t reserved_44_63 : 20;
4066 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4067 uint64_t rsv_f : 5; /**< Reserved */
4068 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4069 uint64_t rsv_e : 1; /**< Reserved */
4070 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4071 uint64_t rsv_d : 6; /**< Reserved */
4072 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4076 uint64_t rsv_c : 5; /**< Reserved */
4077 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4079 uint64_t rsv_b : 1; /**< Reserved
4081 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4083 uint64_t rsv_a : 6; /**< Reserved */
4085 uint64_t rsv_a : 6;
4086 uint64_t skp_len : 7;
4087 uint64_t rsv_b : 1;
4088 uint64_t par_mode : 2;
4089 uint64_t rsv_c : 5;
4090 uint64_t use_ihdr : 1;
4091 uint64_t rsv_d : 6;
4092 uint64_t rskp_len : 7;
4093 uint64_t rsv_e : 1;
4094 uint64_t rparmode : 2;
4095 uint64_t rsv_f : 5;
4096 uint64_t pbp : 1;
4097 uint64_t reserved_44_63 : 20;
4118 uint64_t u64;
4121 uint64_t reserved_44_63 : 20;
4122 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4123 uint64_t rsv_f : 5; /**< Reserved */
4124 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4125 uint64_t rsv_e : 1; /**< Reserved */
4126 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4127 uint64_t rsv_d : 6; /**< Reserved */
4128 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4132 uint64_t rsv_c : 5; /**< Reserved */
4133 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4135 uint64_t rsv_b : 1; /**< Reserved
4137 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4139 uint64_t rsv_a : 6; /**< Reserved */
4141 uint64_t rsv_a : 6;
4142 uint64_t skp_len : 7;
4143 uint64_t rsv_b : 1;
4144 uint64_t par_mode : 2;
4145 uint64_t rsv_c : 5;
4146 uint64_t use_ihdr : 1;
4147 uint64_t rsv_d : 6;
4148 uint64_t rskp_len : 7;
4149 uint64_t rsv_e : 1;
4150 uint64_t rparmode : 2;
4151 uint64_t rsv_f : 5;
4152 uint64_t pbp : 1;
4153 uint64_t reserved_44_63 : 20;
4173 uint64_t u64;
4176 uint64_t reserved_44_63 : 20;
4177 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4178 uint64_t rsv_f : 5; /**< Reserved */
4179 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4180 uint64_t rsv_e : 1; /**< Reserved */
4181 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4182 uint64_t rsv_d : 6; /**< Reserved */
4183 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4187 uint64_t rsv_c : 5; /**< Reserved */
4188 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4190 uint64_t rsv_b : 1; /**< Reserved
4192 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4194 uint64_t rsv_a : 6; /**< Reserved */
4196 uint64_t rsv_a : 6;
4197 uint64_t skp_len : 7;
4198 uint64_t rsv_b : 1;
4199 uint64_t par_mode : 2;
4200 uint64_t rsv_c : 5;
4201 uint64_t use_ihdr : 1;
4202 uint64_t rsv_d : 6;
4203 uint64_t rskp_len : 7;
4204 uint64_t rsv_e : 1;
4205 uint64_t rparmode : 2;
4206 uint64_t rsv_f : 5;
4207 uint64_t pbp : 1;
4208 uint64_t reserved_44_63 : 20;
4226 uint64_t u64;
4229 uint64_t reserved_44_63 : 20;
4230 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4231 uint64_t rsv_f : 5; /**< Reserved */
4232 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4233 uint64_t rsv_e : 1; /**< Reserved */
4234 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4235 uint64_t rsv_d : 6; /**< Reserved */
4236 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4240 uint64_t rsv_c : 5; /**< Reserved */
4241 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4243 uint64_t rsv_b : 1; /**< Reserved
4245 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4247 uint64_t rsv_a : 6; /**< Reserved */
4249 uint64_t rsv_a : 6;
4250 uint64_t skp_len : 7;
4251 uint64_t rsv_b : 1;
4252 uint64_t par_mode : 2;
4253 uint64_t rsv_c : 5;
4254 uint64_t use_ihdr : 1;
4255 uint64_t rsv_d : 6;
4256 uint64_t rskp_len : 7;
4257 uint64_t rsv_e : 1;
4258 uint64_t rparmode : 2;
4259 uint64_t rsv_f : 5;
4260 uint64_t pbp : 1;
4261 uint64_t reserved_44_63 : 20;
4279 uint64_t u64;
4282 uint64_t reserved_8_63 : 56;
4283 uint64_t bp_on : 4; /**< Port 35-32 port level backpressure applied. */
4284 uint64_t enb : 4; /**< Enables port level backpressure from the IPD. */
4286 uint64_t enb : 4;
4287 uint64_t bp_on : 4;
4288 uint64_t reserved_8_63 : 56;
4311 uint64_t u64;
4314 uint64_t reserved_32_63 : 32;
4315 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4316 uint64_t iob : 1; /**< IOB_INT_SUM */
4317 uint64_t reserved_28_29 : 2;
4318 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4319 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4320 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4321 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4322 uint64_t asx1 : 1; /**< ASX1_INT_REG */
4323 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4324 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4325 uint64_t pip : 1; /**< PIP_INT_REG. */
4326 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */
4327 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */
4328 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4329 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4330 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4331 uint64_t reserved_13_14 : 2;
4332 uint64_t pow : 1; /**< POW_ECC_ERR */
4333 uint64_t tim : 1; /**< TIM_REG_ERROR */
4334 uint64_t pko : 1; /**< PKO_REG_ERROR */
4335 uint64_t ipd : 1; /**< IPD_INT_SUM */
4336 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4337 uint64_t zip : 1; /**< ZIP_ERROR */
4338 uint64_t dfa : 1; /**< DFA_ERR */
4339 uint64_t fpa : 1; /**< FPA_INT_SUM */
4340 uint64_t key : 1; /**< KEY_INT_SUM */
4341 uint64_t npi : 1; /**< NPI_INT_SUM */
4342 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
4343 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4344 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4346 uint64_t mio : 1;
4347 uint64_t gmx0 : 1;
4348 uint64_t gmx1 : 1;
4349 uint64_t npi : 1;
4350 uint64_t key : 1;
4351 uint64_t fpa : 1;
4352 uint64_t dfa : 1;
4353 uint64_t zip : 1;
4354 uint64_t rint_8 : 1;
4355 uint64_t ipd : 1;
4356 uint64_t pko : 1;
4357 uint64_t tim : 1;
4358 uint64_t pow : 1;
4359 uint64_t reserved_13_14 : 2;
4360 uint64_t rint_15 : 1;
4361 uint64_t l2c : 1;
4362 uint64_t lmc : 1;
4363 uint64_t spx0 : 1;
4364 uint64_t spx1 : 1;
4365 uint64_t pip : 1;
4366 uint64_t rint_21 : 1;
4367 uint64_t asx0 : 1;
4368 uint64_t asx1 : 1;
4369 uint64_t rint_24 : 1;
4370 uint64_t rint_25 : 1;
4371 uint64_t rint_26 : 1;
4372 uint64_t rint_27 : 1;
4373 uint64_t reserved_28_29 : 2;
4374 uint64_t iob : 1;
4375 uint64_t rint_31 : 1;
4376 uint64_t reserved_32_63 : 32;
4381 uint64_t reserved_32_63 : 32;
4382 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4383 uint64_t iob : 1; /**< IOB_INT_SUM */
4384 uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4385 uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4386 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4387 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4388 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4389 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4390 uint64_t asx1 : 1; /**< ASX1_INT_REG */
4391 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4392 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4393 uint64_t pip : 1; /**< PIP_INT_REG. */
4394 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */
4395 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */
4396 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4397 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4398 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4399 uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4400 uint64_t usb : 1; /**< USBN_INT_SUM */
4401 uint64_t pow : 1; /**< POW_ECC_ERR */
4402 uint64_t tim : 1; /**< TIM_REG_ERROR */
4403 uint64_t pko : 1; /**< PKO_REG_ERROR */
4404 uint64_t ipd : 1; /**< IPD_INT_SUM */
4405 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4406 uint64_t zip : 1; /**< ZIP_ERROR */
4407 uint64_t dfa : 1; /**< DFA_ERR */
4408 uint64_t fpa : 1; /**< FPA_INT_SUM */
4409 uint64_t key : 1; /**< Set '1' when RSL bLock has an interrupt. */
4410 uint64_t npi : 1; /**< NPI_INT_SUM */
4411 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
4412 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4413 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4415 uint64_t mio : 1;
4416 uint64_t gmx0 : 1;
4417 uint64_t gmx1 : 1;
4418 uint64_t npi : 1;
4419 uint64_t key : 1;
4420 uint64_t fpa : 1;
4421 uint64_t dfa : 1;
4422 uint64_t zip : 1;
4423 uint64_t rint_8 : 1;
4424 uint64_t ipd : 1;
4425 uint64_t pko : 1;
4426 uint64_t tim : 1;
4427 uint64_t pow : 1;
4428 uint64_t usb : 1;
4429 uint64_t rint_14 : 1;
4430 uint64_t rint_15 : 1;
4431 uint64_t l2c : 1;
4432 uint64_t lmc : 1;
4433 uint64_t spx0 : 1;
4434 uint64_t spx1 : 1;
4435 uint64_t pip : 1;
4436 uint64_t rint_21 : 1;
4437 uint64_t asx0 : 1;
4438 uint64_t asx1 : 1;
4439 uint64_t rint_24 : 1;
4440 uint64_t rint_25 : 1;
4441 uint64_t rint_26 : 1;
4442 uint64_t rint_27 : 1;
4443 uint64_t rint_28 : 1;
4444 uint64_t rint_29 : 1;
4445 uint64_t iob : 1;
4446 uint64_t rint_31 : 1;
4447 uint64_t reserved_32_63 : 32;
4453 uint64_t reserved_32_63 : 32;
4454 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4455 uint64_t iob : 1; /**< IOB_INT_SUM */
4456 uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4457 uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4458 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4459 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4460 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4461 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4462 uint64_t asx1 : 1; /**< ASX1_INT_REG */
4463 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4464 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4465 uint64_t pip : 1; /**< PIP_INT_REG. */
4466 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */
4467 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */
4468 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4469 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4470 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4471 uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4472 uint64_t rint_13 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4473 uint64_t pow : 1; /**< POW_ECC_ERR */
4474 uint64_t tim : 1; /**< TIM_REG_ERROR */
4475 uint64_t pko : 1; /**< PKO_REG_ERROR */
4476 uint64_t ipd : 1; /**< IPD_INT_SUM */
4477 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4478 uint64_t zip : 1; /**< ZIP_ERROR */
4479 uint64_t dfa : 1; /**< DFA_ERR */
4480 uint64_t fpa : 1; /**< FPA_INT_SUM */
4481 uint64_t key : 1; /**< KEY_INT_SUM */
4482 uint64_t npi : 1; /**< NPI_INT_SUM */
4483 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
4484 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4485 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4487 uint64_t mio : 1;
4488 uint64_t gmx0 : 1;
4489 uint64_t gmx1 : 1;
4490 uint64_t npi : 1;
4491 uint64_t key : 1;
4492 uint64_t fpa : 1;
4493 uint64_t dfa : 1;
4494 uint64_t zip : 1;
4495 uint64_t rint_8 : 1;
4496 uint64_t ipd : 1;
4497 uint64_t pko : 1;
4498 uint64_t tim : 1;
4499 uint64_t pow : 1;
4500 uint64_t rint_13 : 1;
4501 uint64_t rint_14 : 1;
4502 uint64_t rint_15 : 1;
4503 uint64_t l2c : 1;
4504 uint64_t lmc : 1;
4505 uint64_t spx0 : 1;
4506 uint64_t spx1 : 1;
4507 uint64_t pip : 1;
4508 uint64_t rint_21 : 1;
4509 uint64_t asx0 : 1;
4510 uint64_t asx1 : 1;
4511 uint64_t rint_24 : 1;
4512 uint64_t rint_25 : 1;
4513 uint64_t rint_26 : 1;
4514 uint64_t rint_27 : 1;
4515 uint64_t rint_28 : 1;
4516 uint64_t rint_29 : 1;
4517 uint64_t iob : 1;
4518 uint64_t rint_31 : 1;
4519 uint64_t reserved_32_63 : 32;
4525 uint64_t reserved_31_63 : 33;
4526 uint64_t iob : 1; /**< IOB_INT_SUM */
4527 uint64_t lmc1 : 1; /**< Always reads as zero */
4528 uint64_t agl : 1; /**< Always reads as zero */
4529 uint64_t reserved_24_27 : 4;
4530 uint64_t asx1 : 1; /**< Always reads as zero */
4531 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4532 uint64_t reserved_21_21 : 1;
4533 uint64_t pip : 1; /**< PIP_INT_REG. */
4534 uint64_t spx1 : 1; /**< Always reads as zero */
4535 uint64_t spx0 : 1; /**< Always reads as zero */
4536 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4537 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4538 uint64_t reserved_15_15 : 1;
4539 uint64_t rad : 1; /**< Always reads as zero */
4540 uint64_t usb : 1; /**< USBN_INT_SUM */
4541 uint64_t pow : 1; /**< POW_ECC_ERR */
4542 uint64_t tim : 1; /**< TIM_REG_ERROR */
4543 uint64_t pko : 1; /**< PKO_REG_ERROR */
4544 uint64_t ipd : 1; /**< IPD_INT_SUM */
4545 uint64_t reserved_8_8 : 1;
4546 uint64_t zip : 1; /**< Always reads as zero */
4547 uint64_t dfa : 1; /**< Always reads as zero */
4548 uint64_t fpa : 1; /**< FPA_INT_SUM */
4549 uint64_t key : 1; /**< Always reads as zero */
4550 uint64_t npi : 1; /**< NPI_INT_SUM */
4551 uint64_t gmx1 : 1; /**< Always reads as zero */
4552 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4553 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4555 uint64_t mio : 1;
4556 uint64_t gmx0 : 1;
4557 uint64_t gmx1 : 1;
4558 uint64_t npi : 1;
4559 uint64_t key : 1;
4560 uint64_t fpa : 1;
4561 uint64_t dfa : 1;
4562 uint64_t zip : 1;
4563 uint64_t reserved_8_8 : 1;
4564 uint64_t ipd : 1;
4565 uint64_t pko : 1;
4566 uint64_t tim : 1;
4567 uint64_t pow : 1;
4568 uint64_t usb : 1;
4569 uint64_t rad : 1;
4570 uint64_t reserved_15_15 : 1;
4571 uint64_t l2c : 1;
4572 uint64_t lmc : 1;
4573 uint64_t spx0 : 1;
4574 uint64_t spx1 : 1;
4575 uint64_t pip : 1;
4576 uint64_t reserved_21_21 : 1;
4577 uint64_t asx0 : 1;
4578 uint64_t asx1 : 1;
4579 uint64_t reserved_24_27 : 4;
4580 uint64_t agl : 1;
4581 uint64_t lmc1 : 1;
4582 uint64_t iob : 1;
4583 uint64_t reserved_31_63 : 33;
4599 uint64_t u64;
4602 uint64_t reserved_32_63 : 32;
4603 uint64_t size : 32; /**< The size of the Instruction Queue used by Octane.
4607 uint64_t size : 32;
4608 uint64_t reserved_32_63 : 32;
4629 uint64_t u64;
4632 uint64_t reserved_32_63 : 32;
4633 uint64_t time : 32; /**< Time to wait in core clocks. A value of 0 will
4636 uint64_t time : 32;
4637 uint64_t reserved_32_63 : 32;