Lines Matching refs:uint64_t
56 static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
69 static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
80 static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
91 static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
102 static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
113 static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
124 static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
135 static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
146 static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
157 static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
168 static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
179 static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
189 static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
201 static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
213 static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
225 static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
238 static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
249 static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
260 static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
271 static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void)
283 static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void)
298 static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
309 static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
320 static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
331 static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
342 static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
353 static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
364 static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
375 static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
386 static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
397 static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
408 static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
418 static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
431 static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
442 static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
453 static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
464 static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
475 static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
486 static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
497 static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
508 static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
519 static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
530 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
541 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
552 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
563 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
574 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
585 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
596 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
607 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
618 static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
629 static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
640 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
651 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
662 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
673 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
683 static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
695 static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
707 static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
719 static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
731 static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
743 static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
755 static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
767 static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
779 static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
792 static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
803 static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
814 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
825 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
836 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
847 static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
858 static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
869 static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
880 static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
891 static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
902 static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
913 static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
923 static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
936 static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
947 static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
958 static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
969 static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
980 static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
991 static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
1002 static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
1013 static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
1024 static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
1035 static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
1046 static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
1057 static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
1068 static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
1079 static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
1090 static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
1101 static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
1112 static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
1123 static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
1134 static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
1145 static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
1156 static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
1167 static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
1178 static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
1189 static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
1200 static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
1288 uint64_t u64;
1291 uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */
1292 uint64_t reserved_60_62 : 3;
1293 uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */
1294 uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */
1295 uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */
1296 uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */
1297 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */
1298 uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */
1299 uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */
1300 uint64_t reserved_50_52 : 3;
1301 uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */
1302 uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */
1303 uint64_t reserved_36_47 : 12;
1304 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1305 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1306 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1307 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1308 uint64_t reserved_31_31 : 1;
1309 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1310 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1311 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1312 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1313 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1314 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1315 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1316 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1317 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1318 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1319 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1320 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1321 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1322 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1323 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1324 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1325 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1326 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1327 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1328 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1329 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1330 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1331 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1332 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1333 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1334 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1335 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1336 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1337 uint64_t reserved_2_2 : 1;
1338 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1339 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1341 uint64_t ncb_cmd : 1;
1342 uint64_t msi : 1;
1343 uint64_t reserved_2_2 : 1;
1344 uint64_t dif3 : 1;
1345 uint64_t dif2 : 1;
1346 uint64_t dif1 : 1;
1347 uint64_t dif0 : 1;
1348 uint64_t csm1 : 1;
1349 uint64_t csm0 : 1;
1350 uint64_t p2n1_p1 : 1;
1351 uint64_t p2n1_p0 : 1;
1352 uint64_t p2n1_n : 1;
1353 uint64_t p2n1_c1 : 1;
1354 uint64_t p2n1_c0 : 1;
1355 uint64_t p2n0_p1 : 1;
1356 uint64_t p2n0_p0 : 1;
1357 uint64_t p2n0_n : 1;
1358 uint64_t p2n0_c1 : 1;
1359 uint64_t p2n0_c0 : 1;
1360 uint64_t p2n0_co : 1;
1361 uint64_t p2n0_no : 1;
1362 uint64_t p2n0_po : 1;
1363 uint64_t p2n1_co : 1;
1364 uint64_t p2n1_no : 1;
1365 uint64_t p2n1_po : 1;
1366 uint64_t cpl_p1 : 1;
1367 uint64_t cpl_p0 : 1;
1368 uint64_t n2p1_o : 1;
1369 uint64_t n2p1_c : 1;
1370 uint64_t n2p0_o : 1;
1371 uint64_t n2p0_c : 1;
1372 uint64_t reserved_31_31 : 1;
1373 uint64_t d3_pst : 1;
1374 uint64_t d2_pst : 1;
1375 uint64_t d1_pst : 1;
1376 uint64_t d0_pst : 1;
1377 uint64_t reserved_36_47 : 12;
1378 uint64_t pkt_slm : 1;
1379 uint64_t pkt_ind : 1;
1380 uint64_t reserved_50_52 : 3;
1381 uint64_t pcsr_sl : 1;
1382 uint64_t pcsr_id : 1;
1383 uint64_t pcsr_cnt : 1;
1384 uint64_t pcsr_im : 1;
1385 uint64_t pcsr_int : 1;
1386 uint64_t pkt_pif : 1;
1387 uint64_t pcr_gim : 1;
1388 uint64_t reserved_60_62 : 3;
1389 uint64_t pkt_rdf : 1;
1394 uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */
1395 uint64_t reserved_60_62 : 3;
1396 uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */
1397 uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */
1398 uint64_t pcsr_int : 1; /**< BIST Status for PKT OUTB Interrupt MEM */
1399 uint64_t pcsr_im : 1; /**< BIST Status for PKT CSR Instr MEM */
1400 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT INB Count MEM */
1401 uint64_t pcsr_id : 1; /**< BIST Status for PKT INB Instr Done MEM */
1402 uint64_t pcsr_sl : 1; /**< BIST Status for PKT OUTB SLIST MEM */
1403 uint64_t pkt_imem : 1; /**< BIST Status for PKT OUTB IFIFO */
1404 uint64_t pkt_pfm : 1; /**< BIST Status for PKT Front MEM */
1405 uint64_t pkt_pof : 1; /**< BIST Status for PKT OUTB FIFO */
1406 uint64_t reserved_48_49 : 2;
1407 uint64_t pkt_pop0 : 1; /**< BIST Status for PKT OUTB Slist0 */
1408 uint64_t pkt_pop1 : 1; /**< BIST Status for PKT OUTB Slist1 */
1409 uint64_t d0_mem : 1; /**< BIST Status for DMA MEM 0 */
1410 uint64_t d1_mem : 1; /**< BIST Status for DMA MEM 1 */
1411 uint64_t d2_mem : 1; /**< BIST Status for DMA MEM 2 */
1412 uint64_t d3_mem : 1; /**< BIST Status for DMA MEM 3 */
1413 uint64_t d4_mem : 1; /**< BIST Status for DMA MEM 4 */
1414 uint64_t ds_mem : 1; /**< BIST Status for DMA Memory */
1415 uint64_t reserved_36_39 : 4;
1416 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1417 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1418 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1419 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1420 uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */
1421 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1422 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1423 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1424 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1425 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1426 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1427 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1428 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1429 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1430 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1431 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1432 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1433 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1434 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1435 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1436 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1437 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1438 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1439 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1440 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1441 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1442 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1443 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1444 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1445 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1446 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1447 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1448 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1449 uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */
1450 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1451 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1453 uint64_t ncb_cmd : 1;
1454 uint64_t msi : 1;
1455 uint64_t dif4 : 1;
1456 uint64_t dif3 : 1;
1457 uint64_t dif2 : 1;
1458 uint64_t dif1 : 1;
1459 uint64_t dif0 : 1;
1460 uint64_t csm1 : 1;
1461 uint64_t csm0 : 1;
1462 uint64_t p2n1_p1 : 1;
1463 uint64_t p2n1_p0 : 1;
1464 uint64_t p2n1_n : 1;
1465 uint64_t p2n1_c1 : 1;
1466 uint64_t p2n1_c0 : 1;
1467 uint64_t p2n0_p1 : 1;
1468 uint64_t p2n0_p0 : 1;
1469 uint64_t p2n0_n : 1;
1470 uint64_t p2n0_c1 : 1;
1471 uint64_t p2n0_c0 : 1;
1472 uint64_t p2n0_co : 1;
1473 uint64_t p2n0_no : 1;
1474 uint64_t p2n0_po : 1;
1475 uint64_t p2n1_co : 1;
1476 uint64_t p2n1_no : 1;
1477 uint64_t p2n1_po : 1;
1478 uint64_t cpl_p1 : 1;
1479 uint64_t cpl_p0 : 1;
1480 uint64_t n2p1_o : 1;
1481 uint64_t n2p1_c : 1;
1482 uint64_t n2p0_o : 1;
1483 uint64_t n2p0_c : 1;
1484 uint64_t d4_pst : 1;
1485 uint64_t d3_pst : 1;
1486 uint64_t d2_pst : 1;
1487 uint64_t d1_pst : 1;
1488 uint64_t d0_pst : 1;
1489 uint64_t reserved_36_39 : 4;
1490 uint64_t ds_mem : 1;
1491 uint64_t d4_mem : 1;
1492 uint64_t d3_mem : 1;
1493 uint64_t d2_mem : 1;
1494 uint64_t d1_mem : 1;
1495 uint64_t d0_mem : 1;
1496 uint64_t pkt_pop1 : 1;
1497 uint64_t pkt_pop0 : 1;
1498 uint64_t reserved_48_49 : 2;
1499 uint64_t pkt_pof : 1;
1500 uint64_t pkt_pfm : 1;
1501 uint64_t pkt_imem : 1;
1502 uint64_t pcsr_sl : 1;
1503 uint64_t pcsr_id : 1;
1504 uint64_t pcsr_cnt : 1;
1505 uint64_t pcsr_im : 1;
1506 uint64_t pcsr_int : 1;
1507 uint64_t pkt_pif : 1;
1508 uint64_t pcr_gim : 1;
1509 uint64_t reserved_60_62 : 3;
1510 uint64_t pkt_rdf : 1;
1515 uint64_t reserved_46_63 : 18;
1516 uint64_t d0_mem0 : 1; /**< BIST Status for DMA0 Memory */
1517 uint64_t d1_mem1 : 1; /**< BIST Status for DMA1 Memory */
1518 uint64_t d2_mem2 : 1; /**< BIST Status for DMA2 Memory */
1519 uint64_t d3_mem3 : 1; /**< BIST Status for DMA3 Memory */
1520 uint64_t dr0_mem : 1; /**< BIST Status for DMA0 Store */
1521 uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */
1522 uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */
1523 uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */
1524 uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */
1525 uint64_t dr1_mem : 1; /**< BIST Status for DMA1 Store */
1526 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1527 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1528 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1529 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1530 uint64_t dr2_mem : 1; /**< BIST Status for DMA2 Store */
1531 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1532 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1533 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1534 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1535 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1536 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1537 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1538 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1539 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1540 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1541 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1542 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1543 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1544 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1545 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1546 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1547 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1548 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1549 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1550 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1551 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1552 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1553 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1554 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1555 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1556 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1557 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1558 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1559 uint64_t dr3_mem : 1; /**< BIST Status for DMA3 Store */
1560 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1561 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1563 uint64_t ncb_cmd : 1;
1564 uint64_t msi : 1;
1565 uint64_t dr3_mem : 1;
1566 uint64_t dif3 : 1;
1567 uint64_t dif2 : 1;
1568 uint64_t dif1 : 1;
1569 uint64_t dif0 : 1;
1570 uint64_t csm1 : 1;
1571 uint64_t csm0 : 1;
1572 uint64_t p2n1_p1 : 1;
1573 uint64_t p2n1_p0 : 1;
1574 uint64_t p2n1_n : 1;
1575 uint64_t p2n1_c1 : 1;
1576 uint64_t p2n1_c0 : 1;
1577 uint64_t p2n0_p1 : 1;
1578 uint64_t p2n0_p0 : 1;
1579 uint64_t p2n0_n : 1;
1580 uint64_t p2n0_c1 : 1;
1581 uint64_t p2n0_c0 : 1;
1582 uint64_t p2n0_co : 1;
1583 uint64_t p2n0_no : 1;
1584 uint64_t p2n0_po : 1;
1585 uint64_t p2n1_co : 1;
1586 uint64_t p2n1_no : 1;
1587 uint64_t p2n1_po : 1;
1588 uint64_t cpl_p1 : 1;
1589 uint64_t cpl_p0 : 1;
1590 uint64_t n2p1_o : 1;
1591 uint64_t n2p1_c : 1;
1592 uint64_t n2p0_o : 1;
1593 uint64_t n2p0_c : 1;
1594 uint64_t dr2_mem : 1;
1595 uint64_t d3_pst : 1;
1596 uint64_t d2_pst : 1;
1597 uint64_t d1_pst : 1;
1598 uint64_t d0_pst : 1;
1599 uint64_t dr1_mem : 1;
1600 uint64_t d3_mem : 1;
1601 uint64_t d2_mem : 1;
1602 uint64_t d1_mem : 1;
1603 uint64_t d0_mem : 1;
1604 uint64_t dr0_mem : 1;
1605 uint64_t d3_mem3 : 1;
1606 uint64_t d2_mem2 : 1;
1607 uint64_t d1_mem1 : 1;
1608 uint64_t d0_mem0 : 1;
1609 uint64_t reserved_46_63 : 18;
1615 uint64_t reserved_58_63 : 6;
1616 uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */
1617 uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */
1618 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */
1619 uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */
1620 uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */
1621 uint64_t pkt_pout : 1; /**< BIST Status for PKT OUT Count MEM */
1622 uint64_t pkt_imem : 1; /**< BIST Status for PKT Instruction MEM */
1623 uint64_t pkt_cntm : 1; /**< BIST Status for PKT Count MEM */
1624 uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */
1625 uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */
1626 uint64_t pkt_odf : 1; /**< BIST Status for PKT Output Data FIFO */
1627 uint64_t pkt_oif : 1; /**< BIST Status for PKT Output INFO FIFO */
1628 uint64_t pkt_out : 1; /**< BIST Status for PKT Output FIFO */
1629 uint64_t pkt_i0 : 1; /**< BIST Status for PKT Instr0 */
1630 uint64_t pkt_i1 : 1; /**< BIST Status for PKT Instr1 */
1631 uint64_t pkt_s0 : 1; /**< BIST Status for PKT Slist0 */
1632 uint64_t pkt_s1 : 1; /**< BIST Status for PKT Slist1 */
1633 uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */
1634 uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */
1635 uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */
1636 uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */
1637 uint64_t d4_mem : 1; /**< BIST Status for DMA4 Memory */
1638 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1639 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1640 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1641 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1642 uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */
1643 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1644 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1645 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1646 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1647 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1648 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1649 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1650 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1651 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1652 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1653 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1654 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1655 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1656 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1657 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1658 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1659 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1660 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1661 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1662 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1663 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1664 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1665 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1666 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1667 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1668 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1669 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1670 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1671 uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */
1672 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1673 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1675 uint64_t ncb_cmd : 1;
1676 uint64_t msi : 1;
1677 uint64_t dif4 : 1;
1678 uint64_t dif3 : 1;
1679 uint64_t dif2 : 1;
1680 uint64_t dif1 : 1;
1681 uint64_t dif0 : 1;
1682 uint64_t csm1 : 1;
1683 uint64_t csm0 : 1;
1684 uint64_t p2n1_p1 : 1;
1685 uint64_t p2n1_p0 : 1;
1686 uint64_t p2n1_n : 1;
1687 uint64_t p2n1_c1 : 1;
1688 uint64_t p2n1_c0 : 1;
1689 uint64_t p2n0_p1 : 1;
1690 uint64_t p2n0_p0 : 1;
1691 uint64_t p2n0_n : 1;
1692 uint64_t p2n0_c1 : 1;
1693 uint64_t p2n0_c0 : 1;
1694 uint64_t p2n0_co : 1;
1695 uint64_t p2n0_no : 1;
1696 uint64_t p2n0_po : 1;
1697 uint64_t p2n1_co : 1;
1698 uint64_t p2n1_no : 1;
1699 uint64_t p2n1_po : 1;
1700 uint64_t cpl_p1 : 1;
1701 uint64_t cpl_p0 : 1;
1702 uint64_t n2p1_o : 1;
1703 uint64_t n2p1_c : 1;
1704 uint64_t n2p0_o : 1;
1705 uint64_t n2p0_c : 1;
1706 uint64_t d4_pst : 1;
1707 uint64_t d3_pst : 1;
1708 uint64_t d2_pst : 1;
1709 uint64_t d1_pst : 1;
1710 uint64_t d0_pst : 1;
1711 uint64_t d4_mem : 1;
1712 uint64_t d3_mem : 1;
1713 uint64_t d2_mem : 1;
1714 uint64_t d1_mem : 1;
1715 uint64_t d0_mem : 1;
1716 uint64_t pkt_s1 : 1;
1717 uint64_t pkt_s0 : 1;
1718 uint64_t pkt_i1 : 1;
1719 uint64_t pkt_i0 : 1;
1720 uint64_t pkt_out : 1;
1721 uint64_t pkt_oif : 1;
1722 uint64_t pkt_odf : 1;
1723 uint64_t pkt_slm : 1;
1724 uint64_t pkt_ind : 1;
1725 uint64_t pkt_cntm : 1;
1726 uint64_t pkt_imem : 1;
1727 uint64_t pkt_pout : 1;
1728 uint64_t pcsr_sl : 1;
1729 uint64_t pcsr_id : 1;
1730 uint64_t pcsr_cnt : 1;
1731 uint64_t pcsr_im : 1;
1732 uint64_t pcsr_int : 1;
1733 uint64_t reserved_58_63 : 6;
1747 uint64_t u64;
1750 uint64_t reserved_14_63 : 50;
1751 uint64_t prd_tag : 1; /**< BIST Status for DMA PCIE RD Tag MEM */
1752 uint64_t prd_st0 : 1; /**< BIST Status for DMA PCIE RD state MEM 0 */
1753 uint64_t prd_st1 : 1; /**< BIST Status for DMA PCIE RD state MEM 1 */
1754 uint64_t prd_err : 1; /**< BIST Status for DMA PCIE RD ERR state MEM */
1755 uint64_t nrd_st : 1; /**< BIST Status for DMA L2C RD state MEM */
1756 uint64_t nwe_st : 1; /**< BIST Status for DMA L2C WR state MEM */
1757 uint64_t nwe_wr0 : 1; /**< BIST Status for DMA L2C WR MEM 0 */
1758 uint64_t nwe_wr1 : 1; /**< BIST Status for DMA L2C WR MEM 1 */
1759 uint64_t pkt_rd : 1; /**< BIST Status for Inbound PKT MEM */
1760 uint64_t psc_p0 : 1; /**< BIST Status for PSC TLP 0 MEM */
1761 uint64_t psc_p1 : 1; /**< BIST Status for PSC TLP 1 MEM */
1762 uint64_t pkt_gd : 1; /**< BIST Status for PKT OUTB Gather Data FIFO */
1763 uint64_t pkt_gl : 1; /**< BIST Status for PKT_OUTB Gather List FIFO */
1764 uint64_t pkt_blk : 1; /**< BIST Status for PKT OUTB Blocked FIFO */
1766 uint64_t pkt_blk : 1;
1767 uint64_t pkt_gl : 1;
1768 uint64_t pkt_gd : 1;
1769 uint64_t psc_p1 : 1;
1770 uint64_t psc_p0 : 1;
1771 uint64_t pkt_rd : 1;
1772 uint64_t nwe_wr1 : 1;
1773 uint64_t nwe_wr0 : 1;
1774 uint64_t nwe_st : 1;
1775 uint64_t nrd_st : 1;
1776 uint64_t prd_err : 1;
1777 uint64_t prd_st1 : 1;
1778 uint64_t prd_st0 : 1;
1779 uint64_t prd_tag : 1;
1780 uint64_t reserved_14_63 : 50;
1796 uint64_t u64;
1799 uint64_t reserved_21_63 : 43;
1800 uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit
1806 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */
1807 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */
1808 uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */
1809 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */
1810 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
1812 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
1814 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
1816 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
1818 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */
1819 uint64_t reserved_6_6 : 1;
1820 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */
1821 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when
1823 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to
1825 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to
1828 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1835 uint64_t wait_com : 1;
1836 uint64_t bar2_cax : 1;
1837 uint64_t bar2_esx : 2;
1838 uint64_t bar2_enb : 1;
1839 uint64_t ptlp_ro : 1;
1840 uint64_t reserved_6_6 : 1;
1841 uint64_t ctlp_ro : 1;
1842 uint64_t inta_map : 2;
1843 uint64_t intb_map : 2;
1844 uint64_t intc_map : 2;
1845 uint64_t intd_map : 2;
1846 uint64_t inta : 1;
1847 uint64_t intb : 1;
1848 uint64_t intc : 1;
1849 uint64_t intd : 1;
1850 uint64_t waitl_com : 1;
1851 uint64_t reserved_21_63 : 43;
1869 uint64_t u64;
1872 uint64_t reserved_21_63 : 43;
1873 uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit
1878 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */
1879 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */
1880 uint64_t intb : 1; /**< When '0' Intv wire asserted. Before mapping. */
1881 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */
1882 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
1884 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
1886 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
1888 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
1890 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */
1891 uint64_t reserved_6_6 : 1;
1892 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */
1893 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when
1895 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to
1897 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to
1900 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1907 uint64_t wait_com : 1;
1908 uint64_t bar2_cax : 1;
1909 uint64_t bar2_esx : 2;
1910 uint64_t bar2_enb : 1;
1911 uint64_t ptlp_ro : 1;
1912 uint64_t reserved_6_6 : 1;
1913 uint64_t ctlp_ro : 1;
1914 uint64_t inta_map : 2;
1915 uint64_t intb_map : 2;
1916 uint64_t intc_map : 2;
1917 uint64_t intd_map : 2;
1918 uint64_t inta : 1;
1919 uint64_t intb : 1;
1920 uint64_t intc : 1;
1921 uint64_t intd : 1;
1922 uint64_t waitl_com : 1;
1923 uint64_t reserved_21_63 : 43;
1943 uint64_t u64;
1946 uint64_t reserved_44_63 : 20;
1947 uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1.
1955 uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0.
1963 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a
1969 uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received
1975 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to
1980 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority
1982 uint64_t pkt_bp : 4; /**< Unused */
1983 uint64_t host_mode : 1; /**< Host mode */
1984 uint64_t chip_rev : 8; /**< The chip revision. */
1986 uint64_t chip_rev : 8;
1987 uint64_t host_mode : 1;
1988 uint64_t pkt_bp : 4;
1989 uint64_t arb : 1;
1990 uint64_t lnk_rst : 1;
1991 uint64_t ring_en : 1;
1992 uint64_t cfg_rtry : 16;
1993 uint64_t p0_ntags : 6;
1994 uint64_t p1_ntags : 6;
1995 uint64_t reserved_44_63 : 20;
2001 uint64_t reserved_44_63 : 20;
2002 uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1.
2010 uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0.
2018 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a
2024 uint64_t reserved_15_15 : 1;
2025 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to
2030 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority
2032 uint64_t reserved_9_12 : 4;
2033 uint64_t host_mode : 1; /**< Host mode */
2034 uint64_t chip_rev : 8; /**< The chip revision. */
2036 uint64_t chip_rev : 8;
2037 uint64_t host_mode : 1;
2038 uint64_t reserved_9_12 : 4;
2039 uint64_t arb : 1;
2040 uint64_t lnk_rst : 1;
2041 uint64_t reserved_15_15 : 1;
2042 uint64_t cfg_rtry : 16;
2043 uint64_t p0_ntags : 6;
2044 uint64_t p1_ntags : 6;
2045 uint64_t reserved_44_63 : 20;
2051 uint64_t reserved_15_63 : 49;
2052 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to
2057 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority
2059 uint64_t pkt_bp : 4; /**< Unused */
2060 uint64_t host_mode : 1; /**< Host mode */
2061 uint64_t chip_rev : 8; /**< The chip revision. */
2063 uint64_t chip_rev : 8;
2064 uint64_t host_mode : 1;
2065 uint64_t pkt_bp : 4;
2066 uint64_t arb : 1;
2067 uint64_t lnk_rst : 1;
2068 uint64_t reserved_15_63 : 49;
2085 uint64_t u64;
2088 uint64_t reserved_16_63 : 48;
2089 uint64_t mps : 1; /**< Max Payload Size
2094 uint64_t mrrs : 3; /**< Max Read Request Size
2104 uint64_t c1_w_flt : 1; /**< When '1' enables the window filter for reads and
2126 uint64_t c0_w_flt : 1; /**< When '1' enables the window filter for reads and
2148 uint64_t c1_b1_s : 3; /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB,
2151 uint64_t c0_b1_s : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
2154 uint64_t c1_wi_d : 1; /**< When set '1' disables access to the Window
2156 uint64_t c1_b0_d : 1; /**< When set '1' disables access from PCIe-Port1 to
2160 uint64_t c0_wi_d : 1; /**< When set '1' disables access to the Window
2162 uint64_t c0_b0_d : 1; /**< When set '1' disables access from PCIe-Port0 to
2167 uint64_t c0_b0_d : 1;
2168 uint64_t c0_wi_d : 1;
2169 uint64_t c1_b0_d : 1;
2170 uint64_t c1_wi_d : 1;
2171 uint64_t c0_b1_s : 3;
2172 uint64_t c1_b1_s : 3;
2173 uint64_t c0_w_flt : 1;
2174 uint64_t c1_w_flt : 1;
2175 uint64_t mrrs : 3;
2176 uint64_t mps : 1;
2177 uint64_t reserved_16_63 : 48;
2195 uint64_t u64;
2198 uint64_t reserved_44_63 : 20;
2199 uint64_t p1_ucnt : 16; /**< PCIE-Port1 Fifo Unload Count. This counter is
2203 uint64_t p1_fcnt : 6; /**< PCIE-Port1 Data Out Fifo Count. Number of address
2206 uint64_t p0_ucnt : 16; /**< PCIE-Port0 Fifo Unload Count. This counter is
2210 uint64_t p0_fcnt : 6; /**< PCIE-Port0 Data Out Fifo Count. Number of address
2214 uint64_t p0_fcnt : 6;
2215 uint64_t p0_ucnt : 16;
2216 uint64_t p1_fcnt : 6;
2217 uint64_t p1_ucnt : 16;
2218 uint64_t reserved_44_63 : 20;
2236 uint64_t u64;
2239 uint64_t reserved_28_63 : 36;
2240 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */
2241 uint64_t reserved_25_26 : 2;
2242 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency
2247 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion
2249 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
2251 uint64_t data : 17; /**< Value on the debug data lines. */
2253 uint64_t data : 17;
2254 uint64_t dsel_ext : 1;
2255 uint64_t c_mul : 5;
2256 uint64_t qlm1_spd : 2;
2257 uint64_t reserved_25_26 : 2;
2258 uint64_t qlm0_rev_lanes : 1;
2259 uint64_t reserved_28_63 : 36;
2264 uint64_t reserved_29_63 : 35;
2265 uint64_t qlm0_link_width : 1; /**< Link width of PCIe port 0
2270 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */
2271 uint64_t qlm1_mode : 2; /**< Sets the QLM1 Mode
2276 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency
2281 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion
2283 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
2285 uint64_t data : 17; /**< Value on the debug data lines. */
2287 uint64_t data : 17;
2288 uint64_t dsel_ext : 1;
2289 uint64_t c_mul : 5;
2290 uint64_t qlm1_spd : 2;
2291 uint64_t qlm1_mode : 2;
2292 uint64_t qlm0_rev_lanes : 1;
2293 uint64_t qlm0_link_width : 1;
2294 uint64_t reserved_29_63 : 35;
2300 uint64_t reserved_29_63 : 35;
2301 uint64_t qlm2_rev_lanes : 1; /**< Lane reversal for PCIe port 1 */
2302 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */
2303 uint64_t qlm3_spd : 2; /**< Sets the QLM3 frequency
2308 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency
2313 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion
2315 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
2317 uint64_t data : 17; /**< Value on the debug data lines. */
2319 uint64_t data : 17;
2320 uint64_t dsel_ext : 1;
2321 uint64_t c_mul : 5;
2322 uint64_t qlm1_spd : 2;
2323 uint64_t qlm3_spd : 2;
2324 uint64_t qlm0_rev_lanes : 1;
2325 uint64_t qlm2_rev_lanes : 1;
2326 uint64_t reserved_29_63 : 35;
2341 uint64_t u64;
2344 uint64_t reserved_16_63 : 48;
2345 uint64_t dbg_sel : 16; /**< When this register is written its value is sent to
2348 uint64_t dbg_sel : 16;
2349 uint64_t reserved_16_63 : 48;
2367 uint64_t u64;
2370 uint64_t reserved_39_63 : 25;
2371 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */
2372 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */
2374 uint64_t dbell : 32;
2375 uint64_t fcnt : 7;
2376 uint64_t reserved_39_63 : 25;
2421 uint64_t u64;
2424 uint64_t reserved_37_63 : 27;
2425 uint64_t idle : 1; /**< DMA Engine IDLE state */
2426 uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the
2429 uint64_t reserved_0_6 : 7;
2431 uint64_t reserved_0_6 : 7;
2432 uint64_t saddr : 29;
2433 uint64_t idle : 1;
2434 uint64_t reserved_37_63 : 27;
2440 uint64_t reserved_36_63 : 28;
2441 uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the
2444 uint64_t reserved_0_6 : 7;
2446 uint64_t reserved_0_6 : 7;
2447 uint64_t saddr : 29;
2448 uint64_t reserved_36_63 : 28;
2464 uint64_t u64;
2467 uint64_t reserved_36_63 : 28;
2468 uint64_t addr : 36; /**< The next L2C address to read DMA# instructions
2471 uint64_t addr : 36;
2472 uint64_t reserved_36_63 : 28;
2490 uint64_t u64;
2493 uint64_t time : 32; /**< Whenever the DMA_CNT0 timer exceeds
2498 uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value,
2501 uint64_t cnt : 32;
2502 uint64_t time : 32;
2520 uint64_t u64;
2523 uint64_t time : 32; /**< Whenever the DMA_CNT1 timer exceeds
2528 uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value,
2531 uint64_t cnt : 32;
2532 uint64_t time : 32;
2550 uint64_t u64;
2553 uint64_t dma1 : 32; /**< The DMA counter 1.
2563 uint64_t dma0 : 32; /**< The DMA counter 0.
2574 uint64_t dma0 : 32;
2575 uint64_t dma1 : 32;
2593 uint64_t u64;
2596 uint64_t reserved_40_63 : 24;
2597 uint64_t p_32b_m : 1; /**< DMA PCIE 32-bit word read disable bit
2599 uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2602 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2605 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2608 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2611 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2614 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write
2618 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB
2621 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
2624 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
2626 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
2629 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
2630 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
2631 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
2632 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
2637 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
2643 uint64_t csize : 14;
2644 uint64_t o_mode : 1;
2645 uint64_t o_es : 2;
2646 uint64_t o_ns : 1;
2647 uint64_t o_ro : 1;
2648 uint64_t o_add1 : 1;
2649 uint64_t fpa_que : 3;
2650 uint64_t dwb_ichk : 9;
2651 uint64_t dwb_denb : 1;
2652 uint64_t b0_lend : 1;
2653 uint64_t dma0_enb : 1;
2654 uint64_t dma1_enb : 1;
2655 uint64_t dma2_enb : 1;
2656 uint64_t dma3_enb : 1;
2657 uint64_t dma4_enb : 1;
2658 uint64_t p_32b_m : 1;
2659 uint64_t reserved_40_63 : 24;
2665 uint64_t reserved_38_63 : 26;
2666 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2669 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2672 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2675 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2678 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write
2682 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB
2685 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
2688 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
2690 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
2693 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
2694 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
2695 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
2696 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
2701 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
2707 uint64_t csize : 14;
2708 uint64_t o_mode : 1;
2709 uint64_t o_es : 2;
2710 uint64_t o_ns : 1;
2711 uint64_t o_ro : 1;
2712 uint64_t o_add1 : 1;
2713 uint64_t fpa_que : 3;
2714 uint64_t dwb_ichk : 9;
2715 uint64_t dwb_denb : 1;
2716 uint64_t b0_lend : 1;
2717 uint64_t dma0_enb : 1;
2718 uint64_t dma1_enb : 1;
2719 uint64_t dma2_enb : 1;
2720 uint64_t dma3_enb : 1;
2721 uint64_t reserved_38_63 : 26;
2727 uint64_t reserved_39_63 : 25;
2728 uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2731 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2734 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2737 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2740 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2743 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write
2747 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB
2750 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
2753 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
2755 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
2758 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
2759 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
2760 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
2761 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
2766 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
2772 uint64_t csize : 14;
2773 uint64_t o_mode : 1;
2774 uint64_t o_es : 2;
2775 uint64_t o_ns : 1;
2776 uint64_t o_ro : 1;
2777 uint64_t o_add1 : 1;
2778 uint64_t fpa_que : 3;
2779 uint64_t dwb_ichk : 9;
2780 uint64_t dwb_denb : 1;
2781 uint64_t b0_lend : 1;
2782 uint64_t dma0_enb : 1;
2783 uint64_t dma1_enb : 1;
2784 uint64_t dma2_enb : 1;
2785 uint64_t dma3_enb : 1;
2786 uint64_t dma4_enb : 1;
2787 uint64_t reserved_39_63 : 25;
2801 uint64_t u64;
2804 uint64_t dma_arb : 1; /**< DMA_PKT Read Request Arbitration
2810 uint64_t reserved_53_62 : 10;
2811 uint64_t pkt_cnt : 5; /**< PKT outstanding PCIE Read Request Number for each
2817 uint64_t reserved_45_47 : 3;
2818 uint64_t dma4_cnt : 5; /**< DMA4 outstanding PCIE Read Request Number
2823 uint64_t reserved_37_39 : 3;
2824 uint64_t dma3_cnt : 5; /**< DMA3 outstanding PCIE Read Request Number
2829 uint64_t reserved_29_31 : 3;
2830 uint64_t dma2_cnt : 5; /**< DMA2 outstanding PCIE Read Request Number
2835 uint64_t reserved_21_23 : 3;
2836 uint64_t dma1_cnt : 5; /**< DMA1 outstanding PCIE Read Request Number
2841 uint64_t reserved_13_15 : 3;
2842 uint64_t dma0_cnt : 5; /**< DMA0 outstanding PCIE Read Request Number
2847 uint64_t reserved_5_7 : 3;
2848 uint64_t dma_cnt : 5; /**< Total outstanding PCIE Read Request Number for each
2856 uint64_t dma_cnt : 5;
2857 uint64_t reserved_5_7 : 3;
2858 uint64_t dma0_cnt : 5;
2859 uint64_t reserved_13_15 : 3;
2860 uint64_t dma1_cnt : 5;
2861 uint64_t reserved_21_23 : 3;
2862 uint64_t dma2_cnt : 5;
2863 uint64_t reserved_29_31 : 3;
2864 uint64_t dma3_cnt : 5;
2865 uint64_t reserved_37_39 : 3;
2866 uint64_t dma4_cnt : 5;
2867 uint64_t reserved_45_47 : 3;
2868 uint64_t pkt_cnt : 5;
2869 uint64_t reserved_53_62 : 10;
2870 uint64_t dma_arb : 1;
2886 uint64_t u64;
2889 uint64_t reserved_40_63 : 24;
2890 uint64_t d4_dwe : 8; /**< DMA4 PICe Write State */
2891 uint64_t d3_dwe : 8; /**< DMA3 PICe Write State */
2892 uint64_t d2_dwe : 8; /**< DMA2 PICe Write State */
2893 uint64_t d1_dwe : 8; /**< DMA1 PICe Write State */
2894 uint64_t d0_dwe : 8; /**< DMA0 PICe Write State */
2896 uint64_t d0_dwe : 8;
2897 uint64_t d1_dwe : 8;
2898 uint64_t d2_dwe : 8;
2899 uint64_t d3_dwe : 8;
2900 uint64_t d4_dwe : 8;
2901 uint64_t reserved_40_63 : 24;
2916 uint64_t u64;
2919 uint64_t reserved_60_63 : 4;
2920 uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */
2921 uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */
2922 uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */
2923 uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */
2924 uint64_t d4_difst : 7; /**< DMA engine 4 dif instruction read state */
2925 uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */
2926 uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */
2927 uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */
2928 uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */
2929 uint64_t d4_reqst : 5; /**< DMA engine 4 request data state */
2931 uint64_t d4_reqst : 5;
2932 uint64_t d3_reqst : 5;
2933 uint64_t d2_reqst : 5;
2934 uint64_t d1_reqst : 5;
2935 uint64_t d0_reqst : 5;
2936 uint64_t d4_difst : 7;
2937 uint64_t d3_difst : 7;
2938 uint64_t d2_difst : 7;
2939 uint64_t d1_difst : 7;
2940 uint64_t d0_difst : 7;
2941 uint64_t reserved_60_63 : 4;
2946 uint64_t reserved_60_63 : 4;
2947 uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */
2948 uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */
2949 uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */
2950 uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */
2951 uint64_t reserved_25_31 : 7;
2952 uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */
2953 uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */
2954 uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */
2955 uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */
2956 uint64_t reserved_0_4 : 5;
2958 uint64_t reserved_0_4 : 5;
2959 uint64_t d3_reqst : 5;
2960 uint64_t d2_reqst : 5;
2961 uint64_t d1_reqst : 5;
2962 uint64_t d0_reqst : 5;
2963 uint64_t reserved_25_31 : 7;
2964 uint64_t d3_difst : 7;
2965 uint64_t d2_difst : 7;
2966 uint64_t d1_difst : 7;
2967 uint64_t d0_difst : 7;
2968 uint64_t reserved_60_63 : 4;
2983 uint64_t u64;
2986 uint64_t reserved_28_63 : 36;
2987 uint64_t ndwe : 4; /**< DMA L2C Write State */
2988 uint64_t reserved_21_23 : 3;
2989 uint64_t ndre : 5; /**< DMA L2C Read State */
2990 uint64_t reserved_10_15 : 6;
2991 uint64_t prd : 10; /**< DMA PICe Read State */
2993 uint64_t prd : 10;
2994 uint64_t reserved_10_15 : 6;
2995 uint64_t ndre : 5;
2996 uint64_t reserved_21_23 : 3;
2997 uint64_t ndwe : 4;
2998 uint64_t reserved_28_63 : 36;
3013 uint64_t u64;
3016 uint64_t reserved_45_63 : 19;
3017 uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */
3018 uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */
3019 uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */
3020 uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */
3021 uint64_t d4_dffst : 9; /**< DMA engine 4 dif instruction fetch state */
3023 uint64_t d4_dffst : 9;
3024 uint64_t d3_dffst : 9;
3025 uint64_t d2_dffst : 9;
3026 uint64_t d1_dffst : 9;
3027 uint64_t d0_dffst : 9;
3028 uint64_t reserved_45_63 : 19;
3033 uint64_t reserved_45_63 : 19;
3034 uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */
3035 uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */
3036 uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */
3037 uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */
3038 uint64_t reserved_0_8 : 9;
3040 uint64_t reserved_0_8 : 9;
3041 uint64_t d3_dffst : 9;
3042 uint64_t d2_dffst : 9;
3043 uint64_t d1_dffst : 9;
3044 uint64_t d0_dffst : 9;
3045 uint64_t reserved_45_63 : 19;
3060 uint64_t u64;
3063 uint64_t reserved_60_63 : 4;
3064 uint64_t d0_drest : 15; /**< DMA engine 0 dre state */
3065 uint64_t d1_drest : 15; /**< DMA engine 1 dre state */
3066 uint64_t d2_drest : 15; /**< DMA engine 2 dre state */
3067 uint64_t d3_drest : 15; /**< DMA engine 3 dre state */
3069 uint64_t d3_drest : 15;
3070 uint64_t d2_drest : 15;
3071 uint64_t d1_drest : 15;
3072 uint64_t d0_drest : 15;
3073 uint64_t reserved_60_63 : 4;
3089 uint64_t u64;
3092 uint64_t reserved_52_63 : 12;
3093 uint64_t d0_dwest : 13; /**< DMA engine 0 dwe state */
3094 uint64_t d1_dwest : 13; /**< DMA engine 1 dwe state */
3095 uint64_t d2_dwest : 13; /**< DMA engine 2 dwe state */
3096 uint64_t d3_dwest : 13; /**< DMA engine 3 dwe state */
3098 uint64_t d3_dwest : 13;
3099 uint64_t d2_dwest : 13;
3100 uint64_t d1_dwest : 13;
3101 uint64_t d0_dwest : 13;
3102 uint64_t reserved_52_63 : 12;
3118 uint64_t u64;
3121 uint64_t reserved_28_63 : 36;
3122 uint64_t d4_drest : 15; /**< DMA engine 4 dre state */
3123 uint64_t d4_dwest : 13; /**< DMA engine 4 dwe state */
3125 uint64_t d4_dwest : 13;
3126 uint64_t d4_drest : 15;
3127 uint64_t reserved_28_63 : 36;
3142 uint64_t u64;
3145 uint64_t reserved_10_63 : 54;
3146 uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an
3148 uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an
3150 uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an
3152 uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an
3154 uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an
3156 uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an
3158 uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an
3160 uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an
3162 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3164 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3167 uint64_t dma0_cpl : 1;
3168 uint64_t dma1_cpl : 1;
3169 uint64_t pins_err : 1;
3170 uint64_t pop_err : 1;
3171 uint64_t pdi_err : 1;
3172 uint64_t pgl_err : 1;
3173 uint64_t p0_rdlk : 1;
3174 uint64_t p1_rdlk : 1;
3175 uint64_t pin_bp : 1;
3176 uint64_t pout_err : 1;
3177 uint64_t reserved_10_63 : 54;
3183 uint64_t reserved_2_63 : 62;
3184 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3186 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3189 uint64_t dma0_cpl : 1;
3190 uint64_t dma1_cpl : 1;
3191 uint64_t reserved_2_63 : 62;
3206 uint64_t u64;
3209 uint64_t reserved_10_63 : 54;
3210 uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an
3212 uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an
3214 uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an
3216 uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an
3218 uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an
3220 uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an
3222 uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an
3224 uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an
3226 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3228 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3231 uint64_t dma0_cpl : 1;
3232 uint64_t dma1_cpl : 1;
3233 uint64_t pins_err : 1;
3234 uint64_t pop_err : 1;
3235 uint64_t pdi_err : 1;
3236 uint64_t pgl_err : 1;
3237 uint64_t p0_rdlk : 1;
3238 uint64_t p1_rdlk : 1;
3239 uint64_t pin_bp : 1;
3240 uint64_t pout_err : 1;
3241 uint64_t reserved_10_63 : 54;
3247 uint64_t reserved_2_63 : 62;
3248 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3250 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3253 uint64_t dma0_cpl : 1;
3254 uint64_t dma1_cpl : 1;
3255 uint64_t reserved_2_63 : 62;
3271 uint64_t u64;
3274 uint64_t reserved_10_63 : 54;
3275 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
3277 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK.
3279 uint64_t p1_rdlk : 1; /**< PCIe port 1 received a read lock. */
3280 uint64_t p0_rdlk : 1; /**< PCIe port 0 received a read lock. */
3281 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
3283 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
3285 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
3287 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
3289 uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3291 uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3294 uint64_t dma0_cpl : 1;
3295 uint64_t dma1_cpl : 1;
3296 uint64_t pins_err : 1;
3297 uint64_t pop_err : 1;
3298 uint64_t pdi_err : 1;
3299 uint64_t pgl_err : 1;
3300 uint64_t p0_rdlk : 1;
3301 uint64_t p1_rdlk : 1;
3302 uint64_t pin_bp : 1;
3303 uint64_t pout_err : 1;
3304 uint64_t reserved_10_63 : 54;
3310 uint64_t reserved_2_63 : 62;
3311 uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3313 uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3316 uint64_t dma0_cpl : 1;
3317 uint64_t dma1_cpl : 1;
3318 uint64_t reserved_2_63 : 62;
3333 uint64_t u64;
3336 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an
3338 uint64_t reserved_62_62 : 1;
3339 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an
3341 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3343 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3345 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3347 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3349 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3351 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3353 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3355 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3357 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3359 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3361 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3363 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3365 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3367 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3369 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3371 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3373 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3375 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3377 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3379 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3381 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3383 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3385 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3387 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3389 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3391 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3393 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3395 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3397 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3399 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3401 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3403 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an
3405 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3407 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an
3409 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
3411 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
3413 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
3415 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
3417 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an
3419 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
3421 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an
3423 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
3425 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
3427 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
3429 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
3431 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
3433 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
3435 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
3437 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
3439 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
3441 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
3443 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
3445 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
3447 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
3449 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
3451 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
3453 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
3455 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
3457 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
3459 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
3461 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an
3464 uint64_t rml_rto : 1;
3465 uint64_t rml_wto : 1;
3466 uint64_t bar0_to : 1;
3467 uint64_t iob2big : 1;
3468 uint64_t dma0dbo : 1;
3469 uint64_t dma1dbo : 1;
3470 uint64_t dma2dbo : 1;
3471 uint64_t dma3dbo : 1;
3472 uint64_t dma4dbo : 1;
3473 uint64_t dma0fi : 1;
3474 uint64_t dma1fi : 1;
3475 uint64_t dcnt0 : 1;
3476 uint64_t dcnt1 : 1;
3477 uint64_t dtime0 : 1;
3478 uint64_t dtime1 : 1;
3479 uint64_t psldbof : 1;
3480 uint64_t pidbof : 1;
3481 uint64_t pcnt : 1;
3482 uint64_t ptime : 1;
3483 uint64_t c0_aeri : 1;
3484 uint64_t crs0_er : 1;
3485 uint64_t c0_se : 1;
3486 uint64_t crs0_dr : 1;
3487 uint64_t c0_wake : 1;
3488 uint64_t c0_pmei : 1;
3489 uint64_t c0_hpint : 1;
3490 uint64_t c1_aeri : 1;
3491 uint64_t crs1_er : 1;
3492 uint64_t c1_se : 1;
3493 uint64_t crs1_dr : 1;
3494 uint64_t c1_wake : 1;
3495 uint64_t c1_pmei : 1;
3496 uint64_t c1_hpint : 1;
3497 uint64_t c0_up_b0 : 1;
3498 uint64_t c0_up_b1 : 1;
3499 uint64_t c0_up_b2 : 1;
3500 uint64_t c0_up_wi : 1;
3501 uint64_t c0_up_bx : 1;
3502 uint64_t c0_un_b0 : 1;
3503 uint64_t c0_un_b1 : 1;
3504 uint64_t c0_un_b2 : 1;
3505 uint64_t c0_un_wi : 1;
3506 uint64_t c0_un_bx : 1;
3507 uint64_t c1_up_b0 : 1;
3508 uint64_t c1_up_b1 : 1;
3509 uint64_t c1_up_b2 : 1;
3510 uint64_t c1_up_wi : 1;
3511 uint64_t c1_up_bx : 1;
3512 uint64_t c1_un_b0 : 1;
3513 uint64_t c1_un_b1 : 1;
3514 uint64_t c1_un_b2 : 1;
3515 uint64_t c1_un_wi : 1;
3516 uint64_t c1_un_bx : 1;
3517 uint64_t c0_un_wf : 1;
3518 uint64_t c1_un_wf : 1;
3519 uint64_t c0_up_wf : 1;
3520 uint64_t c1_up_wf : 1;
3521 uint64_t c0_exc : 1;
3522 uint64_t c1_exc : 1;
3523 uint64_t c0_ldwn : 1;
3524 uint64_t c1_ldwn : 1;
3525 uint64_t int_a : 1;
3526 uint64_t reserved_62_62 : 1;
3527 uint64_t mio_inta : 1;
3533 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an
3535 uint64_t reserved_62_62 : 1;
3536 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an
3538 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3540 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3542 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3544 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3546 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3548 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3550 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3552 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3554 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3556 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3558 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3560 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3562 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3564 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3566 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3568 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3570 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3572 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3574 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3576 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3578 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3580 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3582 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3584 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3586 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3588 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3590 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3592 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3594 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3596 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3598 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3600 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an
3602 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3604 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an
3606 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
3608 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
3610 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
3612 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
3614 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an
3616 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
3618 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an
3620 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
3622 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
3624 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
3626 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
3628 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
3630 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
3632 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
3634 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
3636 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
3638 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
3640 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
3642 uint64_t reserved_8_8 : 1;
3643 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
3645 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
3647 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
3649 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
3651 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
3653 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
3655 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
3657 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an
3660 uint64_t rml_rto : 1;
3661 uint64_t rml_wto : 1;
3662 uint64_t bar0_to : 1;
3663 uint64_t iob2big : 1;
3664 uint64_t dma0dbo : 1;
3665 uint64_t dma1dbo : 1;
3666 uint64_t dma2dbo : 1;
3667 uint64_t dma3dbo : 1;
3668 uint64_t reserved_8_8 : 1;
3669 uint64_t dma0fi : 1;
3670 uint64_t dma1fi : 1;
3671 uint64_t dcnt0 : 1;
3672 uint64_t dcnt1 : 1;
3673 uint64_t dtime0 : 1;
3674 uint64_t dtime1 : 1;
3675 uint64_t psldbof : 1;
3676 uint64_t pidbof : 1;
3677 uint64_t pcnt : 1;
3678 uint64_t ptime : 1;
3679 uint64_t c0_aeri : 1;
3680 uint64_t crs0_er : 1;
3681 uint64_t c0_se : 1;
3682 uint64_t crs0_dr : 1;
3683 uint64_t c0_wake : 1;
3684 uint64_t c0_pmei : 1;
3685 uint64_t c0_hpint : 1;
3686 uint64_t c1_aeri : 1;
3687 uint64_t crs1_er : 1;
3688 uint64_t c1_se : 1;
3689 uint64_t crs1_dr : 1;
3690 uint64_t c1_wake : 1;
3691 uint64_t c1_pmei : 1;
3692 uint64_t c1_hpint : 1;
3693 uint64_t c0_up_b0 : 1;
3694 uint64_t c0_up_b1 : 1;
3695 uint64_t c0_up_b2 : 1;
3696 uint64_t c0_up_wi : 1;
3697 uint64_t c0_up_bx : 1;
3698 uint64_t c0_un_b0 : 1;
3699 uint64_t c0_un_b1 : 1;
3700 uint64_t c0_un_b2 : 1;
3701 uint64_t c0_un_wi : 1;
3702 uint64_t c0_un_bx : 1;
3703 uint64_t c1_up_b0 : 1;
3704 uint64_t c1_up_b1 : 1;
3705 uint64_t c1_up_b2 : 1;
3706 uint64_t c1_up_wi : 1;
3707 uint64_t c1_up_bx : 1;
3708 uint64_t c1_un_b0 : 1;
3709 uint64_t c1_un_b1 : 1;
3710 uint64_t c1_un_b2 : 1;
3711 uint64_t c1_un_wi : 1;
3712 uint64_t c1_un_bx : 1;
3713 uint64_t c0_un_wf : 1;
3714 uint64_t c1_un_wf : 1;
3715 uint64_t c0_up_wf : 1;
3716 uint64_t c1_up_wf : 1;
3717 uint64_t c0_exc : 1;
3718 uint64_t c1_exc : 1;
3719 uint64_t c0_ldwn : 1;
3720 uint64_t c1_ldwn : 1;
3721 uint64_t int_a : 1;
3722 uint64_t reserved_62_62 : 1;
3723 uint64_t mio_inta : 1;
3729 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an
3731 uint64_t reserved_61_62 : 2;
3732 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3734 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3736 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3738 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3740 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3742 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3744 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3746 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3748 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3750 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3752 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3754 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3756 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3758 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3760 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3762 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3764 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3766 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3768 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3770 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3772 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3774 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3776 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3778 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3780 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3782 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3784 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3786 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3788 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3790 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3792 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3794 uint64_t reserved_29_29 : 1;
3795 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3797 uint64_t reserved_27_27 : 1;
3798 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
3800 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
3802 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
3804 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
3806 uint64_t reserved_22_22 : 1;
3807 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
3809 uint64_t reserved_20_20 : 1;
3810 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
3812 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
3814 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
3816 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
3818 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
3820 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
3822 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
3824 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
3826 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
3828 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
3830 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
3832 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
3834 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
3836 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
3838 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
3840 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
3842 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
3844 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
3846 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
3848 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an
3851 uint64_t rml_rto : 1;
3852 uint64_t rml_wto : 1;
3853 uint64_t bar0_to : 1;
3854 uint64_t iob2big : 1;
3855 uint64_t dma0dbo : 1;
3856 uint64_t dma1dbo : 1;
3857 uint64_t dma2dbo : 1;
3858 uint64_t dma3dbo : 1;
3859 uint64_t dma4dbo : 1;
3860 uint64_t dma0fi : 1;
3861 uint64_t dma1fi : 1;
3862 uint64_t dcnt0 : 1;
3863 uint64_t dcnt1 : 1;
3864 uint64_t dtime0 : 1;
3865 uint64_t dtime1 : 1;
3866 uint64_t psldbof : 1;
3867 uint64_t pidbof : 1;
3868 uint64_t pcnt : 1;
3869 uint64_t ptime : 1;
3870 uint64_t c0_aeri : 1;
3871 uint64_t reserved_20_20 : 1;
3872 uint64_t c0_se : 1;
3873 uint64_t reserved_22_22 : 1;
3874 uint64_t c0_wake : 1;
3875 uint64_t c0_pmei : 1;
3876 uint64_t c0_hpint : 1;
3877 uint64_t c1_aeri : 1;
3878 uint64_t reserved_27_27 : 1;
3879 uint64_t c1_se : 1;
3880 uint64_t reserved_29_29 : 1;
3881 uint64_t c1_wake : 1;
3882 uint64_t c1_pmei : 1;
3883 uint64_t c1_hpint : 1;
3884 uint64_t c0_up_b0 : 1;
3885 uint64_t c0_up_b1 : 1;
3886 uint64_t c0_up_b2 : 1;
3887 uint64_t c0_up_wi : 1;
3888 uint64_t c0_up_bx : 1;
3889 uint64_t c0_un_b0 : 1;
3890 uint64_t c0_un_b1 : 1;
3891 uint64_t c0_un_b2 : 1;
3892 uint64_t c0_un_wi : 1;
3893 uint64_t c0_un_bx : 1;
3894 uint64_t c1_up_b0 : 1;
3895 uint64_t c1_up_b1 : 1;
3896 uint64_t c1_up_b2 : 1;
3897 uint64_t c1_up_wi : 1;
3898 uint64_t c1_up_bx : 1;
3899 uint64_t c1_un_b0 : 1;
3900 uint64_t c1_un_b1 : 1;
3901 uint64_t c1_un_b2 : 1;
3902 uint64_t c1_un_wi : 1;
3903 uint64_t c1_un_bx : 1;
3904 uint64_t c0_un_wf : 1;
3905 uint64_t c1_un_wf : 1;
3906 uint64_t c0_up_wf : 1;
3907 uint64_t c1_up_wf : 1;
3908 uint64_t c0_exc : 1;
3909 uint64_t c1_exc : 1;
3910 uint64_t c0_ldwn : 1;
3911 uint64_t c1_ldwn : 1;
3912 uint64_t reserved_61_62 : 2;
3913 uint64_t mio_inta : 1;
3927 uint64_t u64;
3930 uint64_t reserved_62_63 : 2;
3931 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an
3933 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3935 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3937 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3939 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3941 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3943 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3945 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3947 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3949 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3951 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3953 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3955 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3957 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3959 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3961 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3963 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3965 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3967 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3969 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3971 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3973 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3975 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3977 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3979 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3981 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3983 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3985 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3987 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3989 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3991 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3993 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3995 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an
3997 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3999 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an
4001 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
4003 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
4005 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
4007 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
4009 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an
4011 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
4013 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an
4015 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
4017 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
4019 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
4021 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
4023 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
4025 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
4027 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
4029 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
4031 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
4033 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
4035 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
4037 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
4039 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
4041 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
4043 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
4045 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
4047 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
4049 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
4051 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
4053 uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an
4056 uint64_t rml_rto : 1;
4057 uint64_t rml_wto : 1;
4058 uint64_t bar0_to : 1;
4059 uint64_t iob2big : 1;
4060 uint64_t dma0dbo : 1;
4061 uint64_t dma1dbo : 1;
4062 uint64_t dma2dbo : 1;
4063 uint64_t dma3dbo : 1;
4064 uint64_t dma4dbo : 1;
4065 uint64_t dma0fi : 1;
4066 uint64_t dma1fi : 1;
4067 uint64_t dcnt0 : 1;
4068 uint64_t dcnt1 : 1;
4069 uint64_t dtime0 : 1;
4070 uint64_t dtime1 : 1;
4071 uint64_t psldbof : 1;
4072 uint64_t pidbof : 1;
4073 uint64_t pcnt : 1;
4074 uint64_t ptime : 1;
4075 uint64_t c0_aeri : 1;
4076 uint64_t crs0_er : 1;
4077 uint64_t c0_se : 1;
4078 uint64_t crs0_dr : 1;
4079 uint64_t c0_wake : 1;
4080 uint64_t c0_pmei : 1;
4081 uint64_t c0_hpint : 1;
4082 uint64_t c1_aeri : 1;
4083 uint64_t crs1_er : 1;
4084 uint64_t c1_se : 1;
4085 uint64_t crs1_dr : 1;
4086 uint64_t c1_wake : 1;
4087 uint64_t c1_pmei : 1;
4088 uint64_t c1_hpint : 1;
4089 uint64_t c0_up_b0 : 1;
4090 uint64_t c0_up_b1 : 1;
4091 uint64_t c0_up_b2 : 1;
4092 uint64_t c0_up_wi : 1;
4093 uint64_t c0_up_bx : 1;
4094 uint64_t c0_un_b0 : 1;
4095 uint64_t c0_un_b1 : 1;
4096 uint64_t c0_un_b2 : 1;
4097 uint64_t c0_un_wi : 1;
4098 uint64_t c0_un_bx : 1;
4099 uint64_t c1_up_b0 : 1;
4100 uint64_t c1_up_b1 : 1;
4101 uint64_t c1_up_b2 : 1;
4102 uint64_t c1_up_wi : 1;
4103 uint64_t c1_up_bx : 1;
4104 uint64_t c1_un_b0 : 1;
4105 uint64_t c1_un_b1 : 1;
4106 uint64_t c1_un_b2 : 1;
4107 uint64_t c1_un_wi : 1;
4108 uint64_t c1_un_bx : 1;
4109 uint64_t c0_un_wf : 1;
4110 uint64_t c1_un_wf : 1;
4111 uint64_t c0_up_wf : 1;
4112 uint64_t c1_up_wf : 1;
4113 uint64_t c0_exc : 1;
4114 uint64_t c1_exc : 1;
4115 uint64_t c0_ldwn : 1;
4116 uint64_t c1_ldwn : 1;
4117 uint64_t int_a : 1;
4118 uint64_t reserved_62_63 : 2;
4124 uint64_t reserved_62_63 : 2;
4125 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an
4127 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM2[60] to generate an
4129 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM2[59] to generate an
4131 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM2[58] to generate an
4133 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM2[57] to generate an
4135 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM2[56] to generate an
4137 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM2[55] to generate an
4139 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM2[54] to generate an
4141 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM2[53] to generate an
4143 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM2[52] to generate an
4145 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM2[51] to generate an
4147 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM2[50] to generate an
4149 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM2[49] to generate an
4151 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM2[48] to generate an
4153 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM2[47] to generate an
4155 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM2[46] to generate an
4157 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM2[45] to generate an
4159 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM2[44] to generate an
4161 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM2[43] to generate an
4163 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM2[42] to generate an
4165 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM2[41] to generate an
4167 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM2[40] to generate an
4169 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM2[39] to generate an
4171 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM2[38] to generate an
4173 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM2[37] to generate an
4175 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM2[36] to generate an
4177 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM2[35] to generate an
4179 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM2[34] to generate an
4181 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM2[33] to generate an
4183 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM2[32] to generate an
4185 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM2[31] to generate an
4187 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM2[30] to generate an
4189 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an
4191 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM2[28] to generate an
4193 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an
4195 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM2[26] to generate an
4197 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM2[25] to generate an
4199 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM2[24] to generate an
4201 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM2[23] to generate an
4203 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an
4205 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM2[21] to generate an
4207 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an
4209 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM2[19] to generate an
4211 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM2[18] to generate an
4213 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM2[17] to generate an
4215 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM2[16] to generate an
4217 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM2[15] to generate an
4219 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM2[14] to generate an
4221 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM2[13] to generate an
4223 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM2[12] to generate an
4225 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM2[11] to generate an
4227 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM2[10] to generate an
4229 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM2[9] to generate an
4231 uint64_t reserved_8_8 : 1;
4232 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM2[7] to generate an
4234 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM2[6] to generate an
4236 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM2[5] to generate an
4238 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM2[4] to generate an
4240 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM2[3] to generate an
4242 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM2[2] to generate an
4244 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM2[1] to generate an
4246 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM2[0] to generate an
4249 uint64_t rml_rto : 1;
4250 uint64_t rml_wto : 1;
4251 uint64_t bar0_to : 1;
4252 uint64_t iob2big : 1;
4253 uint64_t dma0dbo : 1;
4254 uint64_t dma1dbo : 1;
4255 uint64_t dma2dbo : 1;
4256 uint64_t dma3dbo : 1;
4257 uint64_t reserved_8_8 : 1;
4258 uint64_t dma0fi : 1;
4259 uint64_t dma1fi : 1;
4260 uint64_t dcnt0 : 1;
4261 uint64_t dcnt1 : 1;
4262 uint64_t dtime0 : 1;
4263 uint64_t dtime1 : 1;
4264 uint64_t psldbof : 1;
4265 uint64_t pidbof : 1;
4266 uint64_t pcnt : 1;
4267 uint64_t ptime : 1;
4268 uint64_t c0_aeri : 1;
4269 uint64_t crs0_er : 1;
4270 uint64_t c0_se : 1;
4271 uint64_t crs0_dr : 1;
4272 uint64_t c0_wake : 1;
4273 uint64_t c0_pmei : 1;
4274 uint64_t c0_hpint : 1;
4275 uint64_t c1_aeri : 1;
4276 uint64_t crs1_er : 1;
4277 uint64_t c1_se : 1;
4278 uint64_t crs1_dr : 1;
4279 uint64_t c1_wake : 1;
4280 uint64_t c1_pmei : 1;
4281 uint64_t c1_hpint : 1;
4282 uint64_t c0_up_b0 : 1;
4283 uint64_t c0_up_b1 : 1;
4284 uint64_t c0_up_b2 : 1;
4285 uint64_t c0_up_wi : 1;
4286 uint64_t c0_up_bx : 1;
4287 uint64_t c0_un_b0 : 1;
4288 uint64_t c0_un_b1 : 1;
4289 uint64_t c0_un_b2 : 1;
4290 uint64_t c0_un_wi : 1;
4291 uint64_t c0_un_bx : 1;
4292 uint64_t c1_up_b0 : 1;
4293 uint64_t c1_up_b1 : 1;
4294 uint64_t c1_up_b2 : 1;
4295 uint64_t c1_up_wi : 1;
4296 uint64_t c1_up_bx : 1;
4297 uint64_t c1_un_b0 : 1;
4298 uint64_t c1_un_b1 : 1;
4299 uint64_t c1_un_b2 : 1;
4300 uint64_t c1_un_wi : 1;
4301 uint64_t c1_un_bx : 1;
4302 uint64_t c0_un_wf : 1;
4303 uint64_t c1_un_wf : 1;
4304 uint64_t c0_up_wf : 1;
4305 uint64_t c1_up_wf : 1;
4306 uint64_t c0_exc : 1;
4307 uint64_t c1_exc : 1;
4308 uint64_t c0_ldwn : 1;
4309 uint64_t c1_ldwn : 1;
4310 uint64_t int_a : 1;
4311 uint64_t reserved_62_63 : 2;
4317 uint64_t reserved_61_63 : 3;
4318 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
4320 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
4322 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
4324 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
4326 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
4328 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
4330 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
4332 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
4334 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
4336 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
4338 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
4340 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
4342 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
4344 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
4346 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
4348 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
4350 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
4352 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
4354 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
4356 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
4358 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
4360 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
4362 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
4364 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
4366 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
4368 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
4370 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
4372 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
4374 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
4376 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
4378 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
4380 uint64_t reserved_29_29 : 1;
4381 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
4383 uint64_t reserved_27_27 : 1;
4384 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
4386 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
4388 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
4390 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
4392 uint64_t reserved_22_22 : 1;
4393 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
4395 uint64_t reserved_20_20 : 1;
4396 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
4398 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
4400 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
4402 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
4404 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
4406 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
4408 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
4410 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
4412 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
4414 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
4416 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
4418 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
4420 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
4422 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
4424 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
4426 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
4428 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
4430 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
4432 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
4434 uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an
4437 uint64_t rml_rto : 1;
4438 uint64_t rml_wto : 1;
4439 uint64_t bar0_to : 1;
4440 uint64_t iob2big : 1;
4441 uint64_t dma0dbo : 1;
4442 uint64_t dma1dbo : 1;
4443 uint64_t dma2dbo : 1;
4444 uint64_t dma3dbo : 1;
4445 uint64_t dma4dbo : 1;
4446 uint64_t dma0fi : 1;
4447 uint64_t dma1fi : 1;
4448 uint64_t dcnt0 : 1;
4449 uint64_t dcnt1 : 1;
4450 uint64_t dtime0 : 1;
4451 uint64_t dtime1 : 1;
4452 uint64_t psldbof : 1;
4453 uint64_t pidbof : 1;
4454 uint64_t pcnt : 1;
4455 uint64_t ptime : 1;
4456 uint64_t c0_aeri : 1;
4457 uint64_t reserved_20_20 : 1;
4458 uint64_t c0_se : 1;
4459 uint64_t reserved_22_22 : 1;
4460 uint64_t c0_wake : 1;
4461 uint64_t c0_pmei : 1;
4462 uint64_t c0_hpint : 1;
4463 uint64_t c1_aeri : 1;
4464 uint64_t reserved_27_27 : 1;
4465 uint64_t c1_se : 1;
4466 uint64_t reserved_29_29 : 1;
4467 uint64_t c1_wake : 1;
4468 uint64_t c1_pmei : 1;
4469 uint64_t c1_hpint : 1;
4470 uint64_t c0_up_b0 : 1;
4471 uint64_t c0_up_b1 : 1;
4472 uint64_t c0_up_b2 : 1;
4473 uint64_t c0_up_wi : 1;
4474 uint64_t c0_up_bx : 1;
4475 uint64_t c0_un_b0 : 1;
4476 uint64_t c0_un_b1 : 1;
4477 uint64_t c0_un_b2 : 1;
4478 uint64_t c0_un_wi : 1;
4479 uint64_t c0_un_bx : 1;
4480 uint64_t c1_up_b0 : 1;
4481 uint64_t c1_up_b1 : 1;
4482 uint64_t c1_up_b2 : 1;
4483 uint64_t c1_up_wi : 1;
4484 uint64_t c1_up_bx : 1;
4485 uint64_t c1_un_b0 : 1;
4486 uint64_t c1_un_b1 : 1;
4487 uint64_t c1_un_b2 : 1;
4488 uint64_t c1_un_wi : 1;
4489 uint64_t c1_un_bx : 1;
4490 uint64_t c0_un_wf : 1;
4491 uint64_t c1_un_wf : 1;
4492 uint64_t c0_up_wf : 1;
4493 uint64_t c1_up_wf : 1;
4494 uint64_t c0_exc : 1;
4495 uint64_t c1_exc : 1;
4496 uint64_t c0_ldwn : 1;
4497 uint64_t c1_ldwn : 1;
4498 uint64_t reserved_61_63 : 3;
4512 uint64_t u64;
4515 uint64_t reserved_12_63 : 52;
4516 uint64_t pidbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit
4519 uint64_t psldbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit
4523 uint64_t psldbof : 6;
4524 uint64_t pidbof : 6;
4525 uint64_t reserved_12_63 : 52;
4554 uint64_t u64;
4557 uint64_t mio_inta : 1; /**< Interrupt from MIO. */
4558 uint64_t reserved_62_62 : 1;
4559 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and
4562 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */
4563 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */
4564 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit
4567 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit
4570 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4572 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4574 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4576 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4578 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4580 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4582 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4584 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4586 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4588 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4590 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4592 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4594 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4596 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4598 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4600 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4602 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4604 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4606 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4608 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4610 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4612 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4614 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4616 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4618 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt.
4623 uint64_t c1_pmei : 1; /**< PME Interrupt.
4625 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit.
4628 uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */
4629 uint64_t c1_se : 1; /**< System Error, RC Mode Only.
4631 uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4632 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4634 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt.
4639 uint64_t c0_pmei : 1; /**< PME Interrupt.
4641 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit.
4644 uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */
4645 uint64_t c0_se : 1; /**< System Error, RC Mode Only.
4647 uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4648 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4650 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
4652 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
4654 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
4656 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
4658 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
4663 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
4668 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
4670 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
4672 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */
4673 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */
4674 uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow.
4676 uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow.
4678 uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow.
4680 uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow.
4682 uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow.
4684 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
4685 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
4687 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */
4688 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */
4690 uint64_t rml_rto : 1;
4691 uint64_t rml_wto : 1;
4692 uint64_t bar0_to : 1;
4693 uint64_t iob2big : 1;
4694 uint64_t dma0dbo : 1;
4695 uint64_t dma1dbo : 1;
4696 uint64_t dma2dbo : 1;
4697 uint64_t dma3dbo : 1;
4698 uint64_t dma4dbo : 1;
4699 uint64_t dma0fi : 1;
4700 uint64_t dma1fi : 1;
4701 uint64_t dcnt0 : 1;
4702 uint64_t dcnt1 : 1;
4703 uint64_t dtime0 : 1;
4704 uint64_t dtime1 : 1;
4705 uint64_t psldbof : 1;
4706 uint64_t pidbof : 1;
4707 uint64_t pcnt : 1;
4708 uint64_t ptime : 1;
4709 uint64_t c0_aeri : 1;
4710 uint64_t crs0_er : 1;
4711 uint64_t c0_se : 1;
4712 uint64_t crs0_dr : 1;
4713 uint64_t c0_wake : 1;
4714 uint64_t c0_pmei : 1;
4715 uint64_t c0_hpint : 1;
4716 uint64_t c1_aeri : 1;
4717 uint64_t crs1_er : 1;
4718 uint64_t c1_se : 1;
4719 uint64_t crs1_dr : 1;
4720 uint64_t c1_wake : 1;
4721 uint64_t c1_pmei : 1;
4722 uint64_t c1_hpint : 1;
4723 uint64_t c0_up_b0 : 1;
4724 uint64_t c0_up_b1 : 1;
4725 uint64_t c0_up_b2 : 1;
4726 uint64_t c0_up_wi : 1;
4727 uint64_t c0_up_bx : 1;
4728 uint64_t c0_un_b0 : 1;
4729 uint64_t c0_un_b1 : 1;
4730 uint64_t c0_un_b2 : 1;
4731 uint64_t c0_un_wi : 1;
4732 uint64_t c0_un_bx : 1;
4733 uint64_t c1_up_b0 : 1;
4734 uint64_t c1_up_b1 : 1;
4735 uint64_t c1_up_b2 : 1;
4736 uint64_t c1_up_wi : 1;
4737 uint64_t c1_up_bx : 1;
4738 uint64_t c1_un_b0 : 1;
4739 uint64_t c1_un_b1 : 1;
4740 uint64_t c1_un_b2 : 1;
4741 uint64_t c1_un_wi : 1;
4742 uint64_t c1_un_bx : 1;
4743 uint64_t c0_un_wf : 1;
4744 uint64_t c1_un_wf : 1;
4745 uint64_t c0_up_wf : 1;
4746 uint64_t c1_up_wf : 1;
4747 uint64_t c0_exc : 1;
4748 uint64_t c1_exc : 1;
4749 uint64_t c0_ldwn : 1;
4750 uint64_t c1_ldwn : 1;
4751 uint64_t int_a : 1;
4752 uint64_t reserved_62_62 : 1;
4753 uint64_t mio_inta : 1;
4759 uint64_t mio_inta : 1; /**< Interrupt from MIO. */
4760 uint64_t reserved_62_62 : 1;
4761 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and
4764 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */
4765 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */
4766 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit
4769 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit
4772 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4774 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4776 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4778 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4780 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4782 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4784 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4786 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4788 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4790 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4792 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4794 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4796 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4798 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4800 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4802 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4804 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4806 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4808 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4810 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4812 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4814 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4816 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4818 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4820 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt.
4825 uint64_t c1_pmei : 1; /**< PME Interrupt.
4827 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit.
4830 uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */
4831 uint64_t c1_se : 1; /**< System Error, RC Mode Only.
4833 uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4834 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4836 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt.
4841 uint64_t c0_pmei : 1; /**< PME Interrupt.
4843 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit.
4846 uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */
4847 uint64_t c0_se : 1; /**< System Error, RC Mode Only.
4849 uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4850 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4852 uint64_t reserved_15_18 : 4;
4853 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
4858 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
4863 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
4865 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
4867 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */
4868 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */
4869 uint64_t reserved_8_8 : 1;
4870 uint64_t dma3dbo : 1; /**< DMA3 doorbell count overflow.
4872 uint64_t dma2dbo : 1; /**< DMA2 doorbell count overflow.
4874 uint64_t dma1dbo : 1; /**< DMA1 doorbell count overflow.
4876 uint64_t dma0dbo : 1; /**< DMA0 doorbell count overflow.
4878 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
4879 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
4881 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */
4882 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */
4884 uint64_t rml_rto : 1;
4885 uint64_t rml_wto : 1;
4886 uint64_t bar0_to : 1;
4887 uint64_t iob2big : 1;
4888 uint64_t dma0dbo : 1;
4889 uint64_t dma1dbo : 1;
4890 uint64_t dma2dbo : 1;
4891 uint64_t dma3dbo : 1;
4892 uint64_t reserved_8_8 : 1;
4893 uint64_t dma0fi : 1;
4894 uint64_t dma1fi : 1;
4895 uint64_t dcnt0 : 1;
4896 uint64_t dcnt1 : 1;
4897 uint64_t dtime0 : 1;
4898 uint64_t dtime1 : 1;
4899 uint64_t reserved_15_18 : 4;
4900 uint64_t c0_aeri : 1;
4901 uint64_t crs0_er : 1;
4902 uint64_t c0_se : 1;
4903 uint64_t crs0_dr : 1;
4904 uint64_t c0_wake : 1;
4905 uint64_t c0_pmei : 1;
4906 uint64_t c0_hpint : 1;
4907 uint64_t c1_aeri : 1;
4908 uint64_t crs1_er : 1;
4909 uint64_t c1_se : 1;
4910 uint64_t crs1_dr : 1;
4911 uint64_t c1_wake : 1;
4912 uint64_t c1_pmei : 1;
4913 uint64_t c1_hpint : 1;
4914 uint64_t c0_up_b0 : 1;
4915 uint64_t c0_up_b1 : 1;
4916 uint64_t c0_up_b2 : 1;
4917 uint64_t c0_up_wi : 1;
4918 uint64_t c0_up_bx : 1;
4919 uint64_t c0_un_b0 : 1;
4920 uint64_t c0_un_b1 : 1;
4921 uint64_t c0_un_b2 : 1;
4922 uint64_t c0_un_wi : 1;
4923 uint64_t c0_un_bx : 1;
4924 uint64_t c1_up_b0 : 1;
4925 uint64_t c1_up_b1 : 1;
4926 uint64_t c1_up_b2 : 1;
4927 uint64_t c1_up_wi : 1;
4928 uint64_t c1_up_bx : 1;
4929 uint64_t c1_un_b0 : 1;
4930 uint64_t c1_un_b1 : 1;
4931 uint64_t c1_un_b2 : 1;
4932 uint64_t c1_un_wi : 1;
4933 uint64_t c1_un_bx : 1;
4934 uint64_t c0_un_wf : 1;
4935 uint64_t c1_un_wf : 1;
4936 uint64_t c0_up_wf : 1;
4937 uint64_t c1_up_wf : 1;
4938 uint64_t c0_exc : 1;
4939 uint64_t c1_exc : 1;
4940 uint64_t c0_ldwn : 1;
4941 uint64_t c1_ldwn : 1;
4942 uint64_t int_a : 1;
4943 uint64_t reserved_62_62 : 1;
4944 uint64_t mio_inta : 1;
4950 uint64_t mio_inta : 1; /**< Interrupt from MIO. */
4951 uint64_t reserved_61_62 : 2;
4952 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */
4953 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */
4954 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit
4957 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit
4960 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4962 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4964 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4966 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4968 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4970 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4972 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4974 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4976 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4978 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4980 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4982 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4984 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4986 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4988 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4990 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4992 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4994 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4996 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4998 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
5000 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
5002 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
5004 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
5006 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
5008 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt.
5013 uint64_t c1_pmei : 1; /**< PME Interrupt.
5015 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit.
5018 uint64_t reserved_29_29 : 1;
5019 uint64_t c1_se : 1; /**< System Error, RC Mode Only.
5021 uint64_t reserved_27_27 : 1;
5022 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
5024 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt.
5029 uint64_t c0_pmei : 1; /**< PME Interrupt.
5031 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit.
5034 uint64_t reserved_22_22 : 1;
5035 uint64_t c0_se : 1; /**< System Error, RC Mode Only.
5037 uint64_t reserved_20_20 : 1;
5038 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
5040 uint64_t reserved_15_18 : 4;
5041 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
5046 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
5051 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
5053 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
5055 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */
5056 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */
5057 uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow.
5059 uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow.
5061 uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow.
5063 uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow.
5065 uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow.
5067 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
5068 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
5070 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */
5071 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */
5073 uint64_t rml_rto : 1;
5074 uint64_t rml_wto : 1;
5075 uint64_t bar0_to : 1;
5076 uint64_t iob2big : 1;
5077 uint64_t dma0dbo : 1;
5078 uint64_t dma1dbo : 1;
5079 uint64_t dma2dbo : 1;
5080 uint64_t dma3dbo : 1;
5081 uint64_t dma4dbo : 1;
5082 uint64_t dma0fi : 1;
5083 uint64_t dma1fi : 1;
5084 uint64_t dcnt0 : 1;
5085 uint64_t dcnt1 : 1;
5086 uint64_t dtime0 : 1;
5087 uint64_t dtime1 : 1;
5088 uint64_t reserved_15_18 : 4;
5089 uint64_t c0_aeri : 1;
5090 uint64_t reserved_20_20 : 1;
5091 uint64_t c0_se : 1;
5092 uint64_t reserved_22_22 : 1;
5093 uint64_t c0_wake : 1;
5094 uint64_t c0_pmei : 1;
5095 uint64_t c0_hpint : 1;
5096 uint64_t c1_aeri : 1;
5097 uint64_t reserved_27_27 : 1;
5098 uint64_t c1_se : 1;
5099 uint64_t reserved_29_29 : 1;
5100 uint64_t c1_wake : 1;
5101 uint64_t c1_pmei : 1;
5102 uint64_t c1_hpint : 1;
5103 uint64_t c0_up_b0 : 1;
5104 uint64_t c0_up_b1 : 1;
5105 uint64_t c0_up_b2 : 1;
5106 uint64_t c0_up_wi : 1;
5107 uint64_t c0_up_bx : 1;
5108 uint64_t c0_un_b0 : 1;
5109 uint64_t c0_un_b1 : 1;
5110 uint64_t c0_un_b2 : 1;
5111 uint64_t c0_un_wi : 1;
5112 uint64_t c0_un_bx : 1;
5113 uint64_t c1_up_b0 : 1;
5114 uint64_t c1_up_b1 : 1;
5115 uint64_t c1_up_b2 : 1;
5116 uint64_t c1_up_wi : 1;
5117 uint64_t c1_up_bx : 1;
5118 uint64_t c1_un_b0 : 1;
5119 uint64_t c1_un_b1 : 1;
5120 uint64_t c1_un_b2 : 1;
5121 uint64_t c1_un_wi : 1;
5122 uint64_t c1_un_bx : 1;
5123 uint64_t c0_un_wf : 1;
5124 uint64_t c1_un_wf : 1;
5125 uint64_t c0_up_wf : 1;
5126 uint64_t c1_up_wf : 1;
5127 uint64_t c0_exc : 1;
5128 uint64_t c1_exc : 1;
5129 uint64_t c0_ldwn : 1;
5130 uint64_t c1_ldwn : 1;
5131 uint64_t reserved_61_62 : 2;
5132 uint64_t mio_inta : 1;
5146 uint64_t u64;
5149 uint64_t mio_inta : 1; /**< Equal to the cooresponding bit if the
5151 uint64_t reserved_62_62 : 1;
5152 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and
5155 uint64_t c1_ldwn : 1; /**< Equal to the cooresponding bit if the
5157 uint64_t c0_ldwn : 1; /**< Equal to the cooresponding bit if the
5159 uint64_t c1_exc : 1; /**< Equal to the cooresponding bit if the
5161 uint64_t c0_exc : 1; /**< Equal to the cooresponding bit if the
5163 uint64_t c1_up_wf : 1; /**< Equal to the cooresponding bit if the
5165 uint64_t c0_up_wf : 1; /**< Equal to the cooresponding bit if the
5167 uint64_t c1_un_wf : 1; /**< Equal to the cooresponding bit if the
5169 uint64_t c0_un_wf : 1; /**< Equal to the cooresponding bit if the
5171 uint64_t c1_un_bx : 1; /**< Equal to the cooresponding bit if the
5173 uint64_t c1_un_wi : 1; /**< Equal to the cooresponding bit if the
5175 uint64_t c1_un_b2 : 1; /**< Equal to the cooresponding bit if the
5177 uint64_t c1_un_b1 : 1; /**< Equal to the cooresponding bit if the
5179 uint64_t c1_un_b0 : 1; /**< Equal to the cooresponding bit if the
5181 uint64_t c1_up_bx : 1; /**< Equal to the cooresponding bit if the
5183 uint64_t c1_up_wi : 1; /**< Equal to the cooresponding bit if the
5185 uint64_t c1_up_b2 : 1; /**< Equal to the cooresponding bit if the
5187 uint64_t c1_up_b1 : 1; /**< Equal to the cooresponding bit if the
5189 uint64_t c1_up_b0 : 1; /**< Equal to the cooresponding bit if the
5191 uint64_t c0_un_bx : 1; /**< Equal to the cooresponding bit if the
5193 uint64_t c0_un_wi : 1; /**< Equal to the cooresponding bit if the
5195 uint64_t c0_un_b2 : 1; /**< Equal to the cooresponding bit if the
5197 uint64_t c0_un_b1 : 1; /**< Equal to the cooresponding bit if the
5199 uint64_t c0_un_b0 : 1; /**< Equal to the cooresponding bit if the
5201 uint64_t c0_up_bx : 1; /**< Equal to the cooresponding bit if the
5203 uint64_t c0_up_wi : 1; /**< Equal to the cooresponding bit if the
5205 uint64_t c0_up_b2 : 1; /**< Equal to the cooresponding bit if the
5207 uint64_t c0_up_b1 : 1; /**< Equal to the cooresponding bit if the
5209 uint64_t c0_up_b0 : 1; /**< Equal to the cooresponding bit if the
5211 uint64_t c1_hpint : 1; /**< Equal to the cooresponding bit if the
5213 uint64_t c1_pmei : 1; /**< Equal to the cooresponding bit if the
5215 uint64_t c1_wake : 1; /**< Equal to the cooresponding bit if the
5217 uint64_t crs1_dr : 1; /**< Equal to the cooresponding bit if the
5219 uint64_t c1_se : 1; /**< Equal to the cooresponding bit if the
5221 uint64_t crs1_er : 1; /**< Equal to the cooresponding bit if the
5223 uint64_t c1_aeri : 1; /**< Equal to the cooresponding bit if the
5225 uint64_t c0_hpint : 1; /**< Equal to the cooresponding bit if the
5227 uint64_t c0_pmei : 1; /**< Equal to the cooresponding bit if the
5229 uint64_t c0_wake : 1; /**< Equal to the cooresponding bit if the
5231 uint64_t crs0_dr : 1; /**< Equal to the cooresponding bit if the
5233 uint64_t c0_se : 1; /**< Equal to the cooresponding bit if the
5235 uint64_t crs0_er : 1; /**< Equal to the cooresponding bit if the
5237 uint64_t c0_aeri : 1; /**< Equal to the cooresponding bit if the
5239 uint64_t reserved_15_18 : 4;
5240 uint64_t dtime1 : 1; /**< Equal to the cooresponding bit if the
5242 uint64_t dtime0 : 1; /**< Equal to the cooresponding bit if the
5244 uint64_t dcnt1 : 1; /**< Equal to the cooresponding bit if the
5246 uint64_t dcnt0 : 1; /**< Equal to the cooresponding bit if the
5248 uint64_t dma1fi : 1; /**< Equal to the cooresponding bit if the
5250 uint64_t dma0fi : 1; /**< Equal to the cooresponding bit if the
5252 uint64_t reserved_8_8 : 1;
5253 uint64_t dma3dbo : 1; /**< Equal to the cooresponding bit if the
5255 uint64_t dma2dbo : 1; /**< Equal to the cooresponding bit if the
5257 uint64_t dma1dbo : 1; /**< Equal to the cooresponding bit if the
5259 uint64_t dma0dbo : 1; /**< Equal to the cooresponding bit if the
5261 uint64_t iob2big : 1; /**< Equal to the cooresponding bit if the
5263 uint64_t bar0_to : 1; /**< Equal to the cooresponding bit if the
5265 uint64_t rml_wto : 1; /**< Equal to the cooresponding bit if the
5267 uint64_t rml_rto : 1; /**< Equal to the cooresponding bit if the
5270 uint64_t rml_rto : 1;
5271 uint64_t rml_wto : 1;
5272 uint64_t bar0_to : 1;
5273 uint64_t iob2big : 1;
5274 uint64_t dma0dbo : 1;
5275 uint64_t dma1dbo : 1;
5276 uint64_t dma2dbo : 1;
5277 uint64_t dma3dbo : 1;
5278 uint64_t reserved_8_8 : 1;
5279 uint64_t dma0fi : 1;
5280 uint64_t dma1fi : 1;
5281 uint64_t dcnt0 : 1;
5282 uint64_t dcnt1 : 1;
5283 uint64_t dtime0 : 1;
5284 uint64_t dtime1 : 1;
5285 uint64_t reserved_15_18 : 4;
5286 uint64_t c0_aeri : 1;
5287 uint64_t crs0_er : 1;
5288 uint64_t c0_se : 1;
5289 uint64_t crs0_dr : 1;
5290 uint64_t c0_wake : 1;
5291 uint64_t c0_pmei : 1;
5292 uint64_t c0_hpint : 1;
5293 uint64_t c1_aeri : 1;
5294 uint64_t crs1_er : 1;
5295 uint64_t c1_se : 1;
5296 uint64_t crs1_dr : 1;
5297 uint64_t c1_wake : 1;
5298 uint64_t c1_pmei : 1;
5299 uint64_t c1_hpint : 1;
5300 uint64_t c0_up_b0 : 1;
5301 uint64_t c0_up_b1 : 1;
5302 uint64_t c0_up_b2 : 1;
5303 uint64_t c0_up_wi : 1;
5304 uint64_t c0_up_bx : 1;
5305 uint64_t c0_un_b0 : 1;
5306 uint64_t c0_un_b1 : 1;
5307 uint64_t c0_un_b2 : 1;
5308 uint64_t c0_un_wi : 1;
5309 uint64_t c0_un_bx : 1;
5310 uint64_t c1_up_b0 : 1;
5311 uint64_t c1_up_b1 : 1;
5312 uint64_t c1_up_b2 : 1;
5313 uint64_t c1_up_wi : 1;
5314 uint64_t c1_up_bx : 1;
5315 uint64_t c1_un_b0 : 1;
5316 uint64_t c1_un_b1 : 1;
5317 uint64_t c1_un_b2 : 1;
5318 uint64_t c1_un_wi : 1;
5319 uint64_t c1_un_bx : 1;
5320 uint64_t c0_un_wf : 1;
5321 uint64_t c1_un_wf : 1;
5322 uint64_t c0_up_wf : 1;
5323 uint64_t c1_up_wf : 1;
5324 uint64_t c0_exc : 1;
5325 uint64_t c1_exc : 1;
5326 uint64_t c0_ldwn : 1;
5327 uint64_t c1_ldwn : 1;
5328 uint64_t int_a : 1;
5329 uint64_t reserved_62_62 : 1;
5330 uint64_t mio_inta : 1;
5347 uint64_t u64;
5350 uint64_t data : 64; /**< Last window read data. */
5352 uint64_t data : 64;
5370 uint64_t u64;
5373 uint64_t data : 64; /**< Last window read data. */
5375 uint64_t data : 64;
5393 uint64_t u64;
5396 uint64_t reserved_14_63 : 50;
5397 uint64_t max_word : 4; /**< The maximum number of words to merge into a single
5400 uint64_t timer : 10; /**< When the NPEI starts a PP to PCIe write it waits
5406 uint64_t timer : 10;
5407 uint64_t max_word : 4;
5408 uint64_t reserved_14_63 : 50;
5426 uint64_t u64;
5429 uint64_t reserved_42_63 : 22;
5430 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads.
5432 uint64_t port : 2; /**< Port the request is sent to. */
5433 uint64_t nmerge : 1; /**< No merging is allowed in this window. */
5434 uint64_t esr : 2; /**< Endian-swap for Reads. */
5435 uint64_t esw : 2; /**< Endian-swap for Writes. */
5436 uint64_t nsr : 1; /**< No Snoop for Reads. */
5437 uint64_t nsw : 1; /**< No Snoop for Writes. */
5438 uint64_t ror : 1; /**< Relaxed Ordering for Reads. */
5439 uint64_t row : 1; /**< Relaxed Ordering for Writes. */
5440 uint64_t ba : 30; /**< PCIe Adddress Bits <63:34>. */
5442 uint64_t ba : 30;
5443 uint64_t row : 1;
5444 uint64_t ror : 1;
5445 uint64_t nsw : 1;
5446 uint64_t nsr : 1;
5447 uint64_t esw : 2;
5448 uint64_t esr : 2;
5449 uint64_t nmerge : 1;
5450 uint64_t port : 2;
5451 uint64_t zero : 1;
5452 uint64_t reserved_42_63 : 22;
5470 uint64_t u64;
5473 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */
5475 uint64_t enb : 64;
5493 uint64_t u64;
5496 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */
5498 uint64_t enb : 64;
5516 uint64_t u64;
5519 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */
5521 uint64_t enb : 64;
5539 uint64_t u64;
5542 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */
5544 uint64_t enb : 64;
5562 uint64_t u64;
5565 uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
5567 uint64_t intr : 64;
5585 uint64_t u64;
5588 uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
5590 uint64_t intr : 64;
5608 uint64_t u64;
5611 uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
5613 uint64_t intr : 64;
5631 uint64_t u64;
5634 uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
5636 uint64_t intr : 64;
5654 uint64_t u64;
5657 uint64_t reserved_16_63 : 48;
5658 uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY
5660 uint64_t msi_int : 8; /**< Selects the value that would be received when the
5663 uint64_t msi_int : 8;
5664 uint64_t rd_int : 8;
5665 uint64_t reserved_16_63 : 48;
5683 uint64_t u64;
5686 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5690 uint64_t clr : 64;
5706 uint64_t u64;
5709 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5713 uint64_t clr : 64;
5729 uint64_t u64;
5732 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5736 uint64_t clr : 64;
5752 uint64_t u64;
5755 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5759 uint64_t clr : 64;
5775 uint64_t u64;
5778 uint64_t set : 64; /**< A write of '1' to a vector will set the
5782 uint64_t set : 64;
5798 uint64_t u64;
5801 uint64_t set : 64; /**< A write of '1' to a vector will set the
5805 uint64_t set : 64;
5821 uint64_t u64;
5824 uint64_t set : 64; /**< A write of '1' to a vector will set the
5828 uint64_t set : 64;
5844 uint64_t u64;
5847 uint64_t set : 64; /**< A write of '1' to a vector will set the
5851 uint64_t set : 64;
5867 uint64_t u64;
5870 uint64_t reserved_16_63 : 48;
5871 uint64_t ciu_int : 8; /**< Selects which bit in the NPEI_MSI_RCV# (0-255)
5875 uint64_t msi_int : 8; /**< Selects the value that would be received when the
5878 uint64_t msi_int : 8;
5879 uint64_t ciu_int : 8;
5880 uint64_t reserved_16_63 : 48;
5900 uint64_t u64;
5903 uint64_t reserved_48_63 : 16;
5904 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits.
5906 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits.
5908 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits.
5910 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits.
5912 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits.
5914 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits.
5917 uint64_t p0_pcnt : 8;
5918 uint64_t p0_ncnt : 8;
5919 uint64_t p0_ccnt : 8;
5920 uint64_t p1_pcnt : 8;
5921 uint64_t p1_ncnt : 8;
5922 uint64_t p1_ccnt : 8;
5923 uint64_t reserved_48_63 : 16;
5939 uint64_t u64;
5942 uint64_t reserved_8_63 : 56;
5943 uint64_t intr : 8; /**< A write to this register will result in a bit in
5949 uint64_t intr : 8;
5950 uint64_t reserved_8_63 : 56;
5968 uint64_t u64;
5971 uint64_t reserved_16_63 : 48;
5972 uint64_t intr : 8; /**< A write to this register will result in a bit in
5977 uint64_t reserved_0_7 : 8;
5979 uint64_t reserved_0_7 : 8;
5980 uint64_t intr : 8;
5981 uint64_t reserved_16_63 : 48;
5999 uint64_t u64;
6002 uint64_t reserved_24_63 : 40;
6003 uint64_t intr : 8; /**< A write to this register will result in a bit in
6008 uint64_t reserved_0_15 : 16;
6010 uint64_t reserved_0_15 : 16;
6011 uint64_t intr : 8;
6012 uint64_t reserved_24_63 : 40;
6030 uint64_t u64;
6033 uint64_t reserved_32_63 : 32;
6034 uint64_t intr : 8; /**< A write to this register will result in a bit in
6039 uint64_t reserved_0_23 : 24;
6041 uint64_t reserved_0_23 : 24;
6042 uint64_t intr : 8;
6043 uint64_t reserved_32_63 : 32;
6061 uint64_t u64;
6064 uint64_t reserved_54_63 : 10;
6065 uint64_t timer : 22; /**< Timer incremented every 1024 core clocks
6072 uint64_t cnt : 32; /**< ring counter. This field is incremented as
6082 uint64_t cnt : 32;
6083 uint64_t timer : 22;
6084 uint64_t reserved_54_63 : 10;
6100 uint64_t u64;
6103 uint64_t wmark : 32; /**< When CNT is greater than this threshold no more
6108 uint64_t cnt : 32; /**< ring counter. This field is incremented by one
6117 uint64_t cnt : 32;
6118 uint64_t wmark : 32;
6134 uint64_t u64;
6137 uint64_t addr : 61; /**< Base address for Instructions. */
6138 uint64_t reserved_0_2 : 3;
6140 uint64_t reserved_0_2 : 3;
6141 uint64_t addr : 61;
6157 uint64_t u64;
6160 uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR
6162 uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field
6167 uint64_t dbell : 32;
6168 uint64_t aoff : 32;
6184 uint64_t u64;
6187 uint64_t max : 9; /**< Max Fifo Size. */
6188 uint64_t rrp : 9; /**< Fifo read pointer. */
6189 uint64_t wrp : 9; /**< Fifo write pointer. */
6190 uint64_t fcnt : 5; /**< Fifo count. */
6191 uint64_t rsize : 32; /**< Instruction ring size. */
6193 uint64_t rsize : 32;
6194 uint64_t fcnt : 5;
6195 uint64_t wrp : 9;
6196 uint64_t rrp : 9;
6197 uint64_t max : 9;
6213 uint64_t u64;
6216 uint64_t reserved_44_63 : 20;
6217 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
6218 uint64_t reserved_38_42 : 5;
6219 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
6220 uint64_t reserved_35_35 : 1;
6221 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
6222 uint64_t reserved_22_27 : 6;
6223 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
6227 uint64_t reserved_16_20 : 5;
6228 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
6230 uint64_t reserved_13_13 : 1;
6231 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
6233 uint64_t reserved_0_5 : 6;
6235 uint64_t reserved_0_5 : 6;
6236 uint64_t skp_len : 7;
6237 uint64_t reserved_13_13 : 1;
6238 uint64_t par_mode : 2;
6239 uint64_t reserved_16_20 : 5;
6240 uint64_t use_ihdr : 1;
6241 uint64_t reserved_22_27 : 6;
6242 uint64_t rskp_len : 7;
6243 uint64_t reserved_35_35 : 1;
6244 uint64_t rparmode : 2;
6245 uint64_t reserved_38_42 : 5;
6246 uint64_t pbp : 1;
6247 uint64_t reserved_44_63 : 20;
6263 uint64_t u64;
6266 uint64_t addr : 60; /**< Base address for scatter list pointers. */
6267 uint64_t reserved_0_3 : 4;
6269 uint64_t reserved_0_3 : 4;
6270 uint64_t addr : 60;
6286 uint64_t u64;
6289 uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR
6293 uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field
6300 uint64_t dbell : 32;
6301 uint64_t aoff : 32;
6317 uint64_t u64;
6320 uint64_t reserved_32_63 : 32;
6321 uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in
6324 uint64_t rsize : 32;
6325 uint64_t reserved_32_63 : 32;
6341 uint64_t u64;
6344 uint64_t reserved_32_63 : 32;
6345 uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when
6349 uint64_t port : 32;
6350 uint64_t reserved_32_63 : 32;
6366 uint64_t u64;
6369 uint64_t reserved_32_63 : 32;
6370 uint64_t port : 32; /**< Bit vector cooresponding to ring number when set
6373 uint64_t port : 32;
6374 uint64_t reserved_32_63 : 32;
6390 uint64_t u64;
6393 uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31.
6397 uint64_t es : 64;
6413 uint64_t u64;
6416 uint64_t reserved_32_63 : 32;
6417 uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding
6420 uint64_t nsr : 32;
6421 uint64_t reserved_32_63 : 32;
6437 uint64_t u64;
6440 uint64_t reserved_32_63 : 32;
6441 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding
6444 uint64_t ror : 32;
6445 uint64_t reserved_32_63 : 32;
6461 uint64_t u64;
6464 uint64_t reserved_32_63 : 32;
6465 uint64_t dptr : 32; /**< When asserted '1' the vector bit cooresponding
6475 uint64_t dptr : 32;
6476 uint64_t reserved_32_63 : 32;
6492 uint64_t u64;
6495 uint64_t reserved_32_63 : 32;
6496 uint64_t bp : 32; /**< A packet input ring that has its count greater
6503 uint64_t bp : 32;
6504 uint64_t reserved_32_63 : 32;
6520 uint64_t u64;
6523 uint64_t reserved_32_63 : 32;
6524 uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction
6528 uint64_t cnt : 32;
6529 uint64_t reserved_32_63 : 32;
6545 uint64_t u64;
6548 uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */
6549 uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads
6553 uint64_t rd_cnt : 32;
6554 uint64_t wr_cnt : 32;
6570 uint64_t u64;
6573 uint64_t pp : 64; /**< The PCIe port that the Packet ring number is
6579 uint64_t pp : 64;
6595 uint64_t u64;
6598 uint64_t reserved_23_63 : 41;
6599 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
6603 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in
6605 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of
6607 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of
6609 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of
6611 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
6616 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of
6618 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of
6620 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of
6623 uint64_t ror : 1;
6624 uint64_t esr : 2;
6625 uint64_t nsr : 1;
6626 uint64_t use_csr : 1;
6627 uint64_t d_ror : 1;
6628 uint64_t d_esr : 2;
6629 uint64_t d_nsr : 1;
6630 uint64_t pbp_dhi : 13;
6631 uint64_t pkt_rr : 1;
6632 uint64_t reserved_23_63 : 41;
6648 uint64_t u64;
6651 uint64_t reserved_32_63 : 32;
6652 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding
6655 uint64_t enb : 32;
6656 uint64_t reserved_32_63 : 32;
6672 uint64_t u64;
6675 uint64_t rdsize : 64; /**< Number of instructions to be read in one PCIe read
6687 uint64_t rdsize : 64;
6703 uint64_t u64;
6706 uint64_t reserved_32_63 : 32;
6707 uint64_t is_64b : 32; /**< When asserted '1' the vector bit cooresponding
6710 uint64_t is_64b : 32;
6711 uint64_t reserved_32_63 : 32;
6730 uint64_t u64;
6733 uint64_t reserved_54_63 : 10;
6734 uint64_t time : 22; /**< When NPEI_PKT#_CNTS[TIMER] is greater than this
6736 uint64_t cnt : 32; /**< When NPEI_PKT#_CNTS[CNT] becomes
6739 uint64_t cnt : 32;
6740 uint64_t time : 22;
6741 uint64_t reserved_54_63 : 10;
6757 uint64_t u64;
6760 uint64_t reserved_32_63 : 32;
6761 uint64_t iptr : 32; /**< When asserted '1' the vector bit cooresponding
6765 uint64_t iptr : 32;
6766 uint64_t reserved_32_63 : 32;
6782 uint64_t u64;
6785 uint64_t reserved_32_63 : 32;
6786 uint64_t bmode : 32; /**< When asserted '1' the vector bit cooresponding
6792 uint64_t bmode : 32;
6793 uint64_t reserved_32_63 : 32;
6809 uint64_t u64;
6812 uint64_t reserved_32_63 : 32;
6813 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding
6819 uint64_t enb : 32;
6820 uint64_t reserved_32_63 : 32;
6836 uint64_t u64;
6839 uint64_t reserved_32_63 : 32;
6840 uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure
6843 uint64_t wmark : 32;
6844 uint64_t reserved_32_63 : 32;
6860 uint64_t u64;
6863 uint64_t pp : 64; /**< The PCIe port that the Packet ring number is
6869 uint64_t pp : 64;
6885 uint64_t u64;
6888 uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding
6890 uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding
6893 uint64_t out_rst : 32;
6894 uint64_t in_rst : 32;
6910 uint64_t u64;
6913 uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31.
6917 uint64_t es : 64;
6933 uint64_t u64;
6936 uint64_t reserved_23_63 : 41;
6937 uint64_t isize : 7; /**< Information size. Legal sizes are 0 to 120. */
6938 uint64_t bsize : 16; /**< Data size. */
6940 uint64_t bsize : 16;
6941 uint64_t isize : 7;
6942 uint64_t reserved_23_63 : 41;
6958 uint64_t u64;
6961 uint64_t reserved_32_63 : 32;
6962 uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding
6965 uint64_t nsr : 32;
6966 uint64_t reserved_32_63 : 32;
6982 uint64_t u64;
6985 uint64_t reserved_32_63 : 32;
6986 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding
6989 uint64_t ror : 32;
6990 uint64_t reserved_32_63 : 32;
7006 uint64_t u64;
7009 uint64_t reserved_32_63 : 32;
7010 uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when
7014 uint64_t port : 32;
7015 uint64_t reserved_32_63 : 32;
7031 uint64_t u64;
7034 uint64_t reserved_32_63 : 32;
7035 uint64_t port : 32; /**< Bit vector cooresponding to ring number when set
7038 uint64_t port : 32;
7039 uint64_t reserved_32_63 : 32;
7057 uint64_t u64;
7060 uint64_t reserved_31_63 : 33;
7061 uint64_t iob : 1; /**< IOB_INT_SUM */
7062 uint64_t lmc1 : 1; /**< LMC1_MEM_CFG0 */
7063 uint64_t agl : 1; /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */
7064 uint64_t reserved_24_27 : 4;
7065 uint64_t asxpcs1 : 1; /**< PCS1_INT*_REG */
7066 uint64_t asxpcs0 : 1; /**< PCS0_INT*_REG */
7067 uint64_t reserved_21_21 : 1;
7068 uint64_t pip : 1; /**< PIP_INT_REG. */
7069 uint64_t spx1 : 1; /**< Always reads as zero */
7070 uint64_t spx0 : 1; /**< Always reads as zero */
7071 uint64_t lmc0 : 1; /**< LMC0_MEM_CFG0 */
7072 uint64_t l2c : 1; /**< L2C_INT_STAT */
7073 uint64_t usb1 : 1; /**< Always reads as zero */
7074 uint64_t rad : 1; /**< RAD_REG_ERROR */
7075 uint64_t usb : 1; /**< USBN0_INT_SUM */
7076 uint64_t pow : 1; /**< POW_ECC_ERR */
7077 uint64_t tim : 1; /**< TIM_REG_ERROR */
7078 uint64_t pko : 1; /**< PKO_REG_ERROR */
7079 uint64_t ipd : 1; /**< IPD_INT_SUM */
7080 uint64_t reserved_8_8 : 1;
7081 uint64_t zip : 1; /**< ZIP_ERROR */
7082 uint64_t dfa : 1; /**< Always reads as zero */
7083 uint64_t fpa : 1; /**< FPA_INT_SUM */
7084 uint64_t key : 1; /**< KEY_INT_SUM */
7085 uint64_t npei : 1; /**< NPEI_INT_SUM */
7086 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
7087 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
7088 uint64_t mio : 1; /**< MIO_BOOT_ERR */
7090 uint64_t mio : 1;
7091 uint64_t gmx0 : 1;
7092 uint64_t gmx1 : 1;
7093 uint64_t npei : 1;
7094 uint64_t key : 1;
7095 uint64_t fpa : 1;
7096 uint64_t dfa : 1;
7097 uint64_t zip : 1;
7098 uint64_t reserved_8_8 : 1;
7099 uint64_t ipd : 1;
7100 uint64_t pko : 1;
7101 uint64_t tim : 1;
7102 uint64_t pow : 1;
7103 uint64_t usb : 1;
7104 uint64_t rad : 1;
7105 uint64_t usb1 : 1;
7106 uint64_t l2c : 1;
7107 uint64_t lmc0 : 1;
7108 uint64_t spx0 : 1;
7109 uint64_t spx1 : 1;
7110 uint64_t pip : 1;
7111 uint64_t reserved_21_21 : 1;
7112 uint64_t asxpcs0 : 1;
7113 uint64_t asxpcs1 : 1;
7114 uint64_t reserved_24_27 : 4;
7115 uint64_t agl : 1;
7116 uint64_t lmc1 : 1;
7117 uint64_t iob : 1;
7118 uint64_t reserved_31_63 : 33;
7136 uint64_t u64;
7139 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */
7141 uint64_t data : 64;
7159 uint64_t u64;
7162 uint64_t cpl1 : 12; /**< CPL1 State */
7163 uint64_t cpl0 : 12; /**< CPL0 State */
7164 uint64_t arb : 1; /**< ARB State */
7165 uint64_t csr : 39; /**< CSR State */
7167 uint64_t csr : 39;
7168 uint64_t arb : 1;
7169 uint64_t cpl0 : 12;
7170 uint64_t cpl1 : 12;
7188 uint64_t u64;
7191 uint64_t reserved_48_63 : 16;
7192 uint64_t npei : 1; /**< NPEI State */
7193 uint64_t rac : 1; /**< RAC State */
7194 uint64_t csm1 : 15; /**< CSM1 State */
7195 uint64_t csm0 : 15; /**< CSM0 State */
7196 uint64_t nnp0 : 8; /**< NNP0 State */
7197 uint64_t nnd : 8; /**< NND State */
7199 uint64_t nnd : 8;
7200 uint64_t nnp0 : 8;
7201 uint64_t csm0 : 15;
7202 uint64_t csm1 : 15;
7203 uint64_t rac : 1;
7204 uint64_t npei : 1;
7205 uint64_t reserved_48_63 : 16;
7223 uint64_t u64;
7226 uint64_t reserved_56_63 : 8;
7227 uint64_t psm1 : 15; /**< PSM1 State */
7228 uint64_t psm0 : 15; /**< PSM0 State */
7229 uint64_t nsm1 : 13; /**< NSM1 State */
7230 uint64_t nsm0 : 13; /**< NSM0 State */
7232 uint64_t nsm0 : 13;
7233 uint64_t nsm1 : 13;
7234 uint64_t psm0 : 15;
7235 uint64_t psm1 : 15;
7236 uint64_t reserved_56_63 : 8;
7254 uint64_t u64;
7257 uint64_t reserved_51_63 : 13;
7258 uint64_t ld_cmd : 2; /**< The load command sent wit hthe read.
7261 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
7263 uint64_t rd_addr : 48; /**< The address to be read from. Whenever the LSB of
7273 uint64_t rd_addr : 48;
7274 uint64_t iobit : 1;
7275 uint64_t ld_cmd : 2;
7276 uint64_t reserved_51_63 : 13;
7295 uint64_t u64;
7298 uint64_t rd_data : 64; /**< The read data. */
7300 uint64_t rd_data : 64;
7323 uint64_t u64;
7326 uint64_t reserved_49_63 : 15;
7327 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
7329 uint64_t wr_addr : 46; /**< The address that will be written to when the
7338 uint64_t reserved_0_1 : 2;
7340 uint64_t reserved_0_1 : 2;
7341 uint64_t wr_addr : 46;
7342 uint64_t iobit : 1;
7343 uint64_t reserved_49_63 : 15;
7362 uint64_t u64;
7365 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this
7369 uint64_t wr_data : 64;
7387 uint64_t u64;
7390 uint64_t reserved_8_63 : 56;
7391 uint64_t wr_mask : 8; /**< The data to be written. When a bit is '0'
7394 uint64_t wr_mask : 8;
7395 uint64_t reserved_8_63 : 56;
7418 uint64_t u64;
7421 uint64_t reserved_32_63 : 32;
7422 uint64_t time : 32; /**< Time to wait in core clocks to wait for a
7428 uint64_t time : 32;
7429 uint64_t reserved_32_63 : 32;