Lines Matching refs:timer
2487 * Thresholds for DMA count and timer interrupts for DMA0.
2493 uint64_t time : 32; /**< Whenever the DMA_CNT0 timer exceeds
2495 The DMA_CNT0 timer increments every core clock
2517 * Thresholds for DMA count and timer interrupts for DMA1.
2523 uint64_t time : 32; /**< Whenever the DMA_CNT1 timer exceeds
2525 The DMA_CNT1 timer increments every core clock
4659 DMA_CNT1 timer increments every core clock. When
4660 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
4662 clears the DMA_CNT1 timer. */
4664 DMA_CNT0 timer increments every core clock. When
4665 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
4667 clears the DMA_CNT0 timer. */
4854 DMA_CNT1 timer increments every core clock. When
4855 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
4857 clears the DMA_CNT1 timer. */
4859 DMA_CNT0 timer increments every core clock. When
4860 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
4862 clears the DMA_CNT0 timer. */
5042 DMA_CNT1 timer increments every core clock. When
5043 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
5045 clears the DMA_CNT1 timer. */
5047 DMA_CNT0 timer increments every core clock. When
5048 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
5050 clears the DMA_CNT0 timer. */
5400 uint64_t timer : 10; /**< When the NPEI starts a PP to PCIe write it waits
5406 uint64_t timer : 10;
6065 uint64_t timer : 22; /**< Timer incremented every 1024 core clocks
6083 uint64_t timer : 22;
7415 * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#.