Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_MPI_CFG_FUNC(void)
67 static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
84 static inline uint64_t CVMX_MPI_STS_FUNC(void)
95 static inline uint64_t CVMX_MPI_TX_FUNC(void)
120 uint64_t u64;
123 uint64_t reserved_29_63 : 35;
124 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
126 uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS
129 uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS
132 uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS
135 uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS
138 uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
141 uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
145 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
147 uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
149 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
151 uint64_t int_ena : 1; /**< If 0, polling is required | NS
153 uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
155 uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
161 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
165 uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
167 uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
175 uint64_t enable : 1;
176 uint64_t idlelo : 1;
177 uint64_t clk_cont : 1;
178 uint64_t wireor : 1;
179 uint64_t lsbfirst : 1;
180 uint64_t int_ena : 1;
181 uint64_t csena : 1;
182 uint64_t cshi : 1;
183 uint64_t idleclks : 2;
184 uint64_t tritx : 1;
185 uint64_t cslate : 1;
186 uint64_t csena0 : 1;
187 uint64_t csena1 : 1;
188 uint64_t csena2 : 1;
189 uint64_t csena3 : 1;
190 uint64_t clkdiv : 13;
191 uint64_t reserved_29_63 : 35;
196 uint64_t reserved_29_63 : 35;
197 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
199 uint64_t reserved_12_15 : 4;
200 uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
203 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
207 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
209 uint64_t cshi : 1; /**< If 0, CS is low asserted
211 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
213 uint64_t int_ena : 1; /**< If 0, polling is required
215 uint64_t lsbfirst : 1; /**< If 0, shift MSB first
217 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
223 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
227 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
229 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
232 uint64_t enable : 1;
233 uint64_t idlelo : 1;
234 uint64_t clk_cont : 1;
235 uint64_t wireor : 1;
236 uint64_t lsbfirst : 1;
237 uint64_t int_ena : 1;
238 uint64_t csena : 1;
239 uint64_t cshi : 1;
240 uint64_t idleclks : 2;
241 uint64_t tritx : 1;
242 uint64_t cslate : 1;
243 uint64_t reserved_12_15 : 4;
244 uint64_t clkdiv : 13;
245 uint64_t reserved_29_63 : 35;
250 uint64_t reserved_29_63 : 35;
251 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
253 uint64_t reserved_11_15 : 5;
254 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
258 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
260 uint64_t cshi : 1; /**< If 0, CS is low asserted
262 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
264 uint64_t int_ena : 1; /**< If 0, polling is required
266 uint64_t lsbfirst : 1; /**< If 0, shift MSB first
268 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
274 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
278 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
280 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
283 uint64_t enable : 1;
284 uint64_t idlelo : 1;
285 uint64_t clk_cont : 1;
286 uint64_t wireor : 1;
287 uint64_t lsbfirst : 1;
288 uint64_t int_ena : 1;
289 uint64_t csena : 1;
290 uint64_t cshi : 1;
291 uint64_t idleclks : 2;
292 uint64_t tritx : 1;
293 uint64_t reserved_11_15 : 5;
294 uint64_t clkdiv : 13;
295 uint64_t reserved_29_63 : 35;
301 uint64_t reserved_29_63 : 35;
302 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
304 uint64_t reserved_14_15 : 2;
305 uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS
308 uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS
311 uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
314 uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
318 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
320 uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
322 uint64_t reserved_6_6 : 1;
323 uint64_t int_ena : 1; /**< If 0, polling is required | NS
325 uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
327 uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
333 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
337 uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
339 uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
347 uint64_t enable : 1;
348 uint64_t idlelo : 1;
349 uint64_t clk_cont : 1;
350 uint64_t wireor : 1;
351 uint64_t lsbfirst : 1;
352 uint64_t int_ena : 1;
353 uint64_t reserved_6_6 : 1;
354 uint64_t cshi : 1;
355 uint64_t idleclks : 2;
356 uint64_t tritx : 1;
357 uint64_t cslate : 1;
358 uint64_t csena0 : 1;
359 uint64_t csena1 : 1;
360 uint64_t reserved_14_15 : 2;
361 uint64_t clkdiv : 13;
362 uint64_t reserved_29_63 : 35;
367 uint64_t reserved_29_63 : 35;
368 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
370 uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS
373 uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS
376 uint64_t reserved_12_13 : 2;
377 uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
380 uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
384 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
386 uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
388 uint64_t reserved_6_6 : 1;
389 uint64_t int_ena : 1; /**< If 0, polling is required | NS
391 uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
393 uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
399 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
403 uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
405 uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
413 uint64_t enable : 1;
414 uint64_t idlelo : 1;
415 uint64_t clk_cont : 1;
416 uint64_t wireor : 1;
417 uint64_t lsbfirst : 1;
418 uint64_t int_ena : 1;
419 uint64_t reserved_6_6 : 1;
420 uint64_t cshi : 1;
421 uint64_t idleclks : 2;
422 uint64_t tritx : 1;
423 uint64_t cslate : 1;
424 uint64_t reserved_12_13 : 2;
425 uint64_t csena2 : 1;
426 uint64_t csena3 : 1;
427 uint64_t clkdiv : 13;
428 uint64_t reserved_29_63 : 35;
439 uint64_t u64;
442 uint64_t reserved_8_63 : 56;
443 uint64_t data : 8; /**< Data to transmit/received | NS */
445 uint64_t data : 8;
446 uint64_t reserved_8_63 : 56;
462 uint64_t u64;
465 uint64_t reserved_13_63 : 51;
466 uint64_t rxnum : 5; /**< Number of bytes written for transaction | NS */
467 uint64_t reserved_1_7 : 7;
468 uint64_t busy : 1; /**< If 0, no MPI transaction in progress | NS
471 uint64_t busy : 1;
472 uint64_t reserved_1_7 : 7;
473 uint64_t rxnum : 5;
474 uint64_t reserved_13_63 : 51;
490 uint64_t u64;
493 uint64_t reserved_22_63 : 42;
494 uint64_t csid : 2; /**< Which CS to assert for this transaction | NS */
495 uint64_t reserved_17_19 : 3;
496 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS
498 uint64_t reserved_13_15 : 3;
499 uint64_t txnum : 5; /**< Number of bytes to transmit | NS */
500 uint64_t reserved_5_7 : 3;
501 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */
503 uint64_t totnum : 5;
504 uint64_t reserved_5_7 : 3;
505 uint64_t txnum : 5;
506 uint64_t reserved_13_15 : 3;
507 uint64_t leavecs : 1;
508 uint64_t reserved_17_19 : 3;
509 uint64_t csid : 2;
510 uint64_t reserved_22_63 : 42;
515 uint64_t reserved_17_63 : 47;
516 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done
518 uint64_t reserved_13_15 : 3;
519 uint64_t txnum : 5; /**< Number of bytes to transmit */
520 uint64_t reserved_5_7 : 3;
521 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */
523 uint64_t totnum : 5;
524 uint64_t reserved_5_7 : 3;
525 uint64_t txnum : 5;
526 uint64_t reserved_13_15 : 3;
527 uint64_t leavecs : 1;
528 uint64_t reserved_17_63 : 47;
535 uint64_t reserved_21_63 : 43;
536 uint64_t csid : 1; /**< Which CS to assert for this transaction | NS */
537 uint64_t reserved_17_19 : 3;
538 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS
540 uint64_t reserved_13_15 : 3;
541 uint64_t txnum : 5; /**< Number of bytes to transmit | NS */
542 uint64_t reserved_5_7 : 3;
543 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */
545 uint64_t totnum : 5;
546 uint64_t reserved_5_7 : 3;
547 uint64_t txnum : 5;
548 uint64_t reserved_13_15 : 3;
549 uint64_t leavecs : 1;
550 uint64_t reserved_17_19 : 3;
551 uint64_t csid : 1;
552 uint64_t reserved_21_63 : 43;