Lines Matching refs:uint64_t
56 static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
72 static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
88 static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
104 static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
120 static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
136 static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
152 static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
168 static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
184 static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
200 static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
216 static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
232 static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
248 static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
264 static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
278 static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
301 uint64_t u64;
304 uint64_t reserved_6_63 : 58;
305 uint64_t opfdat : 1; /**< Bist Results for AGO OPF Buffer RAM
308 uint64_t mrgdat : 1; /**< Bist Results for AGI MRG Buffer RAM
311 uint64_t mrqdat : 1; /**< Bist Results for NBR CSR RdReq RAM
314 uint64_t ipfdat : 1; /**< Bist Results for MIX Inbound Packet RAM
317 uint64_t irfdat : 1; /**< Bist Results for MIX I-Ring Entry RAM
320 uint64_t orfdat : 1; /**< Bist Results for MIX O-Ring Entry RAM
324 uint64_t orfdat : 1;
325 uint64_t irfdat : 1;
326 uint64_t ipfdat : 1;
327 uint64_t mrqdat : 1;
328 uint64_t mrgdat : 1;
329 uint64_t opfdat : 1;
330 uint64_t reserved_6_63 : 58;
335 uint64_t reserved_4_63 : 60;
336 uint64_t mrqdat : 1; /**< Bist Results for NBR CSR RdReq RAM
339 uint64_t ipfdat : 1; /**< Bist Results for MIX Inbound Packet RAM
342 uint64_t irfdat : 1; /**< Bist Results for MIX I-Ring Entry RAM
345 uint64_t orfdat : 1; /**< Bist Results for MIX O-Ring Entry RAM
349 uint64_t orfdat : 1;
350 uint64_t irfdat : 1;
351 uint64_t ipfdat : 1;
352 uint64_t mrqdat : 1;
353 uint64_t reserved_4_63 : 60;
378 uint64_t u64;
381 uint64_t reserved_12_63 : 52;
382 uint64_t ts_thresh : 4; /**< TimeStamp Interrupt Threshold
390 uint64_t crc_strip : 1; /**< HW CRC Strip Enable
397 uint64_t busy : 1; /**< MIX Busy Status bit
408 uint64_t en : 1; /**< MIX Enable bit
413 uint64_t reset : 1; /**< MIX Soft Reset
439 uint64_t lendian : 1; /**< Packet Little Endian Mode
443 uint64_t nbtarb : 1; /**< MIX CB-Request Arbitration Mode.
452 uint64_t mrq_hwm : 2; /**< MIX CB-Request FIFO Programmable High Water Mark.
462 uint64_t mrq_hwm : 2;
463 uint64_t nbtarb : 1;
464 uint64_t lendian : 1;
465 uint64_t reset : 1;
466 uint64_t en : 1;
467 uint64_t busy : 1;
468 uint64_t crc_strip : 1;
469 uint64_t ts_thresh : 4;
470 uint64_t reserved_12_63 : 52;
475 uint64_t reserved_8_63 : 56;
476 uint64_t crc_strip : 1; /**< HW CRC Strip Enable
483 uint64_t busy : 1; /**< MIX Busy Status bit
494 uint64_t en : 1; /**< MIX Enable bit
499 uint64_t reset : 1; /**< MIX Soft Reset
525 uint64_t lendian : 1; /**< Packet Little Endian Mode
529 uint64_t nbtarb : 1; /**< MIX CB-Request Arbitration Mode.
538 uint64_t mrq_hwm : 2; /**< MIX CB-Request FIFO Programmable High Water Mark.
548 uint64_t mrq_hwm : 2;
549 uint64_t nbtarb : 1;
550 uint64_t lendian : 1;
551 uint64_t reset : 1;
552 uint64_t en : 1;
553 uint64_t busy : 1;
554 uint64_t crc_strip : 1;
555 uint64_t reserved_8_63 : 56;
580 uint64_t u64;
583 uint64_t reserved_8_63 : 56;
584 uint64_t tsena : 1; /**< TimeStamp Interrupt Enable
589 uint64_t orunena : 1; /**< ORCNT UnderFlow Detected Enable
594 uint64_t irunena : 1; /**< IRCNT UnderFlow Interrupt Enable
599 uint64_t data_drpena : 1; /**< Data was dropped due to RX FIFO full Interrupt
604 uint64_t ithena : 1; /**< Inbound Ring Threshold Exceeded Interrupt Enable
609 uint64_t othena : 1; /**< Outbound Ring Threshold Exceeded Interrupt Enable
614 uint64_t ivfena : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected
619 uint64_t ovfena : 1; /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
625 uint64_t ovfena : 1;
626 uint64_t ivfena : 1;
627 uint64_t othena : 1;
628 uint64_t ithena : 1;
629 uint64_t data_drpena : 1;
630 uint64_t irunena : 1;
631 uint64_t orunena : 1;
632 uint64_t tsena : 1;
633 uint64_t reserved_8_63 : 56;
638 uint64_t reserved_7_63 : 57;
639 uint64_t orunena : 1; /**< ORCNT UnderFlow Detected
644 uint64_t irunena : 1; /**< IRCNT UnderFlow Interrupt Enable
649 uint64_t data_drpena : 1; /**< Data was dropped due to RX FIFO full Interrupt
654 uint64_t ithena : 1; /**< Inbound Ring Threshold Exceeded Interrupt Enable
659 uint64_t othena : 1; /**< Outbound Ring Threshold Exceeded Interrupt Enable
664 uint64_t ivfena : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected
669 uint64_t ovfena : 1; /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
675 uint64_t ovfena : 1;
676 uint64_t ivfena : 1;
677 uint64_t othena : 1;
678 uint64_t ithena : 1;
679 uint64_t data_drpena : 1;
680 uint64_t irunena : 1;
681 uint64_t orunena : 1;
682 uint64_t reserved_7_63 : 57;
707 uint64_t u64;
710 uint64_t reserved_20_63 : 44;
711 uint64_t ircnt : 20; /**< Pending \# of I-Ring Packets.
728 uint64_t ircnt : 20;
729 uint64_t reserved_20_63 : 44;
755 uint64_t u64;
758 uint64_t reserved_40_63 : 24;
759 uint64_t ibplwm : 20; /**< I-Ring BackPressure Low Water Mark Threshold.
767 uint64_t irhwm : 20; /**< I-Ring Entry High Water Mark Threshold.
775 uint64_t irhwm : 20;
776 uint64_t ibplwm : 20;
777 uint64_t reserved_40_63 : 24;
803 uint64_t u64;
806 uint64_t reserved_60_63 : 4;
807 uint64_t isize : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
811 uint64_t ibase : 37; /**< Represents the 8B-aligned base address of the first
815 uint64_t reserved_0_2 : 3;
817 uint64_t reserved_0_2 : 3;
818 uint64_t ibase : 37;
819 uint64_t isize : 20;
820 uint64_t reserved_60_63 : 4;
825 uint64_t reserved_60_63 : 4;
826 uint64_t isize : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
830 uint64_t reserved_36_39 : 4;
831 uint64_t ibase : 33; /**< Represents the 8B-aligned base address of the first
835 uint64_t reserved_0_2 : 3;
837 uint64_t reserved_0_2 : 3;
838 uint64_t ibase : 33;
839 uint64_t reserved_36_39 : 4;
840 uint64_t isize : 20;
841 uint64_t reserved_60_63 : 4;
866 uint64_t u64;
869 uint64_t reserved_52_63 : 12;
870 uint64_t itlptr : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring
876 uint64_t reserved_20_31 : 12;
877 uint64_t idbell : 20; /**< Represents the cumulative total of pending
890 uint64_t idbell : 20;
891 uint64_t reserved_20_31 : 12;
892 uint64_t itlptr : 20;
893 uint64_t reserved_52_63 : 12;
919 uint64_t u64;
922 uint64_t reserved_8_63 : 56;
923 uint64_t ts : 1; /**< TimeStamp Interrupt
931 uint64_t orun : 1; /**< ORCNT UnderFlow Detected
940 uint64_t irun : 1; /**< IRCNT UnderFlow Detected
949 uint64_t data_drp : 1; /**< Data was dropped due to RX FIFO full
955 uint64_t irthresh : 1; /**< Inbound Ring Packet Threshold Exceeded
964 uint64_t orthresh : 1; /**< Outbound Ring Packet Threshold Exceeded
973 uint64_t idblovf : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected
998 uint64_t odblovf : 1; /**< Outbound DoorBell(ODBELL) Overflow Detected
1020 uint64_t odblovf : 1;
1021 uint64_t idblovf : 1;
1022 uint64_t orthresh : 1;
1023 uint64_t irthresh : 1;
1024 uint64_t data_drp : 1;
1025 uint64_t irun : 1;
1026 uint64_t orun : 1;
1027 uint64_t ts : 1;
1028 uint64_t reserved_8_63 : 56;
1033 uint64_t reserved_7_63 : 57;
1034 uint64_t orun : 1; /**< ORCNT UnderFlow Detected
1043 uint64_t irun : 1; /**< IRCNT UnderFlow Detected
1052 uint64_t data_drp : 1; /**< Data was dropped due to RX FIFO full
1058 uint64_t irthresh : 1; /**< Inbound Ring Packet Threshold Exceeded
1067 uint64_t orthresh : 1; /**< Outbound Ring Packet Threshold Exceeded
1076 uint64_t idblovf : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected
1101 uint64_t odblovf : 1; /**< Outbound DoorBell(ODBELL) Overflow Detected
1123 uint64_t odblovf : 1;
1124 uint64_t idblovf : 1;
1125 uint64_t orthresh : 1;
1126 uint64_t irthresh : 1;
1127 uint64_t data_drp : 1;
1128 uint64_t irun : 1;
1129 uint64_t orun : 1;
1130 uint64_t reserved_7_63 : 57;
1155 uint64_t u64;
1158 uint64_t reserved_20_63 : 44;
1159 uint64_t orcnt : 20; /**< Pending \# of O-Ring Packets.
1173 uint64_t orcnt : 20;
1174 uint64_t reserved_20_63 : 44;
1200 uint64_t u64;
1203 uint64_t reserved_20_63 : 44;
1204 uint64_t orhwm : 20; /**< O-Ring Entry High Water Mark Threshold.
1212 uint64_t orhwm : 20;
1213 uint64_t reserved_20_63 : 44;
1239 uint64_t u64;
1242 uint64_t reserved_60_63 : 4;
1243 uint64_t osize : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
1247 uint64_t obase : 37; /**< Represents the 8B-aligned base address of the first
1251 uint64_t reserved_0_2 : 3;
1253 uint64_t reserved_0_2 : 3;
1254 uint64_t obase : 37;
1255 uint64_t osize : 20;
1256 uint64_t reserved_60_63 : 4;
1261 uint64_t reserved_60_63 : 4;
1262 uint64_t osize : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
1266 uint64_t reserved_36_39 : 4;
1267 uint64_t obase : 33; /**< Represents the 8B-aligned base address of the first
1271 uint64_t reserved_0_2 : 3;
1273 uint64_t reserved_0_2 : 3;
1274 uint64_t obase : 33;
1275 uint64_t reserved_36_39 : 4;
1276 uint64_t osize : 20;
1277 uint64_t reserved_60_63 : 4;
1302 uint64_t u64;
1305 uint64_t reserved_52_63 : 12;
1306 uint64_t otlptr : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring
1313 uint64_t reserved_20_31 : 12;
1314 uint64_t odbell : 20; /**< Represents the cumulative total of pending
1328 uint64_t odbell : 20;
1329 uint64_t reserved_20_31 : 12;
1330 uint64_t otlptr : 20;
1331 uint64_t reserved_52_63 : 12;
1356 uint64_t u64;
1359 uint64_t reserved_52_63 : 12;
1360 uint64_t iremcnt : 20; /**< Remaining I-Ring Buffer Count
1373 uint64_t reserved_20_31 : 12;
1374 uint64_t oremcnt : 20; /**< Remaining O-Ring Buffer Count
1388 uint64_t oremcnt : 20;
1389 uint64_t reserved_20_31 : 12;
1390 uint64_t iremcnt : 20;
1391 uint64_t reserved_52_63 : 12;
1431 uint64_t u64;
1434 uint64_t reserved_21_63 : 43;
1435 uint64_t tsavl : 5; /**< # of MIX TimeStamp Entries Available for use
1439 uint64_t reserved_13_15 : 3;
1440 uint64_t tstot : 5; /**< # of pending MIX TimeStamp Requests in-flight
1443 uint64_t reserved_5_7 : 3;
1444 uint64_t tscnt : 5; /**< # of pending MIX TimeStamp Interrupts
1448 uint64_t tscnt : 5;
1449 uint64_t reserved_5_7 : 3;
1450 uint64_t tstot : 5;
1451 uint64_t reserved_13_15 : 3;
1452 uint64_t tsavl : 5;
1453 uint64_t reserved_21_63 : 43;
1474 uint64_t u64;
1477 uint64_t tstamp : 64; /**< MIX TimeStamp Value
1512 uint64_t tstamp : 64;