Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_LED_BLINK_FUNC(void)
68 static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
79 static inline uint64_t CVMX_LED_CYLON_FUNC(void)
90 static inline uint64_t CVMX_LED_DBG_FUNC(void)
101 static inline uint64_t CVMX_LED_EN_FUNC(void)
112 static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
123 static inline uint64_t CVMX_LED_PRT_FUNC(void)
134 static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
144 static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
157 static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
170 static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
183 static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
196 static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
216 uint64_t u64;
219 uint64_t reserved_8_63 : 56;
220 uint64_t rate : 8; /**< LED Blink rate in led_latch clks
223 uint64_t rate : 8;
224 uint64_t reserved_8_63 : 56;
250 uint64_t u64;
253 uint64_t reserved_7_63 : 57;
254 uint64_t phase : 7; /**< Number of 64 eclks in order to create the led_clk */
256 uint64_t phase : 7;
257 uint64_t reserved_7_63 : 57;
276 uint64_t u64;
279 uint64_t reserved_16_63 : 48;
280 uint64_t rate : 16; /**< LED Cylon Effect when RATE!=0
283 uint64_t rate : 16;
284 uint64_t reserved_16_63 : 48;
303 uint64_t u64;
306 uint64_t reserved_1_63 : 63;
307 uint64_t dbg_en : 1; /**< Add Debug Port Data to the LED shift chain
310 uint64_t dbg_en : 1;
311 uint64_t reserved_1_63 : 63;
359 uint64_t u64;
362 uint64_t reserved_1_63 : 63;
363 uint64_t en : 1; /**< Enable the LED interface shift-chain */
365 uint64_t en : 1;
366 uint64_t reserved_1_63 : 63;
385 uint64_t u64;
388 uint64_t reserved_1_63 : 63;
389 uint64_t polarity : 1; /**< LED active polarity
393 uint64_t polarity : 1;
394 uint64_t reserved_1_63 : 63;
418 uint64_t u64;
421 uint64_t reserved_8_63 : 56;
422 uint64_t prt_en : 8; /**< Which ports are enabled to display status
428 uint64_t prt_en : 8;
429 uint64_t reserved_8_63 : 56;
454 uint64_t u64;
457 uint64_t reserved_4_63 : 60;
458 uint64_t format : 4; /**< Port Status Information for each enabled port in
471 uint64_t format : 4;
472 uint64_t reserved_4_63 : 60;
491 uint64_t u64;
494 uint64_t reserved_6_63 : 58;
495 uint64_t status : 6; /**< Bits that software can set to be added to the
503 uint64_t status : 6;
504 uint64_t reserved_6_63 : 58;
523 uint64_t u64;
526 uint64_t reserved_6_63 : 58;
527 uint64_t cnt : 6; /**< Number of bits of user-defined data to include in
530 uint64_t cnt : 6;
531 uint64_t reserved_6_63 : 58;
555 uint64_t u64;
558 uint64_t reserved_32_63 : 32;
559 uint64_t dat : 32; /**< Header or trailer UDD data to be displayed on
563 uint64_t dat : 32;
564 uint64_t reserved_32_63 : 32;
583 uint64_t u64;
586 uint64_t reserved_32_63 : 32;
587 uint64_t clr : 32; /**< Bitwise clear for the Header or trailer UDD data to
590 uint64_t clr : 32;
591 uint64_t reserved_32_63 : 32;
610 uint64_t u64;
613 uint64_t reserved_32_63 : 32;
614 uint64_t set : 32; /**< Bitwise set for the Header or trailer UDD data to
617 uint64_t set : 32;
618 uint64_t reserved_32_63 : 32;