Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_L2T_ERR_FUNC(void)
75 uint64_t u64;
78 uint64_t reserved_29_63 : 35;
79 uint64_t fadru : 1; /**< Failing L2 Tag Upper Address Bit (Index[10])
83 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
84 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
96 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
97 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
108 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
113 uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index)
117 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
133 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
138 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
144 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
148 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
152 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
156 uint64_t ecc_ena : 1;
157 uint64_t sec_intena : 1;
158 uint64_t ded_intena : 1;
159 uint64_t sec_err : 1;
160 uint64_t ded_err : 1;
161 uint64_t fsyn : 6;
162 uint64_t fadr : 10;
163 uint64_t fset : 3;
164 uint64_t lckerr : 1;
165 uint64_t lck_intena : 1;
166 uint64_t lckerr2 : 1;
167 uint64_t lck_intena2 : 1;
168 uint64_t fadru : 1;
169 uint64_t reserved_29_63 : 35;
174 uint64_t reserved_28_63 : 36;
175 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
176 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
188 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
189 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
201 uint64_t reserved_23_23 : 1;
202 uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4)
207 uint64_t reserved_19_20 : 2;
208 uint64_t fadr : 8; /**< Failing L2 Tag Store Index (8-bit)
212 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
228 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
233 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
239 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
243 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
247 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
251 uint64_t ecc_ena : 1;
252 uint64_t sec_intena : 1;
253 uint64_t ded_intena : 1;
254 uint64_t sec_err : 1;
255 uint64_t ded_err : 1;
256 uint64_t fsyn : 6;
257 uint64_t fadr : 8;
258 uint64_t reserved_19_20 : 2;
259 uint64_t fset : 2;
260 uint64_t reserved_23_23 : 1;
261 uint64_t lckerr : 1;
262 uint64_t lck_intena : 1;
263 uint64_t lckerr2 : 1;
264 uint64_t lck_intena2 : 1;
265 uint64_t reserved_28_63 : 36;
270 uint64_t reserved_28_63 : 36;
271 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
272 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
284 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
285 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
296 uint64_t reserved_23_23 : 1;
297 uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4)
302 uint64_t reserved_20_20 : 1;
303 uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index)
307 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
323 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
328 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
334 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
338 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
342 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
346 uint64_t ecc_ena : 1;
347 uint64_t sec_intena : 1;
348 uint64_t ded_intena : 1;
349 uint64_t sec_err : 1;
350 uint64_t ded_err : 1;
351 uint64_t fsyn : 6;
352 uint64_t fadr : 9;
353 uint64_t reserved_20_20 : 1;
354 uint64_t fset : 2;
355 uint64_t reserved_23_23 : 1;
356 uint64_t lckerr : 1;
357 uint64_t lck_intena : 1;
358 uint64_t lckerr2 : 1;
359 uint64_t lck_intena2 : 1;
360 uint64_t reserved_28_63 : 36;
365 uint64_t reserved_28_63 : 36;
366 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
367 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
379 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
380 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
391 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
396 uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index)
400 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
416 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
421 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
427 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
431 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
435 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
439 uint64_t ecc_ena : 1;
440 uint64_t sec_intena : 1;
441 uint64_t ded_intena : 1;
442 uint64_t sec_err : 1;
443 uint64_t ded_err : 1;
444 uint64_t fsyn : 6;
445 uint64_t fadr : 10;
446 uint64_t fset : 3;
447 uint64_t lckerr : 1;
448 uint64_t lck_intena : 1;
449 uint64_t lckerr2 : 1;
450 uint64_t lck_intena2 : 1;
451 uint64_t reserved_28_63 : 36;
457 uint64_t reserved_28_63 : 36;
458 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
459 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
471 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
472 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
483 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
488 uint64_t reserved_18_20 : 3;
489 uint64_t fadr : 7; /**< Failing L2 Tag Address (7-bit Index)
493 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
509 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
514 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
520 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
524 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
528 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
532 uint64_t ecc_ena : 1;
533 uint64_t sec_intena : 1;
534 uint64_t ded_intena : 1;
535 uint64_t sec_err : 1;
536 uint64_t ded_err : 1;
537 uint64_t fsyn : 6;
538 uint64_t fadr : 7;
539 uint64_t reserved_18_20 : 3;
540 uint64_t fset : 3;
541 uint64_t lckerr : 1;
542 uint64_t lck_intena : 1;
543 uint64_t lckerr2 : 1;
544 uint64_t lck_intena2 : 1;
545 uint64_t reserved_28_63 : 36;
550 uint64_t reserved_28_63 : 36;
551 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */
552 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n
564 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */
565 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of
576 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8)
581 uint64_t reserved_20_20 : 1;
582 uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index)
586 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
602 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED)
607 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC)
613 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt
617 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
621 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable
625 uint64_t ecc_ena : 1;
626 uint64_t sec_intena : 1;
627 uint64_t ded_intena : 1;
628 uint64_t sec_err : 1;
629 uint64_t ded_err : 1;
630 uint64_t fsyn : 6;
631 uint64_t fadr : 9;
632 uint64_t reserved_20_20 : 1;
633 uint64_t fset : 3;
634 uint64_t lckerr : 1;
635 uint64_t lck_intena : 1;
636 uint64_t lckerr2 : 1;
637 uint64_t lck_intena2 : 1;
638 uint64_t reserved_28_63 : 36;