Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_ILK_BIST_SUM_FUNC(void)
68 static inline uint64_t CVMX_ILK_GBL_CFG_FUNC(void)
79 static inline uint64_t CVMX_ILK_GBL_INT_FUNC(void)
90 static inline uint64_t CVMX_ILK_GBL_INT_EN_FUNC(void)
101 static inline uint64_t CVMX_ILK_INT_SUM_FUNC(void)
112 static inline uint64_t CVMX_ILK_LNE_DBG_FUNC(void)
123 static inline uint64_t CVMX_ILK_LNE_STS_MSG_FUNC(void)
134 static inline uint64_t CVMX_ILK_RXF_IDX_PMAP_FUNC(void)
145 static inline uint64_t CVMX_ILK_RXF_MEM_PMAP_FUNC(void)
155 static inline uint64_t CVMX_ILK_RXX_CFG0(unsigned long offset)
166 static inline uint64_t CVMX_ILK_RXX_CFG1(unsigned long offset)
177 static inline uint64_t CVMX_ILK_RXX_FLOW_CTL0(unsigned long offset)
188 static inline uint64_t CVMX_ILK_RXX_FLOW_CTL1(unsigned long offset)
199 static inline uint64_t CVMX_ILK_RXX_IDX_CAL(unsigned long offset)
210 static inline uint64_t CVMX_ILK_RXX_IDX_STAT0(unsigned long offset)
221 static inline uint64_t CVMX_ILK_RXX_IDX_STAT1(unsigned long offset)
232 static inline uint64_t CVMX_ILK_RXX_INT(unsigned long offset)
243 static inline uint64_t CVMX_ILK_RXX_INT_EN(unsigned long offset)
254 static inline uint64_t CVMX_ILK_RXX_JABBER(unsigned long offset)
265 static inline uint64_t CVMX_ILK_RXX_MEM_CAL0(unsigned long offset)
276 static inline uint64_t CVMX_ILK_RXX_MEM_CAL1(unsigned long offset)
287 static inline uint64_t CVMX_ILK_RXX_MEM_STAT0(unsigned long offset)
298 static inline uint64_t CVMX_ILK_RXX_MEM_STAT1(unsigned long offset)
309 static inline uint64_t CVMX_ILK_RXX_RID(unsigned long offset)
320 static inline uint64_t CVMX_ILK_RXX_STAT0(unsigned long offset)
331 static inline uint64_t CVMX_ILK_RXX_STAT1(unsigned long offset)
342 static inline uint64_t CVMX_ILK_RXX_STAT2(unsigned long offset)
353 static inline uint64_t CVMX_ILK_RXX_STAT3(unsigned long offset)
364 static inline uint64_t CVMX_ILK_RXX_STAT4(unsigned long offset)
375 static inline uint64_t CVMX_ILK_RXX_STAT5(unsigned long offset)
386 static inline uint64_t CVMX_ILK_RXX_STAT6(unsigned long offset)
397 static inline uint64_t CVMX_ILK_RXX_STAT7(unsigned long offset)
408 static inline uint64_t CVMX_ILK_RXX_STAT8(unsigned long offset)
419 static inline uint64_t CVMX_ILK_RXX_STAT9(unsigned long offset)
430 static inline uint64_t CVMX_ILK_RX_LNEX_CFG(unsigned long offset)
441 static inline uint64_t CVMX_ILK_RX_LNEX_INT(unsigned long offset)
452 static inline uint64_t CVMX_ILK_RX_LNEX_INT_EN(unsigned long offset)
463 static inline uint64_t CVMX_ILK_RX_LNEX_STAT0(unsigned long offset)
474 static inline uint64_t CVMX_ILK_RX_LNEX_STAT1(unsigned long offset)
485 static inline uint64_t CVMX_ILK_RX_LNEX_STAT2(unsigned long offset)
496 static inline uint64_t CVMX_ILK_RX_LNEX_STAT3(unsigned long offset)
507 static inline uint64_t CVMX_ILK_RX_LNEX_STAT4(unsigned long offset)
518 static inline uint64_t CVMX_ILK_RX_LNEX_STAT5(unsigned long offset)
529 static inline uint64_t CVMX_ILK_RX_LNEX_STAT6(unsigned long offset)
540 static inline uint64_t CVMX_ILK_RX_LNEX_STAT7(unsigned long offset)
551 static inline uint64_t CVMX_ILK_RX_LNEX_STAT8(unsigned long offset)
562 static inline uint64_t CVMX_ILK_RX_LNEX_STAT9(unsigned long offset)
574 static inline uint64_t CVMX_ILK_SER_CFG_FUNC(void)
584 static inline uint64_t CVMX_ILK_TXX_CFG0(unsigned long offset)
595 static inline uint64_t CVMX_ILK_TXX_CFG1(unsigned long offset)
606 static inline uint64_t CVMX_ILK_TXX_DBG(unsigned long offset)
617 static inline uint64_t CVMX_ILK_TXX_FLOW_CTL0(unsigned long offset)
628 static inline uint64_t CVMX_ILK_TXX_FLOW_CTL1(unsigned long offset)
639 static inline uint64_t CVMX_ILK_TXX_IDX_CAL(unsigned long offset)
650 static inline uint64_t CVMX_ILK_TXX_IDX_PMAP(unsigned long offset)
661 static inline uint64_t CVMX_ILK_TXX_IDX_STAT0(unsigned long offset)
672 static inline uint64_t CVMX_ILK_TXX_IDX_STAT1(unsigned long offset)
683 static inline uint64_t CVMX_ILK_TXX_INT(unsigned long offset)
694 static inline uint64_t CVMX_ILK_TXX_INT_EN(unsigned long offset)
705 static inline uint64_t CVMX_ILK_TXX_MEM_CAL0(unsigned long offset)
716 static inline uint64_t CVMX_ILK_TXX_MEM_CAL1(unsigned long offset)
727 static inline uint64_t CVMX_ILK_TXX_MEM_PMAP(unsigned long offset)
738 static inline uint64_t CVMX_ILK_TXX_MEM_STAT0(unsigned long offset)
749 static inline uint64_t CVMX_ILK_TXX_MEM_STAT1(unsigned long offset)
760 static inline uint64_t CVMX_ILK_TXX_PIPE(unsigned long offset)
771 static inline uint64_t CVMX_ILK_TXX_RMATCH(unsigned long offset)
786 uint64_t u64;
789 uint64_t reserved_58_63 : 6;
790 uint64_t rxf_x2p1 : 1; /**< Bist status of rxf.x2p_fif_mem1 */
791 uint64_t rxf_x2p0 : 1; /**< Bist status of rxf.x2p_fif_mem0 */
792 uint64_t rxf_pmap : 1; /**< Bist status of rxf.rx_map_mem */
793 uint64_t rxf_mem2 : 1; /**< Bist status of rxf.rx_fif_mem2 */
794 uint64_t rxf_mem1 : 1; /**< Bist status of rxf.rx_fif_mem1 */
795 uint64_t rxf_mem0 : 1; /**< Bist status of rxf.rx_fif_mem0 */
796 uint64_t reserved_36_51 : 16;
797 uint64_t rle7_dsk1 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */
798 uint64_t rle7_dsk0 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */
799 uint64_t rle6_dsk1 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */
800 uint64_t rle6_dsk0 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */
801 uint64_t rle5_dsk1 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */
802 uint64_t rle5_dsk0 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */
803 uint64_t rle4_dsk1 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */
804 uint64_t rle4_dsk0 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */
805 uint64_t rle3_dsk1 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */
806 uint64_t rle3_dsk0 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */
807 uint64_t rle2_dsk1 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */
808 uint64_t rle2_dsk0 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */
809 uint64_t rle1_dsk1 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */
810 uint64_t rle1_dsk0 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */
811 uint64_t rle0_dsk1 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */
812 uint64_t rle0_dsk0 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */
813 uint64_t reserved_19_19 : 1;
814 uint64_t rlk1_stat1 : 1; /**< Bist status of rlk1.csr.stat_mem1 ***NOTE: Added in pass 2.0 */
815 uint64_t rlk1_fwc : 1; /**< Bist status of rlk1.fwc.cal_chan_ram */
816 uint64_t rlk1_stat : 1; /**< Bist status of rlk1.csr.stat_mem */
817 uint64_t reserved_15_15 : 1;
818 uint64_t rlk0_stat1 : 1; /**< Bist status of rlk0.csr.stat_mem1 ***NOTE: Added in pass 2.0 */
819 uint64_t rlk0_fwc : 1; /**< Bist status of rlk0.fwc.cal_chan_ram */
820 uint64_t rlk0_stat : 1; /**< Bist status of rlk0.csr.stat_mem */
821 uint64_t tlk1_stat1 : 1; /**< Bist status of tlk1.csr.stat_mem1 */
822 uint64_t tlk1_fwc : 1; /**< Bist status of tlk1.fwc.cal_chan_ram */
823 uint64_t reserved_9_9 : 1;
824 uint64_t tlk1_txf2 : 1; /**< Bist status of tlk1.txf.tx_map_mem */
825 uint64_t tlk1_txf1 : 1; /**< Bist status of tlk1.txf.tx_fif_mem1 */
826 uint64_t tlk1_txf0 : 1; /**< Bist status of tlk1.txf.tx_fif_mem0 */
827 uint64_t tlk0_stat1 : 1; /**< Bist status of tlk0.csr.stat_mem1 */
828 uint64_t tlk0_fwc : 1; /**< Bist status of tlk0.fwc.cal_chan_ram */
829 uint64_t reserved_3_3 : 1;
830 uint64_t tlk0_txf2 : 1; /**< Bist status of tlk0.txf.tx_map_mem */
831 uint64_t tlk0_txf1 : 1; /**< Bist status of tlk0.txf.tx_fif_mem1 */
832 uint64_t tlk0_txf0 : 1; /**< Bist status of tlk0.txf.tx_fif_mem0 */
834 uint64_t tlk0_txf0 : 1;
835 uint64_t tlk0_txf1 : 1;
836 uint64_t tlk0_txf2 : 1;
837 uint64_t reserved_3_3 : 1;
838 uint64_t tlk0_fwc : 1;
839 uint64_t tlk0_stat1 : 1;
840 uint64_t tlk1_txf0 : 1;
841 uint64_t tlk1_txf1 : 1;
842 uint64_t tlk1_txf2 : 1;
843 uint64_t reserved_9_9 : 1;
844 uint64_t tlk1_fwc : 1;
845 uint64_t tlk1_stat1 : 1;
846 uint64_t rlk0_stat : 1;
847 uint64_t rlk0_fwc : 1;
848 uint64_t rlk0_stat1 : 1;
849 uint64_t reserved_15_15 : 1;
850 uint64_t rlk1_stat : 1;
851 uint64_t rlk1_fwc : 1;
852 uint64_t rlk1_stat1 : 1;
853 uint64_t reserved_19_19 : 1;
854 uint64_t rle0_dsk0 : 1;
855 uint64_t rle0_dsk1 : 1;
856 uint64_t rle1_dsk0 : 1;
857 uint64_t rle1_dsk1 : 1;
858 uint64_t rle2_dsk0 : 1;
859 uint64_t rle2_dsk1 : 1;
860 uint64_t rle3_dsk0 : 1;
861 uint64_t rle3_dsk1 : 1;
862 uint64_t rle4_dsk0 : 1;
863 uint64_t rle4_dsk1 : 1;
864 uint64_t rle5_dsk0 : 1;
865 uint64_t rle5_dsk1 : 1;
866 uint64_t rle6_dsk0 : 1;
867 uint64_t rle6_dsk1 : 1;
868 uint64_t rle7_dsk0 : 1;
869 uint64_t rle7_dsk1 : 1;
870 uint64_t reserved_36_51 : 16;
871 uint64_t rxf_mem0 : 1;
872 uint64_t rxf_mem1 : 1;
873 uint64_t rxf_mem2 : 1;
874 uint64_t rxf_pmap : 1;
875 uint64_t rxf_x2p0 : 1;
876 uint64_t rxf_x2p1 : 1;
877 uint64_t reserved_58_63 : 6;
882 uint64_t reserved_58_63 : 6;
883 uint64_t rxf_x2p1 : 1; /**< Bist status of rxf.x2p_fif_mem1 */
884 uint64_t rxf_x2p0 : 1; /**< Bist status of rxf.x2p_fif_mem0 */
885 uint64_t rxf_pmap : 1; /**< Bist status of rxf.rx_map_mem */
886 uint64_t rxf_mem2 : 1; /**< Bist status of rxf.rx_fif_mem2 */
887 uint64_t rxf_mem1 : 1; /**< Bist status of rxf.rx_fif_mem1 */
888 uint64_t rxf_mem0 : 1; /**< Bist status of rxf.rx_fif_mem0 */
889 uint64_t reserved_36_51 : 16;
890 uint64_t rle7_dsk1 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */
891 uint64_t rle7_dsk0 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */
892 uint64_t rle6_dsk1 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */
893 uint64_t rle6_dsk0 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */
894 uint64_t rle5_dsk1 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */
895 uint64_t rle5_dsk0 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */
896 uint64_t rle4_dsk1 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */
897 uint64_t rle4_dsk0 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */
898 uint64_t rle3_dsk1 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */
899 uint64_t rle3_dsk0 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */
900 uint64_t rle2_dsk1 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */
901 uint64_t rle2_dsk0 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */
902 uint64_t rle1_dsk1 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */
903 uint64_t rle1_dsk0 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */
904 uint64_t rle0_dsk1 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */
905 uint64_t rle0_dsk0 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */
906 uint64_t reserved_19_19 : 1;
907 uint64_t rlk1_stat1 : 1; /**< Bist status of rlk1.csr.stat_mem1 ***NOTE: Added in pass 2.0 */
908 uint64_t rlk1_fwc : 1; /**< Bist status of rlk1.fwc.cal_chan_ram */
909 uint64_t rlk1_stat : 1; /**< Bist status of rlk1.csr.stat_mem0 */
910 uint64_t reserved_15_15 : 1;
911 uint64_t rlk0_stat1 : 1; /**< Bist status of rlk0.csr.stat_mem1 ***NOTE: Added in pass 2.0 */
912 uint64_t rlk0_fwc : 1; /**< Bist status of rlk0.fwc.cal_chan_ram */
913 uint64_t rlk0_stat : 1; /**< Bist status of rlk0.csr.stat_mem0 */
914 uint64_t tlk1_stat1 : 1; /**< Bist status of tlk1.csr.stat_mem1 */
915 uint64_t tlk1_fwc : 1; /**< Bist status of tlk1.fwc.cal_chan_ram */
916 uint64_t tlk1_stat0 : 1; /**< Bist status of tlk1.csr.stat_mem0 */
917 uint64_t tlk1_txf2 : 1; /**< Bist status of tlk1.txf.tx_map_mem */
918 uint64_t tlk1_txf1 : 1; /**< Bist status of tlk1.txf.tx_fif_mem1 */
919 uint64_t tlk1_txf0 : 1; /**< Bist status of tlk1.txf.tx_fif_mem0 */
920 uint64_t tlk0_stat1 : 1; /**< Bist status of tlk0.csr.stat_mem1 */
921 uint64_t tlk0_fwc : 1; /**< Bist status of tlk0.fwc.cal_chan_ram */
922 uint64_t tlk0_stat0 : 1; /**< Bist status of tlk0.csr.stat_mem0 */
923 uint64_t tlk0_txf2 : 1; /**< Bist status of tlk0.txf.tx_map_mem */
924 uint64_t tlk0_txf1 : 1; /**< Bist status of tlk0.txf.tx_fif_mem1 */
925 uint64_t tlk0_txf0 : 1; /**< Bist status of tlk0.txf.tx_fif_mem0 */
927 uint64_t tlk0_txf0 : 1;
928 uint64_t tlk0_txf1 : 1;
929 uint64_t tlk0_txf2 : 1;
930 uint64_t tlk0_stat0 : 1;
931 uint64_t tlk0_fwc : 1;
932 uint64_t tlk0_stat1 : 1;
933 uint64_t tlk1_txf0 : 1;
934 uint64_t tlk1_txf1 : 1;
935 uint64_t tlk1_txf2 : 1;
936 uint64_t tlk1_stat0 : 1;
937 uint64_t tlk1_fwc : 1;
938 uint64_t tlk1_stat1 : 1;
939 uint64_t rlk0_stat : 1;
940 uint64_t rlk0_fwc : 1;
941 uint64_t rlk0_stat1 : 1;
942 uint64_t reserved_15_15 : 1;
943 uint64_t rlk1_stat : 1;
944 uint64_t rlk1_fwc : 1;
945 uint64_t rlk1_stat1 : 1;
946 uint64_t reserved_19_19 : 1;
947 uint64_t rle0_dsk0 : 1;
948 uint64_t rle0_dsk1 : 1;
949 uint64_t rle1_dsk0 : 1;
950 uint64_t rle1_dsk1 : 1;
951 uint64_t rle2_dsk0 : 1;
952 uint64_t rle2_dsk1 : 1;
953 uint64_t rle3_dsk0 : 1;
954 uint64_t rle3_dsk1 : 1;
955 uint64_t rle4_dsk0 : 1;
956 uint64_t rle4_dsk1 : 1;
957 uint64_t rle5_dsk0 : 1;
958 uint64_t rle5_dsk1 : 1;
959 uint64_t rle6_dsk0 : 1;
960 uint64_t rle6_dsk1 : 1;
961 uint64_t rle7_dsk0 : 1;
962 uint64_t rle7_dsk1 : 1;
963 uint64_t reserved_36_51 : 16;
964 uint64_t rxf_mem0 : 1;
965 uint64_t rxf_mem1 : 1;
966 uint64_t rxf_mem2 : 1;
967 uint64_t rxf_pmap : 1;
968 uint64_t rxf_x2p0 : 1;
969 uint64_t rxf_x2p1 : 1;
970 uint64_t reserved_58_63 : 6;
975 uint64_t reserved_58_63 : 6;
976 uint64_t rxf_x2p1 : 1; /**< Bist status of rxf.x2p_fif_mem1 */
977 uint64_t rxf_x2p0 : 1; /**< Bist status of rxf.x2p_fif_mem0 */
978 uint64_t rxf_pmap : 1; /**< Bist status of rxf.rx_map_mem */
979 uint64_t rxf_mem2 : 1; /**< Bist status of rxf.rx_fif_mem2 */
980 uint64_t rxf_mem1 : 1; /**< Bist status of rxf.rx_fif_mem1 */
981 uint64_t rxf_mem0 : 1; /**< Bist status of rxf.rx_fif_mem0 */
982 uint64_t reserved_36_51 : 16;
983 uint64_t rle7_dsk1 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */
984 uint64_t rle7_dsk0 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */
985 uint64_t rle6_dsk1 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */
986 uint64_t rle6_dsk0 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */
987 uint64_t rle5_dsk1 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */
988 uint64_t rle5_dsk0 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */
989 uint64_t rle4_dsk1 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */
990 uint64_t rle4_dsk0 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */
991 uint64_t rle3_dsk1 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */
992 uint64_t rle3_dsk0 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */
993 uint64_t rle2_dsk1 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */
994 uint64_t rle2_dsk0 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */
995 uint64_t rle1_dsk1 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */
996 uint64_t rle1_dsk0 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */
997 uint64_t rle0_dsk1 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */
998 uint64_t rle0_dsk0 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */
999 uint64_t reserved_18_19 : 2;
1000 uint64_t rlk1_fwc : 1; /**< Bist status of rlk1.fwc.cal_chan_ram */
1001 uint64_t rlk1_stat : 1; /**< Bist status of rlk1.csr.stat_mem */
1002 uint64_t reserved_14_15 : 2;
1003 uint64_t rlk0_fwc : 1; /**< Bist status of rlk0.fwc.cal_chan_ram */
1004 uint64_t rlk0_stat : 1; /**< Bist status of rlk0.csr.stat_mem */
1005 uint64_t reserved_11_11 : 1;
1006 uint64_t tlk1_fwc : 1; /**< Bist status of tlk1.fwc.cal_chan_ram */
1007 uint64_t tlk1_stat : 1; /**< Bist status of tlk1.csr.stat_mem */
1008 uint64_t tlk1_txf2 : 1; /**< Bist status of tlk1.txf.tx_map_mem */
1009 uint64_t tlk1_txf1 : 1; /**< Bist status of tlk1.txf.tx_fif_mem1 */
1010 uint64_t tlk1_txf0 : 1; /**< Bist status of tlk1.txf.tx_fif_mem0 */
1011 uint64_t reserved_5_5 : 1;
1012 uint64_t tlk0_fwc : 1; /**< Bist status of tlk0.fwc.cal_chan_ram */
1013 uint64_t tlk0_stat : 1; /**< Bist status of tlk0.csr.stat_mem */
1014 uint64_t tlk0_txf2 : 1; /**< Bist status of tlk0.txf.tx_map_mem */
1015 uint64_t tlk0_txf1 : 1; /**< Bist status of tlk0.txf.tx_fif_mem1 */
1016 uint64_t tlk0_txf0 : 1; /**< Bist status of tlk0.txf.tx_fif_mem0 */
1018 uint64_t tlk0_txf0 : 1;
1019 uint64_t tlk0_txf1 : 1;
1020 uint64_t tlk0_txf2 : 1;
1021 uint64_t tlk0_stat : 1;
1022 uint64_t tlk0_fwc : 1;
1023 uint64_t reserved_5_5 : 1;
1024 uint64_t tlk1_txf0 : 1;
1025 uint64_t tlk1_txf1 : 1;
1026 uint64_t tlk1_txf2 : 1;
1027 uint64_t tlk1_stat : 1;
1028 uint64_t tlk1_fwc : 1;
1029 uint64_t reserved_11_11 : 1;
1030 uint64_t rlk0_stat : 1;
1031 uint64_t rlk0_fwc : 1;
1032 uint64_t reserved_14_15 : 2;
1033 uint64_t rlk1_stat : 1;
1034 uint64_t rlk1_fwc : 1;
1035 uint64_t reserved_18_19 : 2;
1036 uint64_t rle0_dsk0 : 1;
1037 uint64_t rle0_dsk1 : 1;
1038 uint64_t rle1_dsk0 : 1;
1039 uint64_t rle1_dsk1 : 1;
1040 uint64_t rle2_dsk0 : 1;
1041 uint64_t rle2_dsk1 : 1;
1042 uint64_t rle3_dsk0 : 1;
1043 uint64_t rle3_dsk1 : 1;
1044 uint64_t rle4_dsk0 : 1;
1045 uint64_t rle4_dsk1 : 1;
1046 uint64_t rle5_dsk0 : 1;
1047 uint64_t rle5_dsk1 : 1;
1048 uint64_t rle6_dsk0 : 1;
1049 uint64_t rle6_dsk1 : 1;
1050 uint64_t rle7_dsk0 : 1;
1051 uint64_t rle7_dsk1 : 1;
1052 uint64_t reserved_36_51 : 16;
1053 uint64_t rxf_mem0 : 1;
1054 uint64_t rxf_mem1 : 1;
1055 uint64_t rxf_mem2 : 1;
1056 uint64_t rxf_pmap : 1;
1057 uint64_t rxf_x2p0 : 1;
1058 uint64_t rxf_x2p1 : 1;
1059 uint64_t reserved_58_63 : 6;
1069 uint64_t u64;
1072 uint64_t reserved_4_63 : 60;
1073 uint64_t rid_rstdis : 1; /**< Disable automatic reassembly-id error recovery. For diagnostic
1077 uint64_t reset : 1; /**< Reset ILK. For diagnostic use only.
1080 uint64_t cclk_dis : 1; /**< Disable ILK conditional clocking. For diagnostic use only. */
1081 uint64_t rxf_xlink : 1; /**< Causes external loopback traffic to switch links. Enabling
1084 uint64_t rxf_xlink : 1;
1085 uint64_t cclk_dis : 1;
1086 uint64_t reset : 1;
1087 uint64_t rid_rstdis : 1;
1088 uint64_t reserved_4_63 : 60;
1094 uint64_t reserved_2_63 : 62;
1095 uint64_t cclk_dis : 1; /**< Disable ILK conditional clocking. For diagnostic use only. */
1096 uint64_t rxf_xlink : 1; /**< Causes external loopback traffic to switch links. Enabling
1099 uint64_t rxf_xlink : 1;
1100 uint64_t cclk_dis : 1;
1101 uint64_t reserved_2_63 : 62;
1111 uint64_t u64;
1114 uint64_t reserved_5_63 : 59;
1115 uint64_t rxf_push_full : 1; /**< RXF overflow */
1116 uint64_t rxf_pop_empty : 1; /**< RXF underflow */
1117 uint64_t rxf_ctl_perr : 1; /**< RXF parity error occurred on sideband control signals. Data
1119 uint64_t rxf_lnk1_perr : 1; /**< RXF parity error occurred on RxLink1 packet data
1121 uint64_t rxf_lnk0_perr : 1; /**< RXF parity error occurred on RxLink0 packet data. Packet will
1124 uint64_t rxf_lnk0_perr : 1;
1125 uint64_t rxf_lnk1_perr : 1;
1126 uint64_t rxf_ctl_perr : 1;
1127 uint64_t rxf_pop_empty : 1;
1128 uint64_t rxf_push_full : 1;
1129 uint64_t reserved_5_63 : 59;
1141 uint64_t u64;
1144 uint64_t reserved_5_63 : 59;
1145 uint64_t rxf_push_full : 1; /**< RXF overflow */
1146 uint64_t rxf_pop_empty : 1; /**< RXF underflow */
1147 uint64_t rxf_ctl_perr : 1; /**< RXF parity error occurred on sideband control signals. Data
1149 uint64_t rxf_lnk1_perr : 1; /**< RXF parity error occurred on RxLink1 packet data
1151 uint64_t rxf_lnk0_perr : 1; /**< RXF parity error occurred on RxLink0 packet data
1154 uint64_t rxf_lnk0_perr : 1;
1155 uint64_t rxf_lnk1_perr : 1;
1156 uint64_t rxf_ctl_perr : 1;
1157 uint64_t rxf_pop_empty : 1;
1158 uint64_t rxf_push_full : 1;
1159 uint64_t reserved_5_63 : 59;
1171 uint64_t u64;
1174 uint64_t reserved_13_63 : 51;
1175 uint64_t rle7_int : 1; /**< RxLane7 interrupt status. See ILK_RX_LNE7_INT */
1176 uint64_t rle6_int : 1; /**< RxLane6 interrupt status. See ILK_RX_LNE6_INT */
1177 uint64_t rle5_int : 1; /**< RxLane5 interrupt status. See ILK_RX_LNE5_INT */
1178 uint64_t rle4_int : 1; /**< RxLane4 interrupt status. See ILK_RX_LNE4_INT */
1179 uint64_t rle3_int : 1; /**< RxLane3 interrupt status. See ILK_RX_LNE3_INT */
1180 uint64_t rle2_int : 1; /**< RxLane2 interrupt status. See ILK_RX_LNE2_INT */
1181 uint64_t rle1_int : 1; /**< RxLane1 interrupt status. See ILK_RX_LNE1_INT */
1182 uint64_t rle0_int : 1; /**< RxLane0 interrupt status. See ILK_RX_LNE0_INT */
1183 uint64_t rlk1_int : 1; /**< RxLink1 interrupt status. See ILK_RX1_INT */
1184 uint64_t rlk0_int : 1; /**< RxLink0 interrupt status. See ILK_RX0_INT */
1185 uint64_t tlk1_int : 1; /**< TxLink1 interrupt status. See ILK_TX1_INT */
1186 uint64_t tlk0_int : 1; /**< TxLink0 interrupt status. See ILK_TX0_INT */
1187 uint64_t gbl_int : 1; /**< Global interrupt status. See ILK_GBL_INT */
1189 uint64_t gbl_int : 1;
1190 uint64_t tlk0_int : 1;
1191 uint64_t tlk1_int : 1;
1192 uint64_t rlk0_int : 1;
1193 uint64_t rlk1_int : 1;
1194 uint64_t rle0_int : 1;
1195 uint64_t rle1_int : 1;
1196 uint64_t rle2_int : 1;
1197 uint64_t rle3_int : 1;
1198 uint64_t rle4_int : 1;
1199 uint64_t rle5_int : 1;
1200 uint64_t rle6_int : 1;
1201 uint64_t rle7_int : 1;
1202 uint64_t reserved_13_63 : 51;
1214 uint64_t u64;
1217 uint64_t reserved_60_63 : 4;
1218 uint64_t tx_bad_crc32 : 1; /**< Send 1 diagnostic word with bad CRC32 to the selected lane.
1220 uint64_t tx_bad_6467_cnt : 5; /**< Send N bad 64B/67B codewords on selected lane */
1221 uint64_t tx_bad_sync_cnt : 3; /**< Send N bad sync words on selected lane */
1222 uint64_t tx_bad_scram_cnt : 3; /**< Send N bad scram state on selected lane */
1223 uint64_t reserved_40_47 : 8;
1224 uint64_t tx_bad_lane_sel : 8; /**< Select lane to apply error injection counts */
1225 uint64_t reserved_24_31 : 8;
1226 uint64_t tx_dis_dispr : 8; /**< Per-lane disparity disable */
1227 uint64_t reserved_8_15 : 8;
1228 uint64_t tx_dis_scram : 8; /**< Per-lane scrambler disable */
1230 uint64_t tx_dis_scram : 8;
1231 uint64_t reserved_8_15 : 8;
1232 uint64_t tx_dis_dispr : 8;
1233 uint64_t reserved_24_31 : 8;
1234 uint64_t tx_bad_lane_sel : 8;
1235 uint64_t reserved_40_47 : 8;
1236 uint64_t tx_bad_scram_cnt : 3;
1237 uint64_t tx_bad_sync_cnt : 3;
1238 uint64_t tx_bad_6467_cnt : 5;
1239 uint64_t tx_bad_crc32 : 1;
1240 uint64_t reserved_60_63 : 4;
1252 uint64_t u64;
1255 uint64_t reserved_56_63 : 8;
1256 uint64_t rx_lnk_stat : 8; /**< Link status received in the diagnostic word (per-lane) */
1257 uint64_t reserved_40_47 : 8;
1258 uint64_t rx_lne_stat : 8; /**< Lane status received in the diagnostic word (per-lane) */
1259 uint64_t reserved_24_31 : 8;
1260 uint64_t tx_lnk_stat : 8; /**< Link status transmitted in the diagnostic word (per-lane) */
1261 uint64_t reserved_8_15 : 8;
1262 uint64_t tx_lne_stat : 8; /**< Lane status transmitted in the diagnostic word (per-lane) */
1264 uint64_t tx_lne_stat : 8;
1265 uint64_t reserved_8_15 : 8;
1266 uint64_t tx_lnk_stat : 8;
1267 uint64_t reserved_24_31 : 8;
1268 uint64_t rx_lne_stat : 8;
1269 uint64_t reserved_40_47 : 8;
1270 uint64_t rx_lnk_stat : 8;
1271 uint64_t reserved_56_63 : 8;
1283 uint64_t u64;
1286 uint64_t ext_lpbk_fc : 1; /**< Enable Rx-Tx flowcontrol loopback (external) */
1287 uint64_t ext_lpbk : 1; /**< Enable Rx-Tx data loopback (external). Note that with differing
1289 uint64_t reserved_60_61 : 2;
1290 uint64_t lnk_stats_wrap : 1; /**< Upon overflow, a statistics counter should wrap instead of
1294 uint64_t bcw_push : 1; /**< The 8 byte burst control word containing the SOP will be
1298 uint64_t mproto_ign : 1; /**< When LA_MODE=1 and MPROTO_IGN=0, the multi-protocol bit of the
1304 uint64_t ptrn_mode : 1; /**< Enable programmable test pattern mode */
1305 uint64_t lnk_stats_rdclr : 1; /**< CSR read to ILK_RXx_STAT* clears the counter after returning
1307 uint64_t lnk_stats_ena : 1; /**< Enable link statistics counters */
1308 uint64_t mltuse_fc_ena : 1; /**< Use multi-use field for calendar */
1309 uint64_t cal_ena : 1; /**< Enable Rx calendar. When the calendar table is disabled, all
1311 uint64_t mfrm_len : 13; /**< The quantity of data sent on each lane including one sync word,
1315 uint64_t brst_shrt : 7; /**< Minimum interval between burst control words, as a multiple of
1320 uint64_t lane_rev : 1; /**< Lane reversal. When enabled, lane de-striping is performed
1323 uint64_t brst_max : 5; /**< Maximum size of a data burst, as a multiple of 64 byte blocks.
1329 uint64_t reserved_25_25 : 1;
1330 uint64_t cal_depth : 9; /**< Number of valid entries in the calendar. Supported range from
1332 uint64_t reserved_8_15 : 8;
1333 uint64_t lane_ena : 8; /**< Lane enable mask. Link is enabled if any lane is enabled. The
1347 uint64_t lane_ena : 8;
1348 uint64_t reserved_8_15 : 8;
1349 uint64_t cal_depth : 9;
1350 uint64_t reserved_25_25 : 1;
1351 uint64_t brst_max : 5;
1352 uint64_t lane_rev : 1;
1353 uint64_t brst_shrt : 7;
1354 uint64_t mfrm_len : 13;
1355 uint64_t cal_ena : 1;
1356 uint64_t mltuse_fc_ena : 1;
1357 uint64_t lnk_stats_ena : 1;
1358 uint64_t lnk_stats_rdclr : 1;
1359 uint64_t ptrn_mode : 1;
1360 uint64_t mproto_ign : 1;
1361 uint64_t bcw_push : 1;
1362 uint64_t lnk_stats_wrap : 1;
1363 uint64_t reserved_60_61 : 2;
1364 uint64_t ext_lpbk : 1;
1365 uint64_t ext_lpbk_fc : 1;
1371 uint64_t ext_lpbk_fc : 1; /**< Enable Rx-Tx flowcontrol loopback (external) */
1372 uint64_t ext_lpbk : 1; /**< Enable Rx-Tx data loopback (external). Note that with differing
1374 uint64_t reserved_57_61 : 5;
1375 uint64_t ptrn_mode : 1; /**< Enable programmable test pattern mode */
1376 uint64_t lnk_stats_rdclr : 1; /**< CSR read to ILK_RXx_STAT* clears the counter after returning
1378 uint64_t lnk_stats_ena : 1; /**< Enable link statistics counters */
1379 uint64_t mltuse_fc_ena : 1; /**< Use multi-use field for calendar */
1380 uint64_t cal_ena : 1; /**< Enable Rx calendar. When the calendar table is disabled, all
1382 uint64_t mfrm_len : 13; /**< The quantity of data sent on each lane including one sync word,
1386 uint64_t brst_shrt : 7; /**< Minimum interval between burst control words, as a multiple of
1391 uint64_t lane_rev : 1; /**< Lane reversal. When enabled, lane de-striping is performed
1394 uint64_t brst_max : 5; /**< Maximum size of a data burst, as a multiple of 64 byte blocks.
1400 uint64_t reserved_25_25 : 1;
1401 uint64_t cal_depth : 9; /**< Number of valid entries in the calendar. Supported range from
1403 uint64_t reserved_8_15 : 8;
1404 uint64_t lane_ena : 8; /**< Lane enable mask. Link is enabled if any lane is enabled. The
1418 uint64_t lane_ena : 8;
1419 uint64_t reserved_8_15 : 8;
1420 uint64_t cal_depth : 9;
1421 uint64_t reserved_25_25 : 1;
1422 uint64_t brst_max : 5;
1423 uint64_t lane_rev : 1;
1424 uint64_t brst_shrt : 7;
1425 uint64_t mfrm_len : 13;
1426 uint64_t cal_ena : 1;
1427 uint64_t mltuse_fc_ena : 1;
1428 uint64_t lnk_stats_ena : 1;
1429 uint64_t lnk_stats_rdclr : 1;
1430 uint64_t ptrn_mode : 1;
1431 uint64_t reserved_57_61 : 5;
1432 uint64_t ext_lpbk : 1;
1433 uint64_t ext_lpbk_fc : 1;
1443 uint64_t u64;
1446 uint64_t reserved_62_63 : 2;
1447 uint64_t rx_fifo_cnt : 12; /**< Number of 64-bit words currently consumed by this link in the
1449 uint64_t reserved_48_49 : 2;
1450 uint64_t rx_fifo_hwm : 12; /**< Number of 64-bit words consumed by this link before switch
1455 uint64_t reserved_34_35 : 2;
1456 uint64_t rx_fifo_max : 12; /**< Maximum number of 64-bit words consumed by this link in the RX
1458 uint64_t pkt_flush : 1; /**< Packet receive flush. Writing PKT_FLUSH=1 will cause all open
1460 uint64_t pkt_ena : 1; /**< Packet receive enable. When PKT_ENA=0, any received SOP causes
1462 uint64_t la_mode : 1; /**< 0 = Interlaken
1464 uint64_t tx_link_fc : 1; /**< Link flow control status transmitted by the Tx-Link
1466 uint64_t rx_link_fc : 1; /**< Link flow control status received in burst/idle control words.
1468 uint64_t rx_align_ena : 1; /**< Enable the lane alignment. This should only be done after all
1473 uint64_t reserved_8_15 : 8;
1474 uint64_t rx_bdry_lock_ena : 8; /**< Enable word boundary lock. While disabled, received data is
1478 uint64_t rx_bdry_lock_ena : 8;
1479 uint64_t reserved_8_15 : 8;
1480 uint64_t rx_align_ena : 1;
1481 uint64_t rx_link_fc : 1;
1482 uint64_t tx_link_fc : 1;
1483 uint64_t la_mode : 1;
1484 uint64_t pkt_ena : 1;
1485 uint64_t pkt_flush : 1;
1486 uint64_t rx_fifo_max : 12;
1487 uint64_t reserved_34_35 : 2;
1488 uint64_t rx_fifo_hwm : 12;
1489 uint64_t reserved_48_49 : 2;
1490 uint64_t rx_fifo_cnt : 12;
1491 uint64_t reserved_62_63 : 2;
1503 uint64_t u64;
1506 uint64_t status : 64; /**< Flow control status for port-pipes 63-0, where a 1 indicates
1510 uint64_t status : 64;
1522 uint64_t u64;
1525 uint64_t status : 64; /**< Flow control status for port-pipes 127-64, where a 1 indicates
1529 uint64_t status : 64;
1541 uint64_t u64;
1544 uint64_t reserved_14_63 : 50;
1545 uint64_t inc : 6; /**< Increment to add to current index for next index. NOTE:
1547 uint64_t reserved_6_7 : 2;
1548 uint64_t index : 6; /**< Specify the group of 8 entries accessed by the next CSR
1552 uint64_t index : 6;
1553 uint64_t reserved_6_7 : 2;
1554 uint64_t inc : 6;
1555 uint64_t reserved_14_63 : 50;
1567 uint64_t u64;
1570 uint64_t reserved_32_63 : 32;
1571 uint64_t clr : 1; /**< CSR read to ILK_RXx_MEM_STAT0 clears the selected counter after
1573 uint64_t reserved_24_30 : 7;
1574 uint64_t inc : 8; /**< Increment to add to current index for next index */
1575 uint64_t reserved_8_15 : 8;
1576 uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the
1579 uint64_t index : 8;
1580 uint64_t reserved_8_15 : 8;
1581 uint64_t inc : 8;
1582 uint64_t reserved_24_30 : 7;
1583 uint64_t clr : 1;
1584 uint64_t reserved_32_63 : 32;
1596 uint64_t u64;
1599 uint64_t reserved_32_63 : 32;
1600 uint64_t clr : 1; /**< CSR read to ILK_RXx_MEM_STAT1 clears the selected counter after
1602 uint64_t reserved_24_30 : 7;
1603 uint64_t inc : 8; /**< Increment to add to current index for next index */
1604 uint64_t reserved_8_15 : 8;
1605 uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the
1608 uint64_t index : 8;
1609 uint64_t reserved_8_15 : 8;
1610 uint64_t inc : 8;
1611 uint64_t reserved_24_30 : 7;
1612 uint64_t clr : 1;
1613 uint64_t reserved_32_63 : 32;
1625 uint64_t u64;
1628 uint64_t reserved_9_63 : 55;
1629 uint64_t pkt_drop_sop : 1; /**< Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,
1634 uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or
1636 uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
1637 uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown
1639 uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */
1640 uint64_t lane_align_done : 1; /**< Lane alignment successful */
1641 uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and
1643 uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */
1644 uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries). Hardware will repeat lane
1648 uint64_t lane_align_fail : 1;
1649 uint64_t crc24_err : 1;
1650 uint64_t word_sync_done : 1;
1651 uint64_t lane_align_done : 1;
1652 uint64_t stat_cnt_ovfl : 1;
1653 uint64_t lane_bad_word : 1;
1654 uint64_t pkt_drop_rxf : 1;
1655 uint64_t pkt_drop_rid : 1;
1656 uint64_t pkt_drop_sop : 1;
1657 uint64_t reserved_9_63 : 55;
1663 uint64_t reserved_8_63 : 56;
1664 uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or
1666 uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
1667 uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown
1669 uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */
1670 uint64_t lane_align_done : 1; /**< Lane alignment successful */
1671 uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and
1673 uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */
1674 uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries). Hardware will repeat lane
1678 uint64_t lane_align_fail : 1;
1679 uint64_t crc24_err : 1;
1680 uint64_t word_sync_done : 1;
1681 uint64_t lane_align_done : 1;
1682 uint64_t stat_cnt_ovfl : 1;
1683 uint64_t lane_bad_word : 1;
1684 uint64_t pkt_drop_rxf : 1;
1685 uint64_t pkt_drop_rid : 1;
1686 uint64_t reserved_8_63 : 56;
1696 uint64_t u64;
1699 uint64_t reserved_9_63 : 55;
1700 uint64_t pkt_drop_sop : 1; /**< Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,
1705 uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or
1707 uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
1708 uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown
1710 uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */
1711 uint64_t lane_align_done : 1; /**< Lane alignment successful */
1712 uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and
1714 uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */
1715 uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries) */
1717 uint64_t lane_align_fail : 1;
1718 uint64_t crc24_err : 1;
1719 uint64_t word_sync_done : 1;
1720 uint64_t lane_align_done : 1;
1721 uint64_t stat_cnt_ovfl : 1;
1722 uint64_t lane_bad_word : 1;
1723 uint64_t pkt_drop_rxf : 1;
1724 uint64_t pkt_drop_rid : 1;
1725 uint64_t pkt_drop_sop : 1;
1726 uint64_t reserved_9_63 : 55;
1732 uint64_t reserved_8_63 : 56;
1733 uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or
1735 uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */
1736 uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown
1738 uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */
1739 uint64_t lane_align_done : 1; /**< Lane alignment successful */
1740 uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and
1742 uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */
1743 uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries) */
1745 uint64_t lane_align_fail : 1;
1746 uint64_t crc24_err : 1;
1747 uint64_t word_sync_done : 1;
1748 uint64_t lane_align_done : 1;
1749 uint64_t stat_cnt_ovfl : 1;
1750 uint64_t lane_bad_word : 1;
1751 uint64_t pkt_drop_rxf : 1;
1752 uint64_t pkt_drop_rid : 1;
1753 uint64_t reserved_8_63 : 56;
1763 uint64_t u64;
1766 uint64_t reserved_16_63 : 48;
1767 uint64_t cnt : 16; /**< Byte count for jabber check. Failing packets will be
1776 uint64_t cnt : 16;
1777 uint64_t reserved_16_63 : 48;
1810 uint64_t u64;
1813 uint64_t reserved_36_63 : 28;
1814 uint64_t entry_ctl3 : 2; /**< XON/XOFF destination for entry (IDX*8)+3
1831 uint64_t port_pipe3 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+3
1835 uint64_t entry_ctl2 : 2; /**< XON/XOFF destination for entry (IDX*8)+2
1852 uint64_t port_pipe2 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+2
1856 uint64_t entry_ctl1 : 2; /**< XON/XOFF destination for entry (IDX*8)+1
1873 uint64_t port_pipe1 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+1
1877 uint64_t entry_ctl0 : 2; /**< XON/XOFF destination for entry (IDX*8)+0
1894 uint64_t port_pipe0 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+0
1899 uint64_t port_pipe0 : 7;
1900 uint64_t entry_ctl0 : 2;
1901 uint64_t port_pipe1 : 7;
1902 uint64_t entry_ctl1 : 2;
1903 uint64_t port_pipe2 : 7;
1904 uint64_t entry_ctl2 : 2;
1905 uint64_t port_pipe3 : 7;
1906 uint64_t entry_ctl3 : 2;
1907 uint64_t reserved_36_63 : 28;
1940 uint64_t u64;
1943 uint64_t reserved_36_63 : 28;
1944 uint64_t entry_ctl7 : 2; /**< XON/XOFF destination for entry (IDX*8)+7
1961 uint64_t port_pipe7 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+7
1965 uint64_t entry_ctl6 : 2; /**< XON/XOFF destination for entry (IDX*8)+6
1982 uint64_t port_pipe6 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+6
1986 uint64_t entry_ctl5 : 2; /**< XON/XOFF destination for entry (IDX*8)+5
2003 uint64_t port_pipe5 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+5
2007 uint64_t entry_ctl4 : 2; /**< XON/XOFF destination for entry (IDX*8)+4
2024 uint64_t port_pipe4 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+4
2029 uint64_t port_pipe4 : 7;
2030 uint64_t entry_ctl4 : 2;
2031 uint64_t port_pipe5 : 7;
2032 uint64_t entry_ctl5 : 2;
2033 uint64_t port_pipe6 : 7;
2034 uint64_t entry_ctl6 : 2;
2035 uint64_t port_pipe7 : 7;
2036 uint64_t entry_ctl7 : 2;
2037 uint64_t reserved_36_63 : 28;
2049 uint64_t u64;
2052 uint64_t reserved_28_63 : 36;
2053 uint64_t rx_pkt : 28; /**< Number of packets received (256M)
2057 uint64_t rx_pkt : 28;
2058 uint64_t reserved_28_63 : 36;
2070 uint64_t u64;
2073 uint64_t reserved_36_63 : 28;
2074 uint64_t rx_bytes : 36; /**< Number of bytes received (64GB)
2078 uint64_t rx_bytes : 36;
2079 uint64_t reserved_36_63 : 28;
2091 uint64_t u64;
2094 uint64_t reserved_6_63 : 58;
2095 uint64_t max_cnt : 6; /**< Maximum number of reassembly-ids allowed for a given link. If
2104 uint64_t max_cnt : 6;
2105 uint64_t reserved_6_63 : 58;
2116 uint64_t u64;
2119 uint64_t reserved_33_63 : 31;
2120 uint64_t crc24_match_cnt : 33; /**< Number of CRC24 matches received. Saturates. Interrupt on
2123 uint64_t crc24_match_cnt : 33;
2124 uint64_t reserved_33_63 : 31;
2130 uint64_t reserved_27_63 : 37;
2131 uint64_t crc24_match_cnt : 27; /**< Number of CRC24 matches received. Saturates. Interrupt on
2134 uint64_t crc24_match_cnt : 27;
2135 uint64_t reserved_27_63 : 37;
2145 uint64_t u64;
2148 uint64_t reserved_18_63 : 46;
2149 uint64_t crc24_err_cnt : 18; /**< Number of bursts with a detected CRC error. Saturates.
2152 uint64_t crc24_err_cnt : 18;
2153 uint64_t reserved_18_63 : 46;
2165 uint64_t u64;
2168 uint64_t reserved_48_63 : 16;
2169 uint64_t brst_not_full_cnt : 16; /**< Number of bursts received which terminated without an eop and
2172 uint64_t reserved_28_31 : 4;
2173 uint64_t brst_cnt : 28; /**< Number of bursts correctly received. (ie. good CRC24, not in
2176 uint64_t brst_cnt : 28;
2177 uint64_t reserved_28_31 : 4;
2178 uint64_t brst_not_full_cnt : 16;
2179 uint64_t reserved_48_63 : 16;
2185 uint64_t reserved_48_63 : 16;
2186 uint64_t brst_not_full_cnt : 16; /**< Number of bursts received which terminated without an eop and
2189 uint64_t reserved_16_31 : 16;
2190 uint64_t brst_cnt : 16; /**< Number of bursts correctly received. (ie. good CRC24, not in
2193 uint64_t brst_cnt : 16;
2194 uint64_t reserved_16_31 : 16;
2195 uint64_t brst_not_full_cnt : 16;
2196 uint64_t reserved_48_63 : 16;
2206 uint64_t u64;
2209 uint64_t reserved_16_63 : 48;
2210 uint64_t brst_max_err_cnt : 16; /**< Number of bursts received longer than the BurstMax parameter */
2212 uint64_t brst_max_err_cnt : 16;
2213 uint64_t reserved_16_63 : 48;
2225 uint64_t u64;
2228 uint64_t reserved_16_63 : 48;
2229 uint64_t brst_shrt_err_cnt : 16; /**< Number of bursts received that violate the BurstShort
2233 uint64_t brst_shrt_err_cnt : 16;
2234 uint64_t reserved_16_63 : 48;
2246 uint64_t u64;
2249 uint64_t reserved_23_63 : 41;
2250 uint64_t align_cnt : 23; /**< Number of alignment sequences received (ie. those that do not
2254 uint64_t align_cnt : 23;
2255 uint64_t reserved_23_63 : 41;
2261 uint64_t reserved_16_63 : 48;
2262 uint64_t align_cnt : 16; /**< Number of alignment sequences received (ie. those that do not
2266 uint64_t align_cnt : 16;
2267 uint64_t reserved_16_63 : 48;
2277 uint64_t u64;
2280 uint64_t reserved_16_63 : 48;
2281 uint64_t align_err_cnt : 16; /**< Number of alignment sequences received in error (ie. those that
2285 uint64_t align_err_cnt : 16;
2286 uint64_t reserved_16_63 : 48;
2298 uint64_t u64;
2301 uint64_t reserved_16_63 : 48;
2302 uint64_t bad_64b67b_cnt : 16; /**< Number of bad 64B/67B codewords. Saturates. Interrupt on
2305 uint64_t bad_64b67b_cnt : 16;
2306 uint64_t reserved_16_63 : 48;
2318 uint64_t u64;
2321 uint64_t reserved_32_63 : 32;
2322 uint64_t pkt_drop_rid_cnt : 16; /**< Number of packets dropped due to the lack of reassembly-ids or
2325 uint64_t pkt_drop_rxf_cnt : 16; /**< Number of packets dropped due to RX_FIFO_CNT >= RX_FIFO_MAX.
2329 uint64_t pkt_drop_rxf_cnt : 16;
2330 uint64_t pkt_drop_rid_cnt : 16;
2331 uint64_t reserved_32_63 : 32;
2343 uint64_t u64;
2346 uint64_t reserved_0_63 : 64;
2348 uint64_t reserved_0_63 : 64;
2360 uint64_t u64;
2363 uint64_t reserved_9_63 : 55;
2364 uint64_t rx_dis_psh_skip : 1; /**< When RX_DIS_PSH_SKIP=0, skip words are de-stripped.
2373 uint64_t reserved_6_7 : 2;
2374 uint64_t rx_scrm_sync : 1; /**< Rx scrambler synchronization status
2377 uint64_t rx_bdry_sync : 1; /**< Rx word boundary sync status */
2378 uint64_t rx_dis_ukwn : 1; /**< Disable normal response to unknown words. They are still
2380 uint64_t rx_dis_scram : 1; /**< Disable lane scrambler (debug) */
2381 uint64_t stat_rdclr : 1; /**< CSR read to ILK_RX_LNEx_STAT* clears the selected counter after
2383 uint64_t stat_ena : 1; /**< Enable RX lane statistics counters */
2385 uint64_t stat_ena : 1;
2386 uint64_t stat_rdclr : 1;
2387 uint64_t rx_dis_scram : 1;
2388 uint64_t rx_dis_ukwn : 1;
2389 uint64_t rx_bdry_sync : 1;
2390 uint64_t rx_scrm_sync : 1;
2391 uint64_t reserved_6_7 : 2;
2392 uint64_t rx_dis_psh_skip : 1;
2393 uint64_t reserved_9_63 : 55;
2399 uint64_t reserved_5_63 : 59;
2400 uint64_t rx_bdry_sync : 1; /**< Rx word boundary sync status */
2401 uint64_t rx_dis_ukwn : 1; /**< Disable normal response to unknown words. They are still
2403 uint64_t rx_dis_scram : 1; /**< Disable lane scrambler (debug) */
2404 uint64_t stat_rdclr : 1; /**< CSR read to ILK_RX_LNEx_STAT* clears the selected counter after
2406 uint64_t stat_ena : 1; /**< Enable RX lane statistics counters */
2408 uint64_t stat_ena : 1;
2409 uint64_t stat_rdclr : 1;
2410 uint64_t rx_dis_scram : 1;
2411 uint64_t rx_dis_ukwn : 1;
2412 uint64_t rx_bdry_sync : 1;
2413 uint64_t reserved_5_63 : 59;
2423 uint64_t u64;
2426 uint64_t reserved_9_63 : 55;
2427 uint64_t bad_64b67b : 1; /**< Bad 64B/67B codeword encountered. Once the bad word reaches
2431 uint64_t stat_cnt_ovfl : 1; /**< Rx lane statistic counter overflow */
2432 uint64_t stat_msg : 1; /**< Status bits for the link or a lane transitioned from a '1'
2434 uint64_t dskew_fifo_ovfl : 1; /**< Rx deskew fifo overflow occurred. */
2435 uint64_t scrm_sync_loss : 1; /**< 4 consecutive bad sync words or 3 consecutive scramble state
2437 uint64_t ukwn_cntl_word : 1; /**< Unknown framing control word. Block type does not match any of
2439 uint64_t crc32_err : 1; /**< Diagnostic CRC32 errors */
2440 uint64_t bdry_sync_loss : 1; /**< Rx logic loses word boundary sync (16 tries). Hardware will
2442 uint64_t serdes_lock_loss : 1; /**< Rx SERDES loses lock */
2444 uint64_t serdes_lock_loss : 1;
2445 uint64_t bdry_sync_loss : 1;
2446 uint64_t crc32_err : 1;
2447 uint64_t ukwn_cntl_word : 1;
2448 uint64_t scrm_sync_loss : 1;
2449 uint64_t dskew_fifo_ovfl : 1;
2450 uint64_t stat_msg : 1;
2451 uint64_t stat_cnt_ovfl : 1;
2452 uint64_t bad_64b67b : 1;
2453 uint64_t reserved_9_63 : 55;
2465 uint64_t u64;
2468 uint64_t reserved_9_63 : 55;
2469 uint64_t bad_64b67b : 1; /**< Bad 64B/67B codeword encountered. Once the bad word reaches
2473 uint64_t stat_cnt_ovfl : 1; /**< Rx lane statistic counter overflow */
2474 uint64_t stat_msg : 1; /**< Status bits for the link or a lane transitioned from a '1'
2476 uint64_t dskew_fifo_ovfl : 1; /**< Rx deskew fifo overflow occurred. */
2477 uint64_t scrm_sync_loss : 1; /**< 4 consecutive bad sync words or 3 consecutive scramble state
2479 uint64_t ukwn_cntl_word : 1; /**< Unknown framing control word. Block type does not match any of
2481 uint64_t crc32_err : 1; /**< Diagnostic CRC32 error */
2482 uint64_t bdry_sync_loss : 1; /**< Rx logic loses word boundary sync (16 tries). Hardware will
2484 uint64_t serdes_lock_loss : 1; /**< Rx SERDES loses lock */
2486 uint64_t serdes_lock_loss : 1;
2487 uint64_t bdry_sync_loss : 1;
2488 uint64_t crc32_err : 1;
2489 uint64_t ukwn_cntl_word : 1;
2490 uint64_t scrm_sync_loss : 1;
2491 uint64_t dskew_fifo_ovfl : 1;
2492 uint64_t stat_msg : 1;
2493 uint64_t stat_cnt_ovfl : 1;
2494 uint64_t bad_64b67b : 1;
2495 uint64_t reserved_9_63 : 55;
2507 uint64_t u64;
2510 uint64_t reserved_18_63 : 46;
2511 uint64_t ser_lock_loss_cnt : 18; /**< Number of times the lane lost clock-data-recovery.
2515 uint64_t ser_lock_loss_cnt : 18;
2516 uint64_t reserved_18_63 : 46;
2528 uint64_t u64;
2531 uint64_t reserved_18_63 : 46;
2532 uint64_t bdry_sync_loss_cnt : 18; /**< Number of times a lane lost word boundary synchronization.
2536 uint64_t bdry_sync_loss_cnt : 18;
2537 uint64_t reserved_18_63 : 46;
2549 uint64_t u64;
2552 uint64_t reserved_50_63 : 14;
2553 uint64_t syncw_good_cnt : 18; /**< Number of good synchronization words. Saturates. Interrupt on
2555 uint64_t reserved_18_31 : 14;
2556 uint64_t syncw_bad_cnt : 18; /**< Number of bad synchronization words. Saturates. Interrupt on
2559 uint64_t syncw_bad_cnt : 18;
2560 uint64_t reserved_18_31 : 14;
2561 uint64_t syncw_good_cnt : 18;
2562 uint64_t reserved_50_63 : 14;
2574 uint64_t u64;
2577 uint64_t reserved_18_63 : 46;
2578 uint64_t bad_64b67b_cnt : 18; /**< Number of bad 64B/67B words, meaning bit 65 or 64 has been
2582 uint64_t bad_64b67b_cnt : 18;
2583 uint64_t reserved_18_63 : 46;
2595 uint64_t u64;
2598 uint64_t reserved_59_63 : 5;
2599 uint64_t cntl_word_cnt : 27; /**< Number of control words received. Saturates. Interrupt on
2601 uint64_t reserved_27_31 : 5;
2602 uint64_t data_word_cnt : 27; /**< Number of data words received. Saturates. Interrupt on
2605 uint64_t data_word_cnt : 27;
2606 uint64_t reserved_27_31 : 5;
2607 uint64_t cntl_word_cnt : 27;
2608 uint64_t reserved_59_63 : 5;
2620 uint64_t u64;
2623 uint64_t reserved_18_63 : 46;
2624 uint64_t unkwn_word_cnt : 18; /**< Number of unknown control words. Saturates. Interrupt on
2627 uint64_t unkwn_word_cnt : 18;
2628 uint64_t reserved_18_63 : 46;
2640 uint64_t u64;
2643 uint64_t reserved_18_63 : 46;
2644 uint64_t scrm_sync_loss_cnt : 18; /**< Number of times scrambler synchronization was lost (due to
2649 uint64_t scrm_sync_loss_cnt : 18;
2650 uint64_t reserved_18_63 : 46;
2662 uint64_t u64;
2665 uint64_t reserved_18_63 : 46;
2666 uint64_t scrm_match_cnt : 18; /**< Number of scrambler state matches received. Saturates.
2669 uint64_t scrm_match_cnt : 18;
2670 uint64_t reserved_18_63 : 46;
2682 uint64_t u64;
2685 uint64_t reserved_18_63 : 46;
2686 uint64_t skipw_good_cnt : 18; /**< Number of good skip words. Saturates. Interrupt on saturation
2689 uint64_t skipw_good_cnt : 18;
2690 uint64_t reserved_18_63 : 46;
2702 uint64_t u64;
2705 uint64_t reserved_50_63 : 14;
2706 uint64_t crc32_err_cnt : 18; /**< Number of errors in the lane CRC. Saturates. Interrupt on
2708 uint64_t reserved_27_31 : 5;
2709 uint64_t crc32_match_cnt : 27; /**< Number of CRC32 matches received. Saturates. Interrupt on
2712 uint64_t crc32_match_cnt : 27;
2713 uint64_t reserved_27_31 : 5;
2714 uint64_t crc32_err_cnt : 18;
2715 uint64_t reserved_50_63 : 14;
2727 uint64_t u64;
2730 uint64_t reserved_25_63 : 39;
2731 uint64_t inc : 9; /**< Increment to add to current index for next index. */
2732 uint64_t reserved_9_15 : 7;
2733 uint64_t index : 9; /**< Specify the link/channel accessed by the next CSR read/write to
2736 uint64_t index : 9;
2737 uint64_t reserved_9_15 : 7;
2738 uint64_t inc : 9;
2739 uint64_t reserved_25_63 : 39;
2751 uint64_t u64;
2754 uint64_t reserved_6_63 : 58;
2755 uint64_t port_kind : 6; /**< Specify the port-kind for the link/channel selected by
2758 uint64_t port_kind : 6;
2759 uint64_t reserved_6_63 : 58;
2771 uint64_t u64;
2774 uint64_t reserved_57_63 : 7;
2775 uint64_t ser_rxpol_auto : 1; /**< Serdes lane receive polarity auto detection mode */
2776 uint64_t reserved_48_55 : 8;
2777 uint64_t ser_rxpol : 8; /**< Serdes lane receive polarity
2780 uint64_t reserved_32_39 : 8;
2781 uint64_t ser_txpol : 8; /**< Serdes lane transmit polarity
2784 uint64_t reserved_16_23 : 8;
2785 uint64_t ser_reset_n : 8; /**< Serdes lane reset */
2786 uint64_t reserved_6_7 : 2;
2787 uint64_t ser_pwrup : 2; /**< Serdes modules (QLM) power up. */
2788 uint64_t reserved_2_3 : 2;
2789 uint64_t ser_haul : 2; /**< Serdes module (QLM) haul mode */
2791 uint64_t ser_haul : 2;
2792 uint64_t reserved_2_3 : 2;
2793 uint64_t ser_pwrup : 2;
2794 uint64_t reserved_6_7 : 2;
2795 uint64_t ser_reset_n : 8;
2796 uint64_t reserved_16_23 : 8;
2797 uint64_t ser_txpol : 8;
2798 uint64_t reserved_32_39 : 8;
2799 uint64_t ser_rxpol : 8;
2800 uint64_t reserved_48_55 : 8;
2801 uint64_t ser_rxpol_auto : 1;
2802 uint64_t reserved_57_63 : 7;
2814 uint64_t u64;
2817 uint64_t ext_lpbk_fc : 1; /**< Enable Rx-Tx flowcontrol loopback (external) */
2818 uint64_t ext_lpbk : 1; /**< Enable Rx-Tx data loopback (external). Note that with differing
2820 uint64_t int_lpbk : 1; /**< Enable Tx-Rx loopback (internal) */
2821 uint64_t reserved_57_60 : 4;
2822 uint64_t ptrn_mode : 1; /**< Enable programmable test pattern mode. This mode allows
2831 uint64_t reserved_55_55 : 1;
2832 uint64_t lnk_stats_ena : 1; /**< Enable link statistics counters */
2833 uint64_t mltuse_fc_ena : 1; /**< When set, the multi-use field of control words will contain
2836 uint64_t cal_ena : 1; /**< Enable Tx calendar, else default calendar used:
2853 uint64_t mfrm_len : 13; /**< The quantity of data sent on each lane including one sync word,
2857 uint64_t brst_shrt : 7; /**< Minimum interval between burst control words, as a multiple of
2860 uint64_t lane_rev : 1; /**< Lane reversal. When enabled, lane striping is performed from
2863 uint64_t brst_max : 5; /**< Maximum size of a data burst, as a multiple of 64 byte blocks.
2866 uint64_t reserved_25_25 : 1;
2867 uint64_t cal_depth : 9; /**< Number of valid entries in the calendar. CAL_DEPTH[2:0] must
2870 uint64_t reserved_8_15 : 8;
2871 uint64_t lane_ena : 8; /**< Lane enable mask. Link is enabled if any lane is enabled. The
2885 uint64_t lane_ena : 8;
2886 uint64_t reserved_8_15 : 8;
2887 uint64_t cal_depth : 9;
2888 uint64_t reserved_25_25 : 1;
2889 uint64_t brst_max : 5;
2890 uint64_t lane_rev : 1;
2891 uint64_t brst_shrt : 7;
2892 uint64_t mfrm_len : 13;
2893 uint64_t cal_ena : 1;
2894 uint64_t mltuse_fc_ena : 1;
2895 uint64_t lnk_stats_ena : 1;
2896 uint64_t reserved_55_55 : 1;
2897 uint64_t ptrn_mode : 1;
2898 uint64_t reserved_57_60 : 4;
2899 uint64_t int_lpbk : 1;
2900 uint64_t ext_lpbk : 1;
2901 uint64_t ext_lpbk_fc : 1;
2913 uint64_t u64;
2916 uint64_t reserved_33_63 : 31;
2917 uint64_t pkt_busy : 1; /**< Tx-Link is transmitting data. */
2918 uint64_t pipe_crd_dis : 1; /**< Disable pipe credits. Should be set when PKO is configure to
2920 uint64_t ptp_delay : 5; /**< Timestamp commit delay. Must not be zero. */
2921 uint64_t skip_cnt : 4; /**< Number of skip words to insert after the scrambler state */
2922 uint64_t pkt_flush : 1; /**< Packet transmit flush. While PKT_FLUSH=1, the TxFifo will
2925 uint64_t pkt_ena : 1; /**< Packet transmit enable. When PKT_ENA=0, the Tx-Link will stop
2927 uint64_t la_mode : 1; /**< 0 = Interlaken
2929 uint64_t tx_link_fc : 1; /**< Link flow control status transmitted by the Tx-Link
2931 uint64_t rx_link_fc : 1; /**< Link flow control status received in burst/idle control words.
2934 uint64_t reserved_12_16 : 5;
2935 uint64_t tx_link_fc_jam : 1; /**< All flow control transmitted in burst/idle control words will
2938 uint64_t rx_link_fc_pkt : 1; /**< Link flow control received in burst/idle control words causes
2941 uint64_t rx_link_fc_ign : 1; /**< Ignore the link flow control status received in burst/idle
2943 uint64_t rmatch : 1; /**< Enable rate matching circuitry */
2944 uint64_t tx_mltuse : 8; /**< Multiple Use bits used when ILKx_TX_CFG[LA_MODE=0] and
2947 uint64_t tx_mltuse : 8;
2948 uint64_t rmatch : 1;
2949 uint64_t rx_link_fc_ign : 1;
2950 uint64_t rx_link_fc_pkt : 1;
2951 uint64_t tx_link_fc_jam : 1;
2952 uint64_t reserved_12_16 : 5;
2953 uint64_t rx_link_fc : 1;
2954 uint64_t tx_link_fc : 1;
2955 uint64_t la_mode : 1;
2956 uint64_t pkt_ena : 1;
2957 uint64_t pkt_flush : 1;
2958 uint64_t skip_cnt : 4;
2959 uint64_t ptp_delay : 5;
2960 uint64_t pipe_crd_dis : 1;
2961 uint64_t pkt_busy : 1;
2962 uint64_t reserved_33_63 : 31;
2968 uint64_t reserved_32_63 : 32;
2969 uint64_t pipe_crd_dis : 1; /**< Disable pipe credits. Should be set when PKO is configure to
2971 uint64_t ptp_delay : 5; /**< Timestamp commit delay. Must not be zero. */
2972 uint64_t skip_cnt : 4; /**< Number of skip words to insert after the scrambler state */
2973 uint64_t pkt_flush : 1; /**< Packet transmit flush. While PKT_FLUSH=1, the TxFifo will
2976 uint64_t pkt_ena : 1; /**< Packet transmit enable. When PKT_ENA=0, the Tx-Link will stop
2978 uint64_t la_mode : 1; /**< 0 = Interlaken
2980 uint64_t tx_link_fc : 1; /**< Link flow control status transmitted by the Tx-Link
2982 uint64_t rx_link_fc : 1; /**< Link flow control status received in burst/idle control words.
2985 uint64_t reserved_12_16 : 5;
2986 uint64_t tx_link_fc_jam : 1; /**< All flow control transmitted in burst/idle control words will
2989 uint64_t rx_link_fc_pkt : 1; /**< Link flow control received in burst/idle control words causes
2992 uint64_t rx_link_fc_ign : 1; /**< Ignore the link flow control status received in burst/idle
2994 uint64_t rmatch : 1; /**< Enable rate matching circuitry */
2995 uint64_t tx_mltuse : 8; /**< Multiple Use bits used when ILKx_TX_CFG[LA_MODE=0] and
2998 uint64_t tx_mltuse : 8;
2999 uint64_t rmatch : 1;
3000 uint64_t rx_link_fc_ign : 1;
3001 uint64_t rx_link_fc_pkt : 1;
3002 uint64_t tx_link_fc_jam : 1;
3003 uint64_t reserved_12_16 : 5;
3004 uint64_t rx_link_fc : 1;
3005 uint64_t tx_link_fc : 1;
3006 uint64_t la_mode : 1;
3007 uint64_t pkt_ena : 1;
3008 uint64_t pkt_flush : 1;
3009 uint64_t skip_cnt : 4;
3010 uint64_t ptp_delay : 5;
3011 uint64_t pipe_crd_dis : 1;
3012 uint64_t reserved_32_63 : 32;
3022 uint64_t u64;
3025 uint64_t reserved_3_63 : 61;
3026 uint64_t tx_bad_crc24 : 1; /**< Send a control word with bad CRC24. Hardware will clear this
3028 uint64_t tx_bad_ctlw2 : 1; /**< Send a control word without the control bit set */
3029 uint64_t tx_bad_ctlw1 : 1; /**< Send a data word with the control bit set */
3031 uint64_t tx_bad_ctlw1 : 1;
3032 uint64_t tx_bad_ctlw2 : 1;
3033 uint64_t tx_bad_crc24 : 1;
3034 uint64_t reserved_3_63 : 61;
3046 uint64_t u64;
3049 uint64_t status : 64; /**< IPD flow control status for backpressue id 63-0, where a 0
3053 uint64_t status : 64;
3069 uint64_t u64;
3072 uint64_t reserved_0_63 : 64;
3074 uint64_t reserved_0_63 : 64;
3086 uint64_t u64;
3089 uint64_t reserved_14_63 : 50;
3090 uint64_t inc : 6; /**< Increment to add to current index for next index. NOTE:
3093 uint64_t reserved_6_7 : 2;
3094 uint64_t index : 6; /**< Specify the group of 8 entries accessed by the next CSR
3098 uint64_t index : 6;
3099 uint64_t reserved_6_7 : 2;
3100 uint64_t inc : 6;
3101 uint64_t reserved_14_63 : 50;
3113 uint64_t u64;
3116 uint64_t reserved_23_63 : 41;
3117 uint64_t inc : 7; /**< Increment to add to current index for next index. */
3118 uint64_t reserved_7_15 : 9;
3119 uint64_t index : 7; /**< Specify the port-pipe accessed by the next CSR read/write to
3123 uint64_t index : 7;
3124 uint64_t reserved_7_15 : 9;
3125 uint64_t inc : 7;
3126 uint64_t reserved_23_63 : 41;
3138 uint64_t u64;
3141 uint64_t reserved_32_63 : 32;
3142 uint64_t clr : 1; /**< CSR read to ILK_TXx_MEM_STAT0 clears the selected counter after
3144 uint64_t reserved_24_30 : 7;
3145 uint64_t inc : 8; /**< Increment to add to current index for next index */
3146 uint64_t reserved_8_15 : 8;
3147 uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the
3150 uint64_t index : 8;
3151 uint64_t reserved_8_15 : 8;
3152 uint64_t inc : 8;
3153 uint64_t reserved_24_30 : 7;
3154 uint64_t clr : 1;
3155 uint64_t reserved_32_63 : 32;
3167 uint64_t u64;
3170 uint64_t reserved_32_63 : 32;
3171 uint64_t clr : 1; /**< CSR read to ILK_TXx_MEM_STAT1 clears the selected counter after
3173 uint64_t reserved_24_30 : 7;
3174 uint64_t inc : 8; /**< Increment to add to current index for next index */
3175 uint64_t reserved_8_15 : 8;
3176 uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the
3179 uint64_t index : 8;
3180 uint64_t reserved_8_15 : 8;
3181 uint64_t inc : 8;
3182 uint64_t reserved_24_30 : 7;
3183 uint64_t clr : 1;
3184 uint64_t reserved_32_63 : 32;
3196 uint64_t u64;
3199 uint64_t reserved_4_63 : 60;
3200 uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */
3201 uint64_t bad_pipe : 1; /**< Received a PKO port-pipe out of the range specified by
3203 uint64_t bad_seq : 1; /**< Received sequence is not SOP followed by 0 or more data cycles
3206 uint64_t txf_err : 1; /**< TX fifo parity error occurred. At EOP time, EOP_Format will
3209 uint64_t txf_err : 1;
3210 uint64_t bad_seq : 1;
3211 uint64_t bad_pipe : 1;
3212 uint64_t stat_cnt_ovfl : 1;
3213 uint64_t reserved_4_63 : 60;
3225 uint64_t u64;
3228 uint64_t reserved_4_63 : 60;
3229 uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */
3230 uint64_t bad_pipe : 1; /**< Received a PKO port-pipe out of the range specified by
3232 uint64_t bad_seq : 1; /**< Received sequence is not SOP followed by 0 or more data cycles
3235 uint64_t txf_err : 1; /**< TX fifo parity error occurred. At EOP time, EOP_Format will
3238 uint64_t txf_err : 1;
3239 uint64_t bad_seq : 1;
3240 uint64_t bad_pipe : 1;
3241 uint64_t stat_cnt_ovfl : 1;
3242 uint64_t reserved_4_63 : 60;
3263 uint64_t u64;
3266 uint64_t reserved_36_63 : 28;
3267 uint64_t entry_ctl3 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+3
3272 uint64_t reserved_33_33 : 1;
3273 uint64_t bpid3 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+3
3275 uint64_t entry_ctl2 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+2
3280 uint64_t reserved_24_24 : 1;
3281 uint64_t bpid2 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+2
3283 uint64_t entry_ctl1 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+1
3288 uint64_t reserved_15_15 : 1;
3289 uint64_t bpid1 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+1
3291 uint64_t entry_ctl0 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+0
3296 uint64_t reserved_6_6 : 1;
3297 uint64_t bpid0 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+0
3300 uint64_t bpid0 : 6;
3301 uint64_t reserved_6_6 : 1;
3302 uint64_t entry_ctl0 : 2;
3303 uint64_t bpid1 : 6;
3304 uint64_t reserved_15_15 : 1;
3305 uint64_t entry_ctl1 : 2;
3306 uint64_t bpid2 : 6;
3307 uint64_t reserved_24_24 : 1;
3308 uint64_t entry_ctl2 : 2;
3309 uint64_t bpid3 : 6;
3310 uint64_t reserved_33_33 : 1;
3311 uint64_t entry_ctl3 : 2;
3312 uint64_t reserved_36_63 : 28;
3333 uint64_t u64;
3336 uint64_t reserved_36_63 : 28;
3337 uint64_t entry_ctl7 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+7
3342 uint64_t reserved_33_33 : 1;
3343 uint64_t bpid7 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+7
3345 uint64_t entry_ctl6 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+6
3350 uint64_t reserved_24_24 : 1;
3351 uint64_t bpid6 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+6
3353 uint64_t entry_ctl5 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+5
3358 uint64_t reserved_15_15 : 1;
3359 uint64_t bpid5 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+5
3361 uint64_t entry_ctl4 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+4
3366 uint64_t reserved_6_6 : 1;
3367 uint64_t bpid4 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+4
3370 uint64_t bpid4 : 6;
3371 uint64_t reserved_6_6 : 1;
3372 uint64_t entry_ctl4 : 2;
3373 uint64_t bpid5 : 6;
3374 uint64_t reserved_15_15 : 1;
3375 uint64_t entry_ctl5 : 2;
3376 uint64_t bpid6 : 6;
3377 uint64_t reserved_24_24 : 1;
3378 uint64_t entry_ctl6 : 2;
3379 uint64_t bpid7 : 6;
3380 uint64_t reserved_33_33 : 1;
3381 uint64_t entry_ctl7 : 2;
3382 uint64_t reserved_36_63 : 28;
3394 uint64_t u64;
3397 uint64_t reserved_17_63 : 47;
3398 uint64_t remap : 1; /**< Dynamically select channel using bits[39:32] of an 8-byte
3403 uint64_t reserved_8_15 : 8;
3404 uint64_t channel : 8; /**< Specify the channel for the port-pipe selected by
3407 uint64_t channel : 8;
3408 uint64_t reserved_8_15 : 8;
3409 uint64_t remap : 1;
3410 uint64_t reserved_17_63 : 47;
3416 uint64_t reserved_8_63 : 56;
3417 uint64_t channel : 8; /**< Specify the channel for the port-pipe selected by
3420 uint64_t channel : 8;
3421 uint64_t reserved_8_63 : 56;
3431 uint64_t u64;
3434 uint64_t reserved_28_63 : 36;
3435 uint64_t tx_pkt : 28; /**< Number of packets transmitted per channel (256M)
3439 uint64_t tx_pkt : 28;
3440 uint64_t reserved_28_63 : 36;
3452 uint64_t u64;
3455 uint64_t reserved_36_63 : 28;
3456 uint64_t tx_bytes : 36; /**< Number of bytes transmitted per channel (64GB) Channel selected
3460 uint64_t tx_bytes : 36;
3461 uint64_t reserved_36_63 : 28;
3473 uint64_t u64;
3476 uint64_t reserved_24_63 : 40;
3477 uint64_t nump : 8; /**< Number of pipes assigned to this Tx Link */
3478 uint64_t reserved_7_15 : 9;
3479 uint64_t base : 7; /**< When NUMP is non-zero, indicates the base pipe number this
3490 uint64_t base : 7;
3491 uint64_t reserved_7_15 : 9;
3492 uint64_t nump : 8;
3493 uint64_t reserved_24_63 : 40;
3505 uint64_t u64;
3508 uint64_t reserved_50_63 : 14;
3509 uint64_t grnlrty : 2; /**< Granularity of a token, where 1 token equal (1<<GRNLRTY) bytes. */
3510 uint64_t brst_limit : 16; /**< Size of token bucket, also the maximum quantity of data that
3513 uint64_t time_limit : 16; /**< Number of cycles per time interval. (Must be >= 4) */
3514 uint64_t rate_limit : 16; /**< Number of tokens added to the bucket when the interval timer
3517 uint64_t rate_limit : 16;
3518 uint64_t time_limit : 16;
3519 uint64_t brst_limit : 16;
3520 uint64_t grnlrty : 2;
3521 uint64_t reserved_50_63 : 14;