Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_DFM_CHAR_CTL_FUNC(void)
68 static inline uint64_t CVMX_DFM_CHAR_MASK0_FUNC(void)
79 static inline uint64_t CVMX_DFM_CHAR_MASK2_FUNC(void)
90 static inline uint64_t CVMX_DFM_CHAR_MASK4_FUNC(void)
101 static inline uint64_t CVMX_DFM_COMP_CTL2_FUNC(void)
112 static inline uint64_t CVMX_DFM_CONFIG_FUNC(void)
123 static inline uint64_t CVMX_DFM_CONTROL_FUNC(void)
134 static inline uint64_t CVMX_DFM_DLL_CTL2_FUNC(void)
145 static inline uint64_t CVMX_DFM_DLL_CTL3_FUNC(void)
156 static inline uint64_t CVMX_DFM_FCLK_CNT_FUNC(void)
167 static inline uint64_t CVMX_DFM_FNT_BIST_FUNC(void)
178 static inline uint64_t CVMX_DFM_FNT_CTL_FUNC(void)
189 static inline uint64_t CVMX_DFM_FNT_IENA_FUNC(void)
200 static inline uint64_t CVMX_DFM_FNT_SCLK_FUNC(void)
211 static inline uint64_t CVMX_DFM_FNT_STAT_FUNC(void)
222 static inline uint64_t CVMX_DFM_IFB_CNT_FUNC(void)
233 static inline uint64_t CVMX_DFM_MODEREG_PARAMS0_FUNC(void)
244 static inline uint64_t CVMX_DFM_MODEREG_PARAMS1_FUNC(void)
255 static inline uint64_t CVMX_DFM_OPS_CNT_FUNC(void)
266 static inline uint64_t CVMX_DFM_PHY_CTL_FUNC(void)
277 static inline uint64_t CVMX_DFM_RESET_CTL_FUNC(void)
288 static inline uint64_t CVMX_DFM_RLEVEL_CTL_FUNC(void)
299 static inline uint64_t CVMX_DFM_RLEVEL_DBG_FUNC(void)
309 static inline uint64_t CVMX_DFM_RLEVEL_RANKX(unsigned long offset)
322 static inline uint64_t CVMX_DFM_RODT_MASK_FUNC(void)
333 static inline uint64_t CVMX_DFM_SLOT_CTL0_FUNC(void)
344 static inline uint64_t CVMX_DFM_SLOT_CTL1_FUNC(void)
355 static inline uint64_t CVMX_DFM_TIMING_PARAMS0_FUNC(void)
366 static inline uint64_t CVMX_DFM_TIMING_PARAMS1_FUNC(void)
377 static inline uint64_t CVMX_DFM_WLEVEL_CTL_FUNC(void)
388 static inline uint64_t CVMX_DFM_WLEVEL_DBG_FUNC(void)
398 static inline uint64_t CVMX_DFM_WLEVEL_RANKX(unsigned long offset)
411 static inline uint64_t CVMX_DFM_WODT_MASK_FUNC(void)
432 uint64_t u64;
435 uint64_t reserved_44_63 : 20;
436 uint64_t dr : 1; /**< Pattern at Data Rate (not Clock Rate) */
437 uint64_t skew_on : 1; /**< Skew adjacent bits */
438 uint64_t en : 1; /**< Enable characterization */
439 uint64_t sel : 1; /**< Pattern select
442 uint64_t prog : 8; /**< Programmable pattern */
443 uint64_t prbs : 32; /**< PRBS Polynomial */
445 uint64_t prbs : 32;
446 uint64_t prog : 8;
447 uint64_t sel : 1;
448 uint64_t en : 1;
449 uint64_t skew_on : 1;
450 uint64_t dr : 1;
451 uint64_t reserved_44_63 : 20;
456 uint64_t reserved_42_63 : 22;
457 uint64_t en : 1; /**< Enable characterization */
458 uint64_t sel : 1; /**< Pattern select
461 uint64_t prog : 8; /**< Programmable pattern */
462 uint64_t prbs : 32; /**< PRBS Polynomial */
464 uint64_t prbs : 32;
465 uint64_t prog : 8;
466 uint64_t sel : 1;
467 uint64_t en : 1;
468 uint64_t reserved_42_63 : 22;
483 uint64_t u64;
486 uint64_t reserved_16_63 : 48;
487 uint64_t mask : 16; /**< Mask for DQ0[15:0] */
489 uint64_t mask : 16;
490 uint64_t reserved_16_63 : 48;
506 uint64_t u64;
509 uint64_t reserved_16_63 : 48;
510 uint64_t mask : 16; /**< Mask for DQ1[15:0] */
512 uint64_t mask : 16;
513 uint64_t reserved_16_63 : 48;
529 uint64_t u64;
532 uint64_t reserved_33_63 : 31;
533 uint64_t reset_n_mask : 1; /**< Mask for RESET_N */
534 uint64_t a_mask : 16; /**< Mask for A[15:0] */
535 uint64_t ba_mask : 3; /**< Mask for BA[2:0] */
536 uint64_t we_n_mask : 1; /**< Mask for WE_N */
537 uint64_t cas_n_mask : 1; /**< Mask for CAS_N */
538 uint64_t ras_n_mask : 1; /**< Mask for RAS_N */
539 uint64_t odt1_mask : 2; /**< Mask for ODT1
541 uint64_t odt0_mask : 2; /**< Mask for ODT0 */
542 uint64_t cs1_n_mask : 2; /**< Mask for CS1_N
544 uint64_t cs0_n_mask : 2; /**< Mask for CS0_N */
545 uint64_t cke_mask : 2; /**< Mask for CKE
548 uint64_t cke_mask : 2;
549 uint64_t cs0_n_mask : 2;
550 uint64_t cs1_n_mask : 2;
551 uint64_t odt0_mask : 2;
552 uint64_t odt1_mask : 2;
553 uint64_t ras_n_mask : 1;
554 uint64_t cas_n_mask : 1;
555 uint64_t we_n_mask : 1;
556 uint64_t ba_mask : 3;
557 uint64_t a_mask : 16;
558 uint64_t reset_n_mask : 1;
559 uint64_t reserved_33_63 : 31;
574 uint64_t u64;
577 uint64_t reserved_34_63 : 30;
578 uint64_t ddr__ptune : 4; /**< DDR pctl from compensation circuit
581 uint64_t ddr__ntune : 4; /**< DDR nctl from compensation circuit
584 uint64_t m180 : 1; /**< Cap impedance at 180 ohm (instead of 240 ohm) */
585 uint64_t byp : 1; /**< Bypass mode
587 uint64_t ptune : 4; /**< PCTL impedance control in bypass mode */
588 uint64_t ntune : 4; /**< NCTL impedance control in bypass mode */
589 uint64_t rodt_ctl : 4; /**< NCTL RODT impedance control bits
597 uint64_t cmd_ctl : 4; /**< Drive strength control for CMD/A/RESET_N/CKE drivers
606 uint64_t ck_ctl : 4; /**< Drive strength control for CK/CS_N/ODT drivers
615 uint64_t dqx_ctl : 4; /**< Drive strength control for DQ/DQS drivers
625 uint64_t dqx_ctl : 4;
626 uint64_t ck_ctl : 4;
627 uint64_t cmd_ctl : 4;
628 uint64_t rodt_ctl : 4;
629 uint64_t ntune : 4;
630 uint64_t ptune : 4;
631 uint64_t byp : 1;
632 uint64_t m180 : 1;
633 uint64_t ddr__ntune : 4;
634 uint64_t ddr__ptune : 4;
635 uint64_t reserved_34_63 : 30;
683 uint64_t u64;
686 uint64_t reserved_59_63 : 5;
687 uint64_t early_unload_d1_r1 : 1; /**< Reserved */
688 uint64_t early_unload_d1_r0 : 1; /**< Reserved */
689 uint64_t early_unload_d0_r1 : 1; /**< When set, unload the PHY silo one cycle early for Rank 1
699 uint64_t early_unload_d0_r0 : 1; /**< When set, unload the PHY silo one cycle early for Rank 0
709 uint64_t init_status : 4; /**< Indicates status of initialization
720 uint64_t mirrmask : 4; /**< Mask determining which ranks are address-mirrored.
730 uint64_t rankmask : 4; /**< Mask to select rank to be leveled/initialized.
741 uint64_t rank_ena : 1; /**< RANK enable (for use with multiple ranks)
745 uint64_t sref_with_dll : 1; /**< Self-refresh entry/exit write MR1 and MR2
751 uint64_t early_dqx : 1; /**< Send DQx signals one CK cycle earlier for the case when
753 uint64_t sequence : 3; /**< Instruction sequence that is run after a 0->1
784 uint64_t ref_zqcs_int : 19; /**< Refresh & ZQCS interval represented in \#of 512 fclk
798 uint64_t reset : 1; /**< Reset oneshot pulse for refresh counter,
802 uint64_t ecc_adr : 1; /**< Must be zero. */
803 uint64_t forcewrite : 4; /**< Force the oldest outstanding write to complete after
805 uint64_t idlepower : 3; /**< Enter precharge power-down mode after the memory
811 uint64_t pbank_lsb : 4; /**< Physical bank address bit select
852 uint64_t row_lsb : 3; /**< Row Address bit select
886 uint64_t ecc_ena : 1; /**< Must be zero. */
887 uint64_t init_start : 1; /**< A 0->1 transition starts the DDR memory sequence that is
891 uint64_t init_start : 1;
892 uint64_t ecc_ena : 1;
893 uint64_t row_lsb : 3;
894 uint64_t pbank_lsb : 4;
895 uint64_t idlepower : 3;
896 uint64_t forcewrite : 4;
897 uint64_t ecc_adr : 1;
898 uint64_t reset : 1;
899 uint64_t ref_zqcs_int : 19;
900 uint64_t sequence : 3;
901 uint64_t early_dqx : 1;
902 uint64_t sref_with_dll : 1;
903 uint64_t rank_ena : 1;
904 uint64_t rankmask : 4;
905 uint64_t mirrmask : 4;
906 uint64_t init_status : 4;
907 uint64_t early_unload_d0_r0 : 1;
908 uint64_t early_unload_d0_r1 : 1;
909 uint64_t early_unload_d1_r0 : 1;
910 uint64_t early_unload_d1_r1 : 1;
911 uint64_t reserved_59_63 : 5;
917 uint64_t reserved_55_63 : 9;
918 uint64_t init_status : 4; /**< Indicates status of initialization
929 uint64_t mirrmask : 4; /**< Mask determining which ranks are address-mirrored.
939 uint64_t rankmask : 4; /**< Mask to select rank to be leveled/initialized.
950 uint64_t rank_ena : 1; /**< RANK enable (for use with multiple ranks)
954 uint64_t sref_with_dll : 1; /**< Self-refresh entry/exit write MR1 and MR2
960 uint64_t early_dqx : 1; /**< Send DQx signals one CK cycle earlier for the case when
962 uint64_t sequence : 3; /**< Instruction sequence that is run after a 0->1
993 uint64_t ref_zqcs_int : 19; /**< Refresh & ZQCS interval represented in \#of 512 fclk
1007 uint64_t reset : 1; /**< Reset oneshot pulse for refresh counter,
1011 uint64_t ecc_adr : 1; /**< Must be zero. */
1012 uint64_t forcewrite : 4; /**< Force the oldest outstanding write to complete after
1014 uint64_t idlepower : 3; /**< Enter precharge power-down mode after the memory
1020 uint64_t pbank_lsb : 4; /**< Physical bank address bit select
1061 uint64_t row_lsb : 3; /**< Row Address bit select
1095 uint64_t ecc_ena : 1; /**< Must be zero. */
1096 uint64_t init_start : 1; /**< A 0->1 transition starts the DDR memory sequence that is
1100 uint64_t init_start : 1;
1101 uint64_t ecc_ena : 1;
1102 uint64_t row_lsb : 3;
1103 uint64_t pbank_lsb : 4;
1104 uint64_t idlepower : 3;
1105 uint64_t forcewrite : 4;
1106 uint64_t ecc_adr : 1;
1107 uint64_t reset : 1;
1108 uint64_t ref_zqcs_int : 19;
1109 uint64_t sequence : 3;
1110 uint64_t early_dqx : 1;
1111 uint64_t sref_with_dll : 1;
1112 uint64_t rank_ena : 1;
1113 uint64_t rankmask : 4;
1114 uint64_t mirrmask : 4;
1115 uint64_t init_status : 4;
1116 uint64_t reserved_55_63 : 9;
1130 uint64_t u64;
1133 uint64_t reserved_24_63 : 40;
1134 uint64_t rodt_bprch : 1; /**< When set, the turn-off time for the ODT pin during a
1136 uint64_t wodt_bprch : 1; /**< When set, the turn-off time for the ODT pin during a
1138 uint64_t bprch : 2; /**< Back Porch Enable: When set, the turn-on time for
1145 uint64_t ext_zqcs_dis : 1; /**< Disable (external) auto-zqcs calibration
1147 uint64_t int_zqcs_dis : 1; /**< Disable (internal) auto-zqcs calibration
1150 uint64_t auto_fclkdis : 1; /**< When 1, DFM will automatically shut off its internal
1153 uint64_t xor_bank : 1; /**< Must be zero. */
1154 uint64_t max_write_batch : 4; /**< Must be set to value 8 */
1155 uint64_t nxm_write_en : 1; /**< Must be zero. */
1156 uint64_t elev_prio_dis : 1; /**< Must be zero. */
1157 uint64_t inorder_wr : 1; /**< Must be zero. */
1158 uint64_t inorder_rd : 1; /**< Must be zero. */
1159 uint64_t throttle_wr : 1; /**< When set, use at most one IFB for writes
1161 uint64_t throttle_rd : 1; /**< When set, use at most one IFB for reads
1163 uint64_t fprch2 : 2; /**< Front Porch Enable: When set, the turn-off
1169 uint64_t pocas : 1; /**< Enable the Posted CAS feature of DDR3.
1171 uint64_t ddr2t : 1; /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
1177 uint64_t bwcnt : 1; /**< Bus utilization counter Clear.
1182 uint64_t rdimm_ena : 1; /**< Must be zero. */
1184 uint64_t rdimm_ena : 1;
1185 uint64_t bwcnt : 1;
1186 uint64_t ddr2t : 1;
1187 uint64_t pocas : 1;
1188 uint64_t fprch2 : 2;
1189 uint64_t throttle_rd : 1;
1190 uint64_t throttle_wr : 1;
1191 uint64_t inorder_rd : 1;
1192 uint64_t inorder_wr : 1;
1193 uint64_t elev_prio_dis : 1;
1194 uint64_t nxm_write_en : 1;
1195 uint64_t max_write_batch : 4;
1196 uint64_t xor_bank : 1;
1197 uint64_t auto_fclkdis : 1;
1198 uint64_t int_zqcs_dis : 1;
1199 uint64_t ext_zqcs_dis : 1;
1200 uint64_t bprch : 2;
1201 uint64_t wodt_bprch : 1;
1202 uint64_t rodt_bprch : 1;
1203 uint64_t reserved_24_63 : 40;
1209 uint64_t reserved_22_63 : 42;
1210 uint64_t bprch : 2; /**< Back Porch Enable: When set, the turn-on time for
1217 uint64_t ext_zqcs_dis : 1; /**< Disable (external) auto-zqcs calibration
1219 uint64_t int_zqcs_dis : 1; /**< Disable (internal) auto-zqcs calibration
1222 uint64_t auto_fclkdis : 1; /**< When 1, DFM will automatically shut off its internal
1225 uint64_t xor_bank : 1; /**< Must be zero. */
1226 uint64_t max_write_batch : 4; /**< Must be set to value 8 */
1227 uint64_t nxm_write_en : 1; /**< Must be zero. */
1228 uint64_t elev_prio_dis : 1; /**< Must be zero. */
1229 uint64_t inorder_wr : 1; /**< Must be zero. */
1230 uint64_t inorder_rd : 1; /**< Must be zero. */
1231 uint64_t throttle_wr : 1; /**< When set, use at most one IFB for writes
1233 uint64_t throttle_rd : 1; /**< When set, use at most one IFB for reads
1235 uint64_t fprch2 : 2; /**< Front Porch Enable: When set, the turn-off
1241 uint64_t pocas : 1; /**< Enable the Posted CAS feature of DDR3.
1243 uint64_t ddr2t : 1; /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
1249 uint64_t bwcnt : 1; /**< Bus utilization counter Clear.
1254 uint64_t rdimm_ena : 1; /**< Must be zero. */
1256 uint64_t rdimm_ena : 1;
1257 uint64_t bwcnt : 1;
1258 uint64_t ddr2t : 1;
1259 uint64_t pocas : 1;
1260 uint64_t fprch2 : 2;
1261 uint64_t throttle_rd : 1;
1262 uint64_t throttle_wr : 1;
1263 uint64_t inorder_rd : 1;
1264 uint64_t inorder_wr : 1;
1265 uint64_t elev_prio_dis : 1;
1266 uint64_t nxm_write_en : 1;
1267 uint64_t max_write_batch : 4;
1268 uint64_t xor_bank : 1;
1269 uint64_t auto_fclkdis : 1;
1270 uint64_t int_zqcs_dis : 1;
1271 uint64_t ext_zqcs_dis : 1;
1272 uint64_t bprch : 2;
1273 uint64_t reserved_22_63 : 42;
1305 uint64_t u64;
1308 uint64_t reserved_15_63 : 49;
1309 uint64_t dll_bringup : 1; /**< DLL Bringup */
1310 uint64_t dreset : 1; /**< Fclk domain reset. The reset signal that is used by the
1312 uint64_t quad_dll_ena : 1; /**< DLL Enable */
1313 uint64_t byp_sel : 4; /**< Bypass select
1320 uint64_t byp_setting : 8; /**< Bypass setting
1328 uint64_t byp_setting : 8;
1329 uint64_t byp_sel : 4;
1330 uint64_t quad_dll_ena : 1;
1331 uint64_t dreset : 1;
1332 uint64_t dll_bringup : 1;
1333 uint64_t reserved_15_63 : 49;
1349 uint64_t u64;
1352 uint64_t reserved_29_63 : 35;
1353 uint64_t dll_fast : 1; /**< DLL lock
1355 uint64_t dll90_setting : 8; /**< Encoded DLL settings. Works in conjuction with
1357 uint64_t fine_tune_mode : 1; /**< Fine Tune Mode */
1358 uint64_t dll_mode : 1; /**< DLL Mode */
1359 uint64_t dll90_byte_sel : 4; /**< Observe DLL settings for selected byte
1364 uint64_t offset_ena : 1; /**< Offset enable
1367 uint64_t load_offset : 1; /**< Load offset
1372 uint64_t mode_sel : 2; /**< Mode select
1377 uint64_t byte_sel : 4; /**< Byte select
1384 uint64_t offset : 6; /**< Write/read offset setting
1389 uint64_t offset : 6;
1390 uint64_t byte_sel : 4;
1391 uint64_t mode_sel : 2;
1392 uint64_t load_offset : 1;
1393 uint64_t offset_ena : 1;
1394 uint64_t dll90_byte_sel : 4;
1395 uint64_t dll_mode : 1;
1396 uint64_t fine_tune_mode : 1;
1397 uint64_t dll90_setting : 8;
1398 uint64_t dll_fast : 1;
1399 uint64_t reserved_29_63 : 35;
1415 uint64_t u64;
1418 uint64_t fclkcnt : 64; /**< Performance Counter that counts fclks
1421 uint64_t fclkcnt : 64;
1438 uint64_t u64;
1441 uint64_t reserved_5_63 : 59;
1442 uint64_t cab : 1; /**< Bist Results for CAB RAM
1445 uint64_t mrq : 1; /**< Bist Results for MRQ RAM
1448 uint64_t mff : 1; /**< Bist Results for MFF RAM
1451 uint64_t rpb : 1; /**< Bist Results for RPB RAM
1454 uint64_t mwb : 1; /**< Bist Results for MWB RAM
1458 uint64_t mwb : 1;
1459 uint64_t rpb : 1;
1460 uint64_t mff : 1;
1461 uint64_t mrq : 1;
1462 uint64_t cab : 1;
1463 uint64_t reserved_5_63 : 59;
1469 uint64_t reserved_4_63 : 60;
1470 uint64_t mrq : 1; /**< Bist Results for MRQ RAM
1473 uint64_t mff : 1; /**< Bist Results for MFF RAM
1476 uint64_t rpb : 1; /**< Bist Results for RPB RAM
1479 uint64_t mwb : 1; /**< Bist Results for MWB RAM
1483 uint64_t mwb : 1;
1484 uint64_t rpb : 1;
1485 uint64_t mff : 1;
1486 uint64_t mrq : 1;
1487 uint64_t reserved_4_63 : 60;
1504 uint64_t u64;
1507 uint64_t reserved_4_63 : 60;
1508 uint64_t sbe_ena : 1; /**< If SBE_ENA=1 & RECC_ENA=1 then all single bit errors
1524 uint64_t wecc_ena : 1; /**< If WECC_ENA=1, HW will auto-generate(overwrite) the 10b
1533 uint64_t recc_ena : 1; /**< If RECC_ENA=1, all DFA memory reads sourced by 1) DFA
1550 uint64_t dfr_ena : 1; /**< DFM Memory Interface Enable
1562 uint64_t dfr_ena : 1;
1563 uint64_t recc_ena : 1;
1564 uint64_t wecc_ena : 1;
1565 uint64_t sbe_ena : 1;
1566 uint64_t reserved_4_63 : 60;
1583 uint64_t u64;
1586 uint64_t reserved_2_63 : 62;
1587 uint64_t dbe_intena : 1; /**< OWECC Double Error Detected(DED) Interrupt Enable
1591 uint64_t sbe_intena : 1; /**< OWECC Single Error Corrected(SEC) Interrupt Enable
1597 uint64_t sbe_intena : 1;
1598 uint64_t dbe_intena : 1;
1599 uint64_t reserved_2_63 : 62;
1619 uint64_t u64;
1622 uint64_t reserved_3_63 : 61;
1623 uint64_t clear_bist : 1; /**< When START_BIST is written 0->1, if CLEAR_BIST=1, all
1630 uint64_t bist_start : 1; /**< When software writes BIST_START=0->1, a BiST is executed
1639 uint64_t sclkdis : 1; /**< DFM sclk disable Source
1645 uint64_t sclkdis : 1;
1646 uint64_t bist_start : 1;
1647 uint64_t clear_bist : 1;
1648 uint64_t reserved_3_63 : 61;
1665 uint64_t u64;
1668 uint64_t reserved_42_63 : 22;
1669 uint64_t fsyn : 10; /**< Failing Syndrome
1680 uint64_t fadr : 28; /**< Failing Memory octaword address
1691 uint64_t reserved_2_3 : 2;
1692 uint64_t dbe_err : 1; /**< Double bit error detected(uncorrectable) during
1695 uint64_t sbe_err : 1; /**< Single bit error detected(corrected) during
1699 uint64_t sbe_err : 1;
1700 uint64_t dbe_err : 1;
1701 uint64_t reserved_2_3 : 2;
1702 uint64_t fadr : 28;
1703 uint64_t fsyn : 10;
1704 uint64_t reserved_42_63 : 22;
1720 uint64_t u64;
1723 uint64_t ifbcnt : 64; /**< Performance Counter
1728 uint64_t ifbcnt : 64;
1745 uint64_t u64;
1748 uint64_t reserved_25_63 : 39;
1749 uint64_t ppd : 1; /**< DLL Control for precharge powerdown
1757 uint64_t wrp : 3; /**< Write recovery for auto precharge
1773 uint64_t dllr : 1; /**< DLL Reset
1779 uint64_t tm : 1; /**< Test Mode
1785 uint64_t rbt : 1; /**< Read Burst Type
1792 uint64_t cl : 4; /**< CAS Latency
1811 uint64_t bl : 2; /**< Burst Length
1818 uint64_t qoff : 1; /**< Qoff Enable
1829 uint64_t tdqs : 1; /**< TDQS Enable
1838 uint64_t wlev : 1; /**< Write Leveling Enable
1850 uint64_t al : 2; /**< Additive Latency
1865 uint64_t dll : 1; /**< DLL Enable
1879 uint64_t mpr : 1; /**< MPR
1888 uint64_t mprloc : 2; /**< MPR Location
1896 uint64_t cwl : 3; /**< CAS Write Latency
1915 uint64_t cwl : 3;
1916 uint64_t mprloc : 2;
1917 uint64_t mpr : 1;
1918 uint64_t dll : 1;
1919 uint64_t al : 2;
1920 uint64_t wlev : 1;
1921 uint64_t tdqs : 1;
1922 uint64_t qoff : 1;
1923 uint64_t bl : 2;
1924 uint64_t cl : 4;
1925 uint64_t rbt : 1;
1926 uint64_t tm : 1;
1927 uint64_t dllr : 1;
1928 uint64_t wrp : 3;
1929 uint64_t ppd : 1;
1930 uint64_t reserved_25_63 : 39;
1947 uint64_t u64;
1950 uint64_t reserved_48_63 : 16;
1951 uint64_t rtt_nom_11 : 3; /**< Must be zero */
1952 uint64_t dic_11 : 2; /**< Must be zero */
1953 uint64_t rtt_wr_11 : 2; /**< Must be zero */
1954 uint64_t srt_11 : 1; /**< Must be zero */
1955 uint64_t asr_11 : 1; /**< Must be zero */
1956 uint64_t pasr_11 : 3; /**< Must be zero */
1957 uint64_t rtt_nom_10 : 3; /**< Must be zero */
1958 uint64_t dic_10 : 2; /**< Must be zero */
1959 uint64_t rtt_wr_10 : 2; /**< Must be zero */
1960 uint64_t srt_10 : 1; /**< Must be zero */
1961 uint64_t asr_10 : 1; /**< Must be zero */
1962 uint64_t pasr_10 : 3; /**< Must be zero */
1963 uint64_t rtt_nom_01 : 3; /**< RTT_NOM Rank 1
1971 uint64_t dic_01 : 2; /**< Output Driver Impedance Control Rank 1
1979 uint64_t rtt_wr_01 : 2; /**< RTT_WR Rank 1
1987 uint64_t srt_01 : 1; /**< Self-refresh temperature range Rank 1
1995 uint64_t asr_01 : 1; /**< Auto self-refresh Rank 1
2003 uint64_t pasr_01 : 3; /**< Partial array self-refresh Rank 1
2011 uint64_t rtt_nom_00 : 3; /**< RTT_NOM Rank 0
2019 uint64_t dic_00 : 2; /**< Output Driver Impedance Control Rank 0
2027 uint64_t rtt_wr_00 : 2; /**< RTT_WR Rank 0
2035 uint64_t srt_00 : 1; /**< Self-refresh temperature range Rank 0
2043 uint64_t asr_00 : 1; /**< Auto self-refresh Rank 0
2051 uint64_t pasr_00 : 3; /**< Partial array self-refresh Rank 0
2060 uint64_t pasr_00 : 3;
2061 uint64_t asr_00 : 1;
2062 uint64_t srt_00 : 1;
2063 uint64_t rtt_wr_00 : 2;
2064 uint64_t dic_00 : 2;
2065 uint64_t rtt_nom_00 : 3;
2066 uint64_t pasr_01 : 3;
2067 uint64_t asr_01 : 1;
2068 uint64_t srt_01 : 1;
2069 uint64_t rtt_wr_01 : 2;
2070 uint64_t dic_01 : 2;
2071 uint64_t rtt_nom_01 : 3;
2072 uint64_t pasr_10 : 3;
2073 uint64_t asr_10 : 1;
2074 uint64_t srt_10 : 1;
2075 uint64_t rtt_wr_10 : 2;
2076 uint64_t dic_10 : 2;
2077 uint64_t rtt_nom_10 : 3;
2078 uint64_t pasr_11 : 3;
2079 uint64_t asr_11 : 1;
2080 uint64_t srt_11 : 1;
2081 uint64_t rtt_wr_11 : 2;
2082 uint64_t dic_11 : 2;
2083 uint64_t rtt_nom_11 : 3;
2084 uint64_t reserved_48_63 : 16;
2100 uint64_t u64;
2103 uint64_t opscnt : 64; /**< Performance Counter
2109 uint64_t opscnt : 64;
2125 uint64_t u64;
2128 uint64_t reserved_15_63 : 49;
2129 uint64_t rx_always_on : 1; /**< Disable dynamic DDR3 IO Rx power gating */
2130 uint64_t lv_mode : 1; /**< Low Voltage Mode (1.35V) */
2131 uint64_t ck_tune1 : 1; /**< Clock Tune
2134 uint64_t ck_dlyout1 : 4; /**< Clock delay out setting
2137 uint64_t ck_tune0 : 1; /**< Clock Tune */
2138 uint64_t ck_dlyout0 : 4; /**< Clock delay out setting */
2139 uint64_t loopback : 1; /**< Loopback enable */
2140 uint64_t loopback_pos : 1; /**< Loopback pos mode */
2141 uint64_t ts_stagger : 1; /**< TS Staggermode
2151 uint64_t ts_stagger : 1;
2152 uint64_t loopback_pos : 1;
2153 uint64_t loopback : 1;
2154 uint64_t ck_dlyout0 : 4;
2155 uint64_t ck_tune0 : 1;
2156 uint64_t ck_dlyout1 : 4;
2157 uint64_t ck_tune1 : 1;
2158 uint64_t lv_mode : 1;
2159 uint64_t rx_always_on : 1;
2160 uint64_t reserved_15_63 : 49;
2166 uint64_t reserved_14_63 : 50;
2167 uint64_t lv_mode : 1; /**< Low Voltage Mode (1.35V) */
2168 uint64_t ck_tune1 : 1; /**< Clock Tune
2171 uint64_t ck_dlyout1 : 4; /**< Clock delay out setting
2174 uint64_t ck_tune0 : 1; /**< Clock Tune */
2175 uint64_t ck_dlyout0 : 4; /**< Clock delay out setting */
2176 uint64_t loopback : 1; /**< Loopback enable */
2177 uint64_t loopback_pos : 1; /**< Loopback pos mode */
2178 uint64_t ts_stagger : 1; /**< TS Staggermode
2188 uint64_t ts_stagger : 1;
2189 uint64_t loopback_pos : 1;
2190 uint64_t loopback : 1;
2191 uint64_t ck_dlyout0 : 4;
2192 uint64_t ck_tune0 : 1;
2193 uint64_t ck_dlyout1 : 4;
2194 uint64_t ck_tune1 : 1;
2195 uint64_t lv_mode : 1;
2196 uint64_t reserved_14_63 : 50;
2224 uint64_t u64;
2227 uint64_t reserved_4_63 : 60;
2228 uint64_t ddr3psv : 1; /**< Must be zero */
2229 uint64_t ddr3psoft : 1; /**< Must be zero */
2230 uint64_t ddr3pwarm : 1; /**< Must be zero */
2231 uint64_t ddr3rst : 1; /**< Memory Reset
2235 uint64_t ddr3rst : 1;
2236 uint64_t ddr3pwarm : 1;
2237 uint64_t ddr3psoft : 1;
2238 uint64_t ddr3psv : 1;
2239 uint64_t reserved_4_63 : 60;
2252 uint64_t u64;
2255 uint64_t reserved_22_63 : 42;
2256 uint64_t delay_unload_3 : 1; /**< When set, unload the PHY silo one cycle later
2259 uint64_t delay_unload_2 : 1; /**< When set, unload the PHY silo one cycle later
2262 uint64_t delay_unload_1 : 1; /**< When set, unload the PHY silo one cycle later
2265 uint64_t delay_unload_0 : 1; /**< When set, unload the PHY silo one cycle later
2268 uint64_t bitmask : 8; /**< Mask to select bit lanes on which read-leveling
2270 uint64_t or_dis : 1; /**< Disable or'ing of bits in a byte lane when computing
2273 uint64_t offset_en : 1; /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read
2275 uint64_t offset : 4; /**< Pick final_setting-offset (if set) for the read level
2278 uint64_t byte : 4; /**< 0 <= BYTE <= 1
2282 uint64_t byte : 4;
2283 uint64_t offset : 4;
2284 uint64_t offset_en : 1;
2285 uint64_t or_dis : 1;
2286 uint64_t bitmask : 8;
2287 uint64_t delay_unload_0 : 1;
2288 uint64_t delay_unload_1 : 1;
2289 uint64_t delay_unload_2 : 1;
2290 uint64_t delay_unload_3 : 1;
2291 uint64_t reserved_22_63 : 42;
2297 uint64_t reserved_9_63 : 55;
2298 uint64_t offset_en : 1; /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read
2300 uint64_t offset : 4; /**< Pick final_setting-offset (if set) for the read level
2303 uint64_t byte : 4; /**< 0 <= BYTE <= 1
2307 uint64_t byte : 4;
2308 uint64_t offset : 4;
2309 uint64_t offset_en : 1;
2310 uint64_t reserved_9_63 : 55;
2330 uint64_t u64;
2333 uint64_t bitmask : 64; /**< Bitmask generated during deskew settings sweep
2338 uint64_t bitmask : 64;
2365 uint64_t u64;
2368 uint64_t reserved_56_63 : 8;
2369 uint64_t status : 2; /**< Indicates status of the read-levelling and where
2375 uint64_t reserved_12_53 : 42;
2376 uint64_t byte1 : 6; /**< Deskew setting */
2377 uint64_t byte0 : 6; /**< Deskew setting */
2379 uint64_t byte0 : 6;
2380 uint64_t byte1 : 6;
2381 uint64_t reserved_12_53 : 42;
2382 uint64_t status : 2;
2383 uint64_t reserved_56_63 : 8;
2433 uint64_t u64;
2436 uint64_t rodt_d3_r1 : 8; /**< Must be zero. */
2437 uint64_t rodt_d3_r0 : 8; /**< Must be zero. */
2438 uint64_t rodt_d2_r1 : 8; /**< Must be zero. */
2439 uint64_t rodt_d2_r0 : 8; /**< Must be zero. */
2440 uint64_t rodt_d1_r1 : 8; /**< Must be zero. */
2441 uint64_t rodt_d1_r0 : 8; /**< Must be zero. */
2442 uint64_t rodt_d0_r1 : 8; /**< Read ODT mask RANK1
2445 uint64_t rodt_d0_r0 : 8; /**< Read ODT mask RANK0
2449 uint64_t rodt_d0_r0 : 8;
2450 uint64_t rodt_d0_r1 : 8;
2451 uint64_t rodt_d1_r0 : 8;
2452 uint64_t rodt_d1_r1 : 8;
2453 uint64_t rodt_d2_r0 : 8;
2454 uint64_t rodt_d2_r1 : 8;
2455 uint64_t rodt_d3_r0 : 8;
2456 uint64_t rodt_d3_r1 : 8;
2478 uint64_t u64;
2481 uint64_t reserved_24_63 : 40;
2482 uint64_t w2w_init : 6; /**< Write-to-write spacing control
2484 uint64_t w2r_init : 6; /**< Write-to-read spacing control
2486 uint64_t r2w_init : 6; /**< Read-to-write spacing control
2488 uint64_t r2r_init : 6; /**< Read-to-read spacing control
2491 uint64_t r2r_init : 6;
2492 uint64_t r2w_init : 6;
2493 uint64_t w2r_init : 6;
2494 uint64_t w2w_init : 6;
2495 uint64_t reserved_24_63 : 40;
2517 uint64_t u64;
2520 uint64_t reserved_24_63 : 40;
2521 uint64_t w2w_xrank_init : 6; /**< Write-to-write spacing control
2523 uint64_t w2r_xrank_init : 6; /**< Write-to-read spacing control
2525 uint64_t r2w_xrank_init : 6; /**< Read-to-write spacing control
2527 uint64_t r2r_xrank_init : 6; /**< Read-to-read spacing control
2530 uint64_t r2r_xrank_init : 6;
2531 uint64_t r2w_xrank_init : 6;
2532 uint64_t w2r_xrank_init : 6;
2533 uint64_t w2w_xrank_init : 6;
2534 uint64_t reserved_24_63 : 40;
2547 uint64_t u64;
2550 uint64_t reserved_47_63 : 17;
2551 uint64_t trp_ext : 1; /**< Indicates tRP constraints.
2558 uint64_t tcksre : 4; /**< Indicates tCKSRE constraints.
2563 uint64_t trp : 4; /**< Indicates tRP constraints.
2570 uint64_t tzqinit : 4; /**< Indicates tZQINIT constraints.
2575 uint64_t tdllk : 4; /**< Indicates tDLLk constraints.
2582 uint64_t tmod : 4; /**< Indicates tMOD constraints.
2587 uint64_t tmrd : 4; /**< Indicates tMRD constraints.
2592 uint64_t txpr : 4; /**< Indicates tXPR constraints.
2597 uint64_t tcke : 4; /**< Indicates tCKE constraints.
2602 uint64_t tzqcs : 4; /**< Indicates tZQCS constraints.
2607 uint64_t tckeon : 10; /**< Reserved. Should be written to zero. */
2609 uint64_t tckeon : 10;
2610 uint64_t tzqcs : 4;
2611 uint64_t tcke : 4;
2612 uint64_t txpr : 4;
2613 uint64_t tmrd : 4;
2614 uint64_t tmod : 4;
2615 uint64_t tdllk : 4;
2616 uint64_t tzqinit : 4;
2617 uint64_t trp : 4;
2618 uint64_t tcksre : 4;
2619 uint64_t trp_ext : 1;
2620 uint64_t reserved_47_63 : 17;
2625 uint64_t reserved_47_63 : 17;
2626 uint64_t trp_ext : 1; /**< Indicates tRP constraints.
2633 uint64_t tcksre : 4; /**< Indicates tCKSRE constraints.
2638 uint64_t trp : 4; /**< Indicates tRP constraints.
2645 uint64_t tzqinit : 4; /**< Indicates tZQINIT constraints.
2650 uint64_t tdllk : 4; /**< Indicates tDLLk constraints.
2657 uint64_t tmod : 4; /**< Indicates tMOD constraints.
2662 uint64_t tmrd : 4; /**< Indicates tMRD constraints.
2667 uint64_t txpr : 4; /**< Indicates tXPR constraints.
2672 uint64_t tcke : 4; /**< Indicates tCKE constraints.
2677 uint64_t tzqcs : 4; /**< Indicates tZQCS constraints.
2682 uint64_t reserved_0_9 : 10;
2684 uint64_t reserved_0_9 : 10;
2685 uint64_t tzqcs : 4;
2686 uint64_t tcke : 4;
2687 uint64_t txpr : 4;
2688 uint64_t tmrd : 4;
2689 uint64_t tmod : 4;
2690 uint64_t tdllk : 4;
2691 uint64_t tzqinit : 4;
2692 uint64_t trp : 4;
2693 uint64_t tcksre : 4;
2694 uint64_t trp_ext : 1;
2695 uint64_t reserved_47_63 : 17;
2700 uint64_t reserved_46_63 : 18;
2701 uint64_t tcksre : 4; /**< Indicates tCKSRE constraints.
2706 uint64_t trp : 4; /**< Indicates tRP constraints.
2713 uint64_t tzqinit : 4; /**< Indicates tZQINIT constraints.
2718 uint64_t tdllk : 4; /**< Indicates tDLLk constraints.
2725 uint64_t tmod : 4; /**< Indicates tMOD constraints.
2730 uint64_t tmrd : 4; /**< Indicates tMRD constraints.
2735 uint64_t txpr : 4; /**< Indicates tXPR constraints.
2740 uint64_t tcke : 4; /**< Indicates tCKE constraints.
2745 uint64_t tzqcs : 4; /**< Indicates tZQCS constraints.
2750 uint64_t tckeon : 10; /**< Reserved. Should be written to zero. */
2752 uint64_t tckeon : 10;
2753 uint64_t tzqcs : 4;
2754 uint64_t tcke : 4;
2755 uint64_t txpr : 4;
2756 uint64_t tmrd : 4;
2757 uint64_t tmod : 4;
2758 uint64_t tdllk : 4;
2759 uint64_t tzqinit : 4;
2760 uint64_t trp : 4;
2761 uint64_t tcksre : 4;
2762 uint64_t reserved_46_63 : 18;
2773 uint64_t u64;
2776 uint64_t reserved_47_63 : 17;
2777 uint64_t tras_ext : 1; /**< Indicates tRAS constraints.
2787 uint64_t txpdll : 5; /**< Indicates tXPDLL constraints.
2792 uint64_t tfaw : 5; /**< Indicates tFAW constraints.
2797 uint64_t twldqsen : 4; /**< Indicates tWLDQSEN constraints.
2802 uint64_t twlmrd : 4; /**< Indicates tWLMRD constraints.
2807 uint64_t txp : 3; /**< Indicates tXP constraints.
2812 uint64_t trrd : 3; /**< Indicates tRRD constraints.
2822 uint64_t trfc : 5; /**< Indicates tRFC constraints.
2835 uint64_t twtr : 4; /**< Indicates tWTR constraints.
2845 uint64_t trcd : 4; /**< Indicates tRCD constraints.
2858 uint64_t tras : 5; /**< Indicates tRAS constraints.
2868 uint64_t tmprr : 4; /**< Indicates tMPRR constraints.
2874 uint64_t tmprr : 4;
2875 uint64_t tras : 5;
2876 uint64_t trcd : 4;
2877 uint64_t twtr : 4;
2878 uint64_t trfc : 5;
2879 uint64_t trrd : 3;
2880 uint64_t txp : 3;
2881 uint64_t twlmrd : 4;
2882 uint64_t twldqsen : 4;
2883 uint64_t tfaw : 5;
2884 uint64_t txpdll : 5;
2885 uint64_t tras_ext : 1;
2886 uint64_t reserved_47_63 : 17;
2892 uint64_t reserved_46_63 : 18;
2893 uint64_t txpdll : 5; /**< Indicates tXPDLL constraints.
2898 uint64_t tfaw : 5; /**< Indicates tFAW constraints.
2903 uint64_t twldqsen : 4; /**< Indicates tWLDQSEN constraints.
2908 uint64_t twlmrd : 4; /**< Indicates tWLMRD constraints.
2913 uint64_t txp : 3; /**< Indicates tXP constraints.
2918 uint64_t trrd : 3; /**< Indicates tRRD constraints.
2928 uint64_t trfc : 5; /**< Indicates tRFC constraints.
2941 uint64_t twtr : 4; /**< Indicates tWTR constraints.
2951 uint64_t trcd : 4; /**< Indicates tRCD constraints.
2964 uint64_t tras : 5; /**< Indicates tRAS constraints.
2974 uint64_t tmprr : 4; /**< Indicates tMPRR constraints.
2980 uint64_t tmprr : 4;
2981 uint64_t tras : 5;
2982 uint64_t trcd : 4;
2983 uint64_t twtr : 4;
2984 uint64_t trfc : 5;
2985 uint64_t trrd : 3;
2986 uint64_t txp : 3;
2987 uint64_t twlmrd : 4;
2988 uint64_t twldqsen : 4;
2989 uint64_t tfaw : 5;
2990 uint64_t txpdll : 5;
2991 uint64_t reserved_46_63 : 18;
3002 uint64_t u64;
3005 uint64_t reserved_22_63 : 42;
3006 uint64_t rtt_nom : 3; /**< RTT_NOM
3019 uint64_t bitmask : 8; /**< Mask to select bit lanes on which write-leveling
3021 uint64_t or_dis : 1; /**< Disable or'ing of bits in a byte lane when computing
3023 uint64_t sset : 1; /**< Run write-leveling on the current setting only. */
3024 uint64_t lanemask : 9; /**< One-hot mask to select byte lane to be leveled by
3030 uint64_t lanemask : 9;
3031 uint64_t sset : 1;
3032 uint64_t or_dis : 1;
3033 uint64_t bitmask : 8;
3034 uint64_t rtt_nom : 3;
3035 uint64_t reserved_22_63 : 42;
3041 uint64_t reserved_10_63 : 54;
3042 uint64_t sset : 1; /**< Run write-leveling on the current setting only. */
3043 uint64_t lanemask : 9; /**< One-hot mask to select byte lane to be leveled by
3049 uint64_t lanemask : 9;
3050 uint64_t sset : 1;
3051 uint64_t reserved_10_63 : 54;
3071 uint64_t u64;
3074 uint64_t reserved_12_63 : 52;
3075 uint64_t bitmask : 8; /**< Bitmask generated during deskew settings sweep
3085 uint64_t byte : 4; /**< 0 <= BYTE <= 8 */
3087 uint64_t byte : 4;
3088 uint64_t bitmask : 8;
3089 uint64_t reserved_12_63 : 52;
3121 uint64_t u64;
3124 uint64_t reserved_47_63 : 17;
3125 uint64_t status : 2; /**< Indicates status of the write-leveling and where
3132 uint64_t reserved_10_44 : 35;
3133 uint64_t byte1 : 5; /**< Deskew setting
3135 uint64_t byte0 : 5; /**< Deskew setting
3138 uint64_t byte0 : 5;
3139 uint64_t byte1 : 5;
3140 uint64_t reserved_10_44 : 35;
3141 uint64_t status : 2;
3142 uint64_t reserved_47_63 : 17;
3187 uint64_t u64;
3190 uint64_t wodt_d3_r1 : 8; /**< Not used by DFM. */
3191 uint64_t wodt_d3_r0 : 8; /**< Not used by DFM. */
3192 uint64_t wodt_d2_r1 : 8; /**< Not used by DFM. */
3193 uint64_t wodt_d2_r0 : 8; /**< Not used by DFM. */
3194 uint64_t wodt_d1_r1 : 8; /**< Not used by DFM. */
3195 uint64_t wodt_d1_r0 : 8; /**< Not used by DFM. */
3196 uint64_t wodt_d0_r1 : 8; /**< Write ODT mask RANK1
3199 uint64_t wodt_d0_r0 : 8; /**< Write ODT mask RANK0
3202 uint64_t wodt_d0_r0 : 8;
3203 uint64_t wodt_d0_r1 : 8;
3204 uint64_t wodt_d1_r0 : 8;
3205 uint64_t wodt_d1_r1 : 8;
3206 uint64_t wodt_d2_r0 : 8;
3207 uint64_t wodt_d2_r1 : 8;
3208 uint64_t wodt_d3_r0 : 8;
3209 uint64_t wodt_d3_r1 : 8;