Lines Matching refs:CVMX_ADD_IO_SEG
61 return CVMX_ADD_IO_SEG(0x00011800D4000220ull);
64 #define CVMX_DFM_CHAR_CTL (CVMX_ADD_IO_SEG(0x00011800D4000220ull))
72 return CVMX_ADD_IO_SEG(0x00011800D4000228ull);
75 #define CVMX_DFM_CHAR_MASK0 (CVMX_ADD_IO_SEG(0x00011800D4000228ull))
83 return CVMX_ADD_IO_SEG(0x00011800D4000238ull);
86 #define CVMX_DFM_CHAR_MASK2 (CVMX_ADD_IO_SEG(0x00011800D4000238ull))
94 return CVMX_ADD_IO_SEG(0x00011800D4000318ull);
97 #define CVMX_DFM_CHAR_MASK4 (CVMX_ADD_IO_SEG(0x00011800D4000318ull))
105 return CVMX_ADD_IO_SEG(0x00011800D40001B8ull);
108 #define CVMX_DFM_COMP_CTL2 (CVMX_ADD_IO_SEG(0x00011800D40001B8ull))
116 return CVMX_ADD_IO_SEG(0x00011800D4000188ull);
119 #define CVMX_DFM_CONFIG (CVMX_ADD_IO_SEG(0x00011800D4000188ull))
127 return CVMX_ADD_IO_SEG(0x00011800D4000190ull);
130 #define CVMX_DFM_CONTROL (CVMX_ADD_IO_SEG(0x00011800D4000190ull))
138 return CVMX_ADD_IO_SEG(0x00011800D40001C8ull);
141 #define CVMX_DFM_DLL_CTL2 (CVMX_ADD_IO_SEG(0x00011800D40001C8ull))
149 return CVMX_ADD_IO_SEG(0x00011800D4000218ull);
152 #define CVMX_DFM_DLL_CTL3 (CVMX_ADD_IO_SEG(0x00011800D4000218ull))
160 return CVMX_ADD_IO_SEG(0x00011800D40001E0ull);
163 #define CVMX_DFM_FCLK_CNT (CVMX_ADD_IO_SEG(0x00011800D40001E0ull))
171 return CVMX_ADD_IO_SEG(0x00011800D40007F8ull);
174 #define CVMX_DFM_FNT_BIST (CVMX_ADD_IO_SEG(0x00011800D40007F8ull))
182 return CVMX_ADD_IO_SEG(0x00011800D4000400ull);
185 #define CVMX_DFM_FNT_CTL (CVMX_ADD_IO_SEG(0x00011800D4000400ull))
193 return CVMX_ADD_IO_SEG(0x00011800D4000410ull);
196 #define CVMX_DFM_FNT_IENA (CVMX_ADD_IO_SEG(0x00011800D4000410ull))
204 return CVMX_ADD_IO_SEG(0x00011800D4000418ull);
207 #define CVMX_DFM_FNT_SCLK (CVMX_ADD_IO_SEG(0x00011800D4000418ull))
215 return CVMX_ADD_IO_SEG(0x00011800D4000408ull);
218 #define CVMX_DFM_FNT_STAT (CVMX_ADD_IO_SEG(0x00011800D4000408ull))
226 return CVMX_ADD_IO_SEG(0x00011800D40001D0ull);
229 #define CVMX_DFM_IFB_CNT (CVMX_ADD_IO_SEG(0x00011800D40001D0ull))
237 return CVMX_ADD_IO_SEG(0x00011800D40001A8ull);
240 #define CVMX_DFM_MODEREG_PARAMS0 (CVMX_ADD_IO_SEG(0x00011800D40001A8ull))
248 return CVMX_ADD_IO_SEG(0x00011800D4000260ull);
251 #define CVMX_DFM_MODEREG_PARAMS1 (CVMX_ADD_IO_SEG(0x00011800D4000260ull))
259 return CVMX_ADD_IO_SEG(0x00011800D40001D8ull);
262 #define CVMX_DFM_OPS_CNT (CVMX_ADD_IO_SEG(0x00011800D40001D8ull))
270 return CVMX_ADD_IO_SEG(0x00011800D4000210ull);
273 #define CVMX_DFM_PHY_CTL (CVMX_ADD_IO_SEG(0x00011800D4000210ull))
281 return CVMX_ADD_IO_SEG(0x00011800D4000180ull);
284 #define CVMX_DFM_RESET_CTL (CVMX_ADD_IO_SEG(0x00011800D4000180ull))
292 return CVMX_ADD_IO_SEG(0x00011800D40002A0ull);
295 #define CVMX_DFM_RLEVEL_CTL (CVMX_ADD_IO_SEG(0x00011800D40002A0ull))
303 return CVMX_ADD_IO_SEG(0x00011800D40002A8ull);
306 #define CVMX_DFM_RLEVEL_DBG (CVMX_ADD_IO_SEG(0x00011800D40002A8ull))
315 return CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8;
318 #define CVMX_DFM_RLEVEL_RANKX(offset) (CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8)
326 return CVMX_ADD_IO_SEG(0x00011800D4000268ull);
329 #define CVMX_DFM_RODT_MASK (CVMX_ADD_IO_SEG(0x00011800D4000268ull))
337 return CVMX_ADD_IO_SEG(0x00011800D40001F8ull);
340 #define CVMX_DFM_SLOT_CTL0 (CVMX_ADD_IO_SEG(0x00011800D40001F8ull))
348 return CVMX_ADD_IO_SEG(0x00011800D4000200ull);
351 #define CVMX_DFM_SLOT_CTL1 (CVMX_ADD_IO_SEG(0x00011800D4000200ull))
359 return CVMX_ADD_IO_SEG(0x00011800D4000198ull);
362 #define CVMX_DFM_TIMING_PARAMS0 (CVMX_ADD_IO_SEG(0x00011800D4000198ull))
370 return CVMX_ADD_IO_SEG(0x00011800D40001A0ull);
373 #define CVMX_DFM_TIMING_PARAMS1 (CVMX_ADD_IO_SEG(0x00011800D40001A0ull))
381 return CVMX_ADD_IO_SEG(0x00011800D4000300ull);
384 #define CVMX_DFM_WLEVEL_CTL (CVMX_ADD_IO_SEG(0x00011800D4000300ull))
392 return CVMX_ADD_IO_SEG(0x00011800D4000308ull);
395 #define CVMX_DFM_WLEVEL_DBG (CVMX_ADD_IO_SEG(0x00011800D4000308ull))
404 return CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8;
407 #define CVMX_DFM_WLEVEL_RANKX(offset) (CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8)
415 return CVMX_ADD_IO_SEG(0x00011800D40001B0ull);
418 #define CVMX_DFM_WODT_MASK (CVMX_ADD_IO_SEG(0x00011800D40001B0ull))