Lines Matching refs:uint64_t
95 volatile uint64_t remote_controlled;
96 uint64_t regs[32];
97 uint64_t lo;
98 uint64_t hi;
110 uint64_t index;
111 uint64_t entrylo[2];
112 uint64_t entryhi;
113 uint64_t pagemask;
114 uint64_t status;
115 uint64_t badvaddr;
116 uint64_t cause;
117 uint64_t depc;
118 uint64_t desave;
119 uint64_t debug;
120 uint64_t multicoredebug;
121 uint64_t perfval[2];
122 uint64_t perfctrl[2];
145 uint64_t status;
146 uint64_t address[4];
147 uint64_t address_mask[4];
148 uint64_t asid[4];
149 uint64_t control[4];
196 uint64_t entryhi;
197 uint64_t pagemask;
198 uint64_t entrylo[2];
199 uint64_t reserved;
246 }__attribute__ ((aligned(sizeof(uint64_t)))) cvmx_debug_state_t;
248 typedef int cvmx_debug_state_t_should_fit_inside_a_cache_block[sizeof(cvmx_debug_state_t)+sizeof(cvmx_spinlock_t)+4*sizeof(uint64_t) > 128 ? -1 : 1];
252 uint64_t version; /* This is always the first element of this struct */
253 uint64_t comm_type; /* cvmx_debug_comm_type_t */
254 volatile uint64_t comm_changed; /* cvmx_debug_comm_type_t+1 when someone wants to change it. */
255 volatile uint64_t init_complete;
265 uint64_t u64;
268 uint64_t rsrvd:32; /**< Unused */
269 uint64_t dbd:1; /**< Indicates whether the last debug exception or
272 uint64_t dm:1; /**< Indicates that the processor is operating in Debug
274 uint64_t nodcr:1; /**< Indicates whether the dseg segment is present */
275 uint64_t lsnm:1; /**< Controls access of loads/stores between the dseg
278 uint64_t doze:1; /**< Indicates that the processor was in a low-power mode
280 uint64_t halt:1; /**< Indicates that the internal processor system bus clock
282 uint64_t countdm:1; /**< Controls or indicates the Count register behavior in
293 uint64_t ibusep:1; /**< Indicates if a Bus Error exception is pending from an
305 uint64_t mcheckp:1; /**< Indicates if a Machine Check exception is pending.
316 uint64_t cacheep:1; /**< Indicates if a Cache Error is pending. Set when a
326 uint64_t dbusep:1; /**< Indicates if a Data Access Bus Error exception is
337 uint64_t iexi:1; /**< An Imprecise Error eXception Inhibit (IEXI) controls
349 uint64_t ddbsimpr:1; /**< Indicates that a Debug Data Break Store Imprecise
359 uint64_t ddblimpr:1; /**< Indicates that a Debug Data Break Load Imprecise
369 uint64_t ejtagver:3; /**< Provides the EJTAG version.
374 uint64_t dexccode:5; /**< Indicates the cause of the latest exception in Debug
384 uint64_t nosst:1; /**< Indicates whether the single-step feature controllable
392 uint64_t sst:1; /**< Controls whether single-step feature is enabled:
398 uint64_t rsrvd2:2; /**< Must be zero */
399 uint64_t dint:1; /**< Indicates that a Debug Interrupt exception occurred.
405 uint64_t dib:1; /**< Indicates that a Debug Instruction Break exception
411 uint64_t ddbs:1; /**< Indicates that a Debug Data Break Store exception
418 uint64_t ddbl:1; /**< Indicates that a Debug Data Break Load exception
425 uint64_t dbp:1; /**< Indicates that a Debug Breakpoint exception
429 uint64_t dss:1; /**< Indicates that a Debug Single Step exception