Lines Matching refs:tmp_reg
291 uint32_t tmp_reg;
293 tmp_reg = ioread32be(&qmi_rg->fmqm_gc);
294 tmp_reg &= ~QMI_CFG_ENQ_MASK;
295 tmp_reg |= ((uint32_t)val << 8);
296 iowrite32be(tmp_reg, &qmi_rg->fmqm_gc);
301 uint32_t tmp_reg;
303 tmp_reg = ioread32be(&qmi_rg->fmqm_gc);
304 tmp_reg &= ~QMI_CFG_DEQ_MASK;
305 tmp_reg |= (uint32_t)val;
306 iowrite32be(tmp_reg, &qmi_rg->fmqm_gc);
409 uint32_t tmp_reg;
414 tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id - 1]);
415 return (uint16_t)((tmp_reg & BMI_FIFO_SIZE_MASK) + 1);
430 uint32_t tmp_reg;
435 tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id-1]);
436 return (uint16_t)((tmp_reg & BMI_EXTRA_FIFO_SIZE_MASK) >>
630 uint32_t tmp_reg;
635 tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg1);
637 (((tmp_reg & BMI_TOTAL_FIFO_SIZE_MASK) >> BMI_CFG1_FIFO_SIZE_SHIFT) + 1) * FMAN_BMI_FIFO_UNITS;
639 tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg2);
641 (uint8_t)(((tmp_reg & BMI_TOTAL_NUM_OF_TASKS_MASK) >> BMI_CFG2_TASKS_SHIFT) + 1);
643 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmtr);
644 cfg->dma_comm_qtsh_asrt_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT);
646 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmhy);
647 cfg->dma_comm_qtsh_clr_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT);
649 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmmr);
650 cfg->dma_cache_override = (enum fman_dma_cache_override)((tmp_reg & DMA_MODE_CACHE_OR_MASK) >> DMA_MODE_CACHE_OR_SHIFT);
651 cfg->dma_cam_num_of_entries = (uint8_t)((((tmp_reg & DMA_MODE_CEN_MASK) >> DMA_MODE_CEN_SHIFT) +1)*DMA_CAM_UNITS);
652 cfg->dma_aid_override = (bool)((tmp_reg & DMA_MODE_AID_OR)? TRUE:FALSE);
653 cfg->dma_dbg_cnt_mode = (enum fman_dma_dbg_cnt_mode)((tmp_reg & DMA_MODE_DBG_MASK) >> DMA_MODE_DBG_SHIFT);
654 cfg->dma_en_emergency = (bool)((tmp_reg & DMA_MODE_EB)? TRUE : FALSE);
656 tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_mxd);
657 cfg->disp_limit_tsh = (uint8_t)((tmp_reg & FPM_DISP_LIMIT_MASK) >> FPM_DISP_LIMIT_SHIFT);
659 tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist1);
660 cfg->prs_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_PRS_MASK ) >> FPM_THR1_PRS_SHIFT);
661 cfg->plcr_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_KG_MASK ) >> FPM_THR1_KG_SHIFT);
662 cfg->kg_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_PLCR_MASK ) >> FPM_THR1_PLCR_SHIFT);
663 cfg->bmi_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_BMI_MASK ) >> FPM_THR1_BMI_SHIFT);
665 tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist2);
666 cfg->qmi_enq_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_QMI_ENQ_MASK ) >> FPM_THR2_QMI_ENQ_SHIFT);
667 cfg->qmi_deq_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_QMI_DEQ_MASK ) >> FPM_THR2_QMI_DEQ_SHIFT);
668 cfg->fm_ctl1_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL1_MASK ) >> FPM_THR2_FM_CTL1_SHIFT);
669 cfg->fm_ctl2_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL2_MASK ) >> FPM_THR2_FM_CTL2_SHIFT);
671 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmsetr);
672 cfg->dma_sos_emergency = tmp_reg;
674 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmwcr);
675 cfg->dma_watchdog = tmp_reg/cfg->clk_freq;
677 tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmemsr);
678 cfg->dma_en_emergency_smoother = (bool)((tmp_reg & DMA_EMSR_EMSTR_MASK)? TRUE : FALSE);
679 cfg->dma_emergency_switch_counter = (tmp_reg & DMA_EMSR_EMSTR_MASK);
698 uint32_t tmp_reg;
705 tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
707 iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg,
711 tmp_reg = 0;
712 tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
714 tmp_reg |= DMA_MODE_AID_OR;
716 tmp_reg |= DMA_MODE_BER;
720 tmp_reg |= DMA_MODE_ECC;
722 tmp_reg |= DMA_MODE_SBER;
724 tmp_reg |= (uint32_t)(DMA_MODE_AXI_DBG_MASK &
728 tmp_reg |= cfg->dma_emergency_bus_select;
729 tmp_reg |= cfg->dma_emergency_level << DMA_MODE_EMER_LVL_SHIFT;
734 tmp_reg |= ((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) <<
736 tmp_reg |= DMA_MODE_SECURE_PROT;
737 tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
738 tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
741 tmp_reg |= DMA_MODE_EMER_READ;
743 iowrite32be(tmp_reg, &dma_rg->fmdmmr);
746 tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_asrt_emer <<
752 iowrite32be(tmp_reg, &dma_rg->fmdmtr);
755 tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_clr_emer <<
761 iowrite32be(tmp_reg, &dma_rg->fmdmhy);
777 uint32_t tmp_reg;
783 tmp_reg = (uint32_t)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
784 iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
786 tmp_reg = (((uint32_t)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
790 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
792 tmp_reg = (((uint32_t)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
796 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
799 tmp_reg = 0;
801 tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
805 tmp_reg |= FPM_EV_MASK_STALL_EN;
807 tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
809 tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
810 tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
811 tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
813 tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
815 tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
816 iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
826 tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
829 tmp_reg |= FPM_RAM_RAMS_ECC_EN_SRC_SEL;
833 tmp_reg |= FPM_RAM_MURAM_TEST_ECC;
835 tmp_reg |= FPM_RAM_IRAM_TEST_ECC;
836 iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
838 tmp_reg = 0;
840 tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
844 tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
847 iowrite32be(tmp_reg, &fpm_rg->fm_rie);
854 uint32_t tmp_reg;
861 tmp_reg = cfg->fifo_base_addr;
862 tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
864 tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
866 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
868 tmp_reg = ((uint32_t)(cfg->total_num_of_tasks - 1) <<
871 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
874 tmp_reg = 0;
882 tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
884 tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
886 tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
888 tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
889 iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
896 uint32_t tmp_reg;
906 tmp_reg = 0;
908 tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
910 tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
912 iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
921 tmp_reg = (uint32_t)((period_in_fm_clocks / 64) + 1);
923 tmp_reg = (uint32_t)(period_in_fm_clocks / 64);
924 if (!tmp_reg)
925 tmp_reg = 1;
927 tmp_reg <<= QMI_TAPC_TAP;
928 iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc);
930 tmp_reg = 0;
934 tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
936 iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
1008 /* Add this port to tmp_reg */
1391 /* clear tmp_reg event bits in order not to clear standing events */