Lines Matching defs:tmpReg
980 uint32_t tmpReg = *p_SoftSeqAttachReg, tmpPrsOffset;
989 tmpReg |= PRS_HDR_ERROR_DIS;
999 tmpReg |= PRS_HDR_MPLS_LBL_INTER_EN;
1007 tmpReg |= ((uint32_t)hdrNum * PRS_HDR_ENTRY_SIZE)
1012 tmpReg |= PRS_HDR_PPPOE_MTU_CHECK_EN;
1016 tmpReg |= PRS_HDR_IPV6_ROUTE_HDR_EN;
1020 tmpReg |= PRS_HDR_TCP_PAD_REMOVAL;
1022 tmpReg &= ~PRS_HDR_TCP_PAD_REMOVAL;
1026 tmpReg |= PRS_HDR_UDP_PAD_REMOVAL;
1028 tmpReg &= ~PRS_HDR_UDP_PAD_REMOVAL;
1042 tmpReg |= (PRS_HDR_SW_PRS_EN | tmpPrsOffset);
1044 *p_SoftSeqAttachReg = tmpReg;
1114 uint32_t tmpReg;
1340 tmpReg = (uint32_t)(absoluteProfileId | NIA_PLCR_ABSOLUTE);
1344 WRITE_UINT32(*p_BmiPrsNia, (uint32_t)(NIA_ENG_PLCR | tmpReg));
1386 tmpReg = 0;
1395 tmpReg = NIA_KG_CC_EN;
1412 tmpReg |= (uint32_t)(NIA_KG_DIRECT | physicalSchemeId);
1414 WRITE_UINT32(*p_BmiPrsNia, NIA_ENG_KG | tmpReg);
1610 tmpReg = PRS_TPID_DFLT;
1613 tmpReg &= PRS_TPID2_MASK;
1614 tmpReg |= (uint32_t)p_PcdParams->p_PrsParams->vlanTpid1
1619 tmpReg &= PRS_TPID1_MASK;
1620 tmpReg |= (uint32_t)p_PcdParams->p_PrsParams->vlanTpid2;
1621 }WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->pctpid, tmpReg);
1892 uint32_t tmpReg;
1905 tmpReg = GET_UINT32(*p_BmiCfgReg) & ~BMI_CMD_ATTR_MACCMD_MASK;
1906 tmpReg |= BMI_CMD_ATTR_MACCMD_SECURED;
1907 tmpReg |= (((uint32_t)dfltSci << BMI_CMD_ATTR_MACCMD_SC_SHIFT)
1910 WRITE_UINT32(*p_BmiCfgReg, tmpReg);
2215 uint32_t tmpReg;
2377 tmpReg =
2380 (((tmpReg & BMI_RX_FIFO_PRI_ELEVATION_MASK)
2383 p_FmPort->p_FmPortDriverParam->rxFifoThreshold = (((tmpReg
2402 tmpReg = 0x00001013;
2404 tmpReg);
2407 tmpReg =
2409 p_FmPort->p_FmPortDriverParam->txFifoMinFillLevel = ((tmpReg
2413 (uint8_t)(((tmpReg & BMI_FIFO_PIPELINE_DEPTH_MASK)
2415 p_FmPort->p_FmPortDriverParam->txFifoLowComfLevel = (((tmpReg
2446 tmpReg =
2449 (uint8_t)(((tmpReg & BMI_FIFO_PIPELINE_DEPTH_MASK)
3705 uint32_t tmpReg;
3723 tmpReg = GET_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tpfcm[0]);
3724 tmpReg &= ~(0xf << ((7 - prio) * 4));
3726 tmpReg |= wqTmpReg;
3729 tmpReg);
4427 uint32_t tmpReg = 0, tmp = 0;
4475 tmpReg = GET_UINT32(*p_BmiStorageProfileId) & ~BMI_SP_ID_MASK;
4476 tmpReg |= (uint32_t)hwStoragePrflId << BMI_SP_ID_SHIFT;
4477 WRITE_UINT32(*p_BmiStorageProfileId, tmpReg);
4479 tmpReg = GET_UINT32(*p_BmiVspe);
4480 WRITE_UINT32(*p_BmiVspe, tmpReg | BMI_SP_EN);
4489 tmpReg = NIA_ENG_BMI | NIA_BMI_AC_FETCH_ALL_FRAME;
4491 tmpReg);
4507 tmpReg = GET_UINT32(*p_BmiStorageProfileId) & ~BMI_SP_ID_MASK;
4508 tmpReg |= (uint32_t)hwStoragePrflId << BMI_SP_ID_SHIFT;
4509 WRITE_UINT32(*p_BmiStorageProfileId, tmpReg);
4511 tmpReg = GET_UINT32(*p_BmiVspe);
4512 WRITE_UINT32(*p_BmiVspe, tmpReg | BMI_SP_EN | tmp);
4572 uint32_t tmpReg;
4581 tmpReg = (uint32_t)((p_FmPort->pcdEngines & FM_PCD_CC) ? NIA_KG_CC_EN : 0);
4634 NIA_ENG_KG | tmpReg | NIA_KG_DIRECT | (uint32_t)physicalSchemeId);
4638 WRITE_UINT32(*p_BmiHpnia, NIA_ENG_KG | tmpReg);
4650 uint32_t tmpReg;
4673 tmpReg = GET_UINT32(*p_BmiNia) & BMI_RFNE_FDCS_MASK;
4678 tmpReg = 0;
4697 tmpReg |= (uint32_t)(NIA_ENG_PLCR | NIA_PLCR_ABSOLUTE | absoluteProfileId);
4702 WRITE_UINT32(*p_BmiHpnia, tmpReg);
4707 tmpReg |= (GET_UINT32(*p_BmiNia) & BMI_RFNE_FDCS_MASK);
4709 WRITE_UINT32(*p_BmiNia, tmpReg);