Lines Matching defs:ah
19 #include "ah.h"
36 ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds)
38 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
61 struct ath_hal *ah,
76 desclen = (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) ? 0x18 : 0x17;
138 ar9300_set_desc_link(struct ath_hal *ah, void *ds, u_int32_t link)
153 ar9300_get_desc_link_ptr(struct ath_hal *ah, void *ds, u_int32_t **link)
161 ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds)
172 ar9300_clear_dest_mask(struct ath_hal *ah, void *ds)
206 ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts)
225 ar9300_set_selfgenrate_limit(ah, ts->ts_rate);
232 ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *txstatus)
234 struct ath_hal_9300 *ahp = AH9300(ah);
246 ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
248 struct ath_hal_9300 *ahp = AH9300(ah);
264 ath_hal_printf(ah,
266 ath_hal_printf(ah,
318 ar9300_update_tx_trig_level(ah, AH_TRUE);
331 ar9300_update_tx_trig_level(ah, AH_TRUE);
335 ar9300_update_tx_trig_level(ah, AH_TRUE);
378 ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts,
445 ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode)
462 HALDEBUG(ah, HAL_DEBUG_TXDESC, "s0(%x) s1(%x)\n",
465 HALDEBUG(ah, HAL_DEBUG_TXDESC, "txe(%x) txd(%x)\n",
466 OS_REG_READ(ah, AR_Q_TXE),
467 OS_REG_READ(ah, AR_Q_TXD)
470 val = OS_REG_READ(ah, AR_QTXDP(i));
471 val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT;
472 HALDEBUG(ah, HAL_DEBUG_TXDESC, "[%d] %x %d\n", i, val, val2);
477 OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum);
489 OS_REG_WRITE(ah, AR_PHY_TEST,
490 (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
492 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
493 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
494 OS_REG_WRITE(ah, AR_DIAG_SW,
495 (OS_REG_READ(ah, AR_DIAG_SW) |
499 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */
505 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
506 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
507 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100);
508 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100);
509 OS_REG_WRITE(ah, AR_TIME_OUT, 2);
510 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100);
513 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
515 OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum);
517 OS_REG_WRITE(ah, AR_TXCFG, txcfg);
519 OS_REG_WRITE(ah, AR_QMISC(qnum), /* set QCU modes */
533 OS_REG_WRITE(ah, AR_Q_TXD, 1 << i);
536 OS_REG_WRITE(ah, AR_Q_TXD, qbits);
539 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
540 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
542 OS_REG_WRITE(ah, AR_DMISC(qnum),
554 OS_REG_WRITE(ah, AR_DQCUMASK(i), 0);
559 OS_REG_WRITE(ah, AR_PHY_TEST,
560 (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR));
561 OS_REG_WRITE(ah, AR_DIAG_SW,
562 (OS_REG_READ(ah, AR_DIAG_SW) &
570 ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num)
577 ar9300_is_tx_done(struct ath_hal *ah)
579 struct ath_hal_9300 *ahp = AH9300(ah);
592 struct ath_hal *ah,
602 struct ath_hal_9300 *ahp = AH9300(ah);
649 void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask)
651 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rxchainmask);
654 void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit)
657 reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG);
661 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS));
662 OS_REG_WRITE(ah, AR_LOC_TIMER_REG, 0);
666 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS));
705 struct ath_hal *ah,
716 struct ath_hal_private *ap = AH_PRIVATE(ah);
743 mode = ath_hal_get_curmode(ah, ap->ah_curchan);
746 if (ah->ah_config.ath_hal_desc_tpc) {
752 txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex,
755 txpower = AH9300(ah)->paprd_training_power;
791 if (ah->ah_config.ath_hal_desc_tpc) {
798 ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode);
800 txpower = AH9300(ah)->paprd_training_power;
810 ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode);
812 txpower = AH9300(ah)->paprd_training_power;
821 ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode);
823 txpower = AH9300(ah)->paprd_training_power;
858 ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
873 ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
892 ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
902 ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
910 ar9300_set_11n_burst_duration(struct ath_hal *ah, struct ath_desc *ds,
920 ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds)
928 ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds)
936 ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds)
944 ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds)
953 ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, struct ath_desc *ds,
966 ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info)
968 desc_info->txctl_numwords = TXCTL_NUMWORDS(ah);
969 desc_info->txctl_offset = TXCTL_OFFSET(ah);
970 desc_info->txstatus_numwords = TXSTATUS_NUMWORDS(ah);
971 desc_info->txstatus_offset = TXSTATUS_OFFSET(ah);
973 desc_info->rxctl_numwords = RXCTL_NUMWORDS(ah);
974 desc_info->rxctl_offset = RXCTL_OFFSET(ah);
975 desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah);
976 desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah);