Lines Matching refs:p_cap
688 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
717 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
771 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
807 *result = p_cap->halNumAntCfg2Ghz;
810 *result = p_cap->halNumAntCfg5Ghz;
813 *result = p_cap->hal_rx_stbc_support;
816 *result = p_cap->hal_tx_stbc_support;
820 *result = p_cap->halLDPCSupport;
826 (p_cap->halTxChainMask & 0x3) != 0x3 ||
827 (p_cap->halRxChainMask & 0x3) != 0x3) ?
831 (p_cap->halTxChainMask & 0x7) != 0x7 ||
832 (p_cap->halRxChainMask & 0x7) != 0x7) ?
885 *result = p_cap->halApmEnable;
888 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
890 *result = p_cap->hal_pcie_lcr_offset;
971 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
976 if (! p_cap->halTkipMicTxRxKeySupport)
1027 if (p_cap->halTsfAddSupport) {
2341 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2346 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
3220 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3229 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {