Lines Matching refs:udma_q
103 * @param udma_q udma queue data structure
107 static int al_udma_q_config(struct al_udma_q *udma_q)
112 if (udma_q->udma->type == UDMA_TX) {
113 reg_addr = &udma_q->q_regs->m2s_q.rlimit.mask;
126 * @param udma_q udma queue data structure
130 static int al_udma_q_config_compl(struct al_udma_q *udma_q)
135 if (udma_q->udma->type == UDMA_TX)
136 reg_addr = &udma_q->q_regs->m2s_q.comp_cfg;
138 reg_addr = &udma_q->q_regs->s2m_q.comp_cfg;
142 if (udma_q->flags & AL_UDMA_Q_FLAGS_NO_COMP_UPDATE)
147 if (udma_q->flags & AL_UDMA_Q_FLAGS_EN_COMP_COAL)
155 if (udma_q->udma->type == UDMA_RX) {
157 &udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c);
160 val |= (udma_q->cdesc_size >> 2)
162 al_reg_write32(&udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c
171 * @param udma_q udma queue data structure
173 static int al_udma_q_set_pointers(struct al_udma_q *udma_q)
177 al_assert((AL_ADDR_LOW(udma_q->desc_phy_base) &
179 al_reg_write32(&udma_q->q_regs->rings.drbp_low,
180 AL_ADDR_LOW(udma_q->desc_phy_base));
181 al_reg_write32(&udma_q->q_regs->rings.drbp_high,
182 AL_ADDR_HIGH(udma_q->desc_phy_base));
184 al_reg_write32(&udma_q->q_regs->rings.drl, udma_q->size);
187 if (udma_q->cdesc_base_ptr == NULL) {
188 udma_q->flags |= AL_UDMA_Q_FLAGS_NO_COMP_UPDATE;
192 al_assert((AL_ADDR_LOW(udma_q->cdesc_phy_base) &
194 al_reg_write32(&udma_q->q_regs->rings.crbp_low,
195 AL_ADDR_LOW(udma_q->cdesc_phy_base));
196 al_reg_write32(&udma_q->q_regs->rings.crbp_high,
197 AL_ADDR_HIGH(udma_q->cdesc_phy_base));
199 al_udma_q_config_compl(udma_q);
206 * @param udma_q udma queue data structure
211 static int al_udma_q_enable(struct al_udma_q *udma_q, int enable)
213 uint32_t reg = al_reg_read32(&udma_q->q_regs->rings.cfg);
217 udma_q->status = AL_QUEUE_ENABLED;
220 udma_q->status = AL_QUEUE_DISABLED;
222 al_reg_write32(&udma_q->q_regs->rings.cfg, reg);
262 udma->udma_q[i].status = AL_QUEUE_NOT_INITIALIZED;
277 struct al_udma_q *udma_q;
287 if (udma->udma_q[qid].status == AL_QUEUE_ENABLED) {
308 udma_q = &udma->udma_q[qid];
311 udma_q->q_regs = (union udma_q_regs __iomem *)
314 udma_q->q_regs = (union udma_q_regs __iomem *)
317 udma_q->adapter_rev_id = q_params->adapter_rev_id;
318 udma_q->size = q_params->size;
319 udma_q->size_mask = q_params->size - 1;
320 udma_q->desc_base_ptr = q_params->desc_base;
321 udma_q->desc_phy_base = q_params->desc_phy_base;
322 udma_q->cdesc_base_ptr = q_params->cdesc_base;
323 udma_q->cdesc_phy_base = q_params->cdesc_phy_base;
324 udma_q->cdesc_size = q_params->cdesc_size;
326 udma_q->next_desc_idx = 0;
327 udma_q->next_cdesc_idx = 0;
328 udma_q->end_cdesc_ptr = (uint8_t *) udma_q->cdesc_base_ptr +
329 (udma_q->size - 1) * udma_q->cdesc_size;
330 udma_q->comp_head_idx = 0;
331 udma_q->comp_head_ptr = (union al_udma_cdesc *)udma_q->cdesc_base_ptr;
332 udma_q->desc_ring_id = AL_UDMA_INITIAL_RING_ID;
333 udma_q->comp_ring_id = AL_UDMA_INITIAL_RING_ID;
335 udma_q->desc_ctrl_bits = AL_UDMA_INITIAL_RING_ID <<
338 udma_q->pkt_crnt_descs = 0;
339 udma_q->flags = 0;
340 udma_q->status = AL_QUEUE_DISABLED;
341 udma_q->udma = udma;
342 udma_q->qid = qid;
345 al_udma_q_config(udma_q);
347 al_udma_q_set_pointers(udma_q);
350 al_udma_q_enable(udma_q, 1);
354 udma_q->udma->name, udma_q->qid,
370 int al_udma_q_reset(struct al_udma_q *udma_q)
378 al_assert(udma_q);
381 al_udma_q_enable(udma_q, 0);
384 status_reg = &udma_q->q_regs->rings.status;
399 "scheduler disable\n", udma_q->udma->name, udma_q->qid,
406 dcp_reg = &udma_q->q_regs->rings.dcp;
407 crhp_reg = &udma_q->q_regs->rings.crhp;
422 udma_q->udma->name, udma_q->qid, __func__);
427 if (udma_q->udma->type == UDMA_TX)
428 q_sw_ctrl_reg = &udma_q->q_regs->m2s_q.q_sw_ctrl;
430 q_sw_ctrl_reg = &udma_q->q_regs->s2m_q.q_sw_ctrl;
451 *q_handle = &udma->udma_q[qid];
554 struct al_udma_q *udma_q,
562 al_assert(!(udma_q->flags & AL_UDMA_Q_FLAGS_NO_COMP_UPDATE));
565 curr = udma_q->comp_head_ptr;
569 if (unlikely(al_udma_new_cdesc(udma_q, comp_flags) == AL_FALSE))
572 count = udma_q->pkt_crnt_descs + 1;
574 curr = al_cdesc_next_update(udma_q, curr);
576 if (unlikely(al_udma_new_cdesc(udma_q, comp_flags)
582 udma_q->pkt_crnt_descs = count;
583 udma_q->comp_head_ptr = curr;
588 al_assert(count <= udma_q->size);
591 *cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);
592 udma_q->pkt_crnt_descs = 0;
593 udma_q->comp_head_ptr = al_cdesc_next_update(udma_q, curr);
596 " descs %d\n", udma_q->udma->name, udma_q->qid, *cdesc,
597 udma_q->next_cdesc_idx, count);