Lines Matching refs:udma_q
816 int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q,
819 struct udma_rlimit_common *rlimit_regs = &udma_q->q_regs->m2s_q.rlimit;
824 int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q,
827 struct udma_rlimit_common *rlimit_regs = &udma_q->q_regs->m2s_q.rlimit;
832 udma_q->udma->name, udma_q->qid, act);
839 int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q,
842 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
851 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
853 reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_2);
859 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_2, reg);
861 reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_3);
864 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_3, reg);
869 int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set)
871 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
877 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
882 int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q)
884 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl);
887 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl, reg);
1001 int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable)
1003 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
1010 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
1016 int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t
1019 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
1026 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
1028 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, coal_timeout);
1053 int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q, al_bool enable,
1056 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
1070 al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
1076 int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q,
1079 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
1090 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
1092 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, conf->comp_timer);
1094 reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
1107 al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
1109 reg = al_reg_read32(&udma_q->q_regs->s2m_q.qos_cfg);
1112 al_reg_write32(&udma_q->q_regs->s2m_q.qos_cfg, reg);