arm/ti/ti_sdma.c

128 	struct ti_sdma_channel sc_channel[NUM_DMA_CHANNELS];
238 				channel = &sc->sc_channel[ch];
352 	channel = &sc->sc_channel[*ch];
477 	sc->sc_channel[ch].reg_cicr = 0x0000;
489 	sc->sc_channel[ch].need_reg_write = 1;
538 	sc->sc_channel[ch].reg_cicr = flags;
550 	sc->sc_channel[ch].need_reg_write = 1;
646 	channel = &sc->sc_channel[ch];
740 	channel = &sc->sc_channel[ch];
831 	sc->sc_channel[ch].need_reg_write = 1;
867 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_ENDIANISM(1);
868 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_ENDIANISM(src);
870 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_ENDIANISM(1);
871 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_ENDIANISM(dst);
873 	sc->sc_channel[ch].need_reg_write = 1;
912 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_BURST_MODE(0x3);
913 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_BURST_MODE(src);
915 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_BURST_MODE(0x3);
916 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_BURST_MODE(dst);
918 	sc->sc_channel[ch].need_reg_write = 1;
954 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DATA_TYPE(0x3);
955 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DATA_TYPE(type);
957 	sc->sc_channel[ch].need_reg_write = 1;
994 	sc->sc_channel[ch].callback = callback;
995 	sc->sc_channel[ch].callback_data = data;
997 	sc->sc_channel[ch].need_reg_write = 1;
1038 	ccr = sc->sc_channel[ch].reg_ccr;
1058 	sc->sc_channel[ch].reg_ccr = ccr;
1060 	sc->sc_channel[ch].need_reg_write = 1;
1102 	ccr = sc->sc_channel[ch].reg_ccr;
1110 	sc->sc_channel[ch].reg_ccr = ccr;
1112 	sc->sc_channel[ch].need_reg_write = 1;