Lines Matching refs:cpsw_read_4
372 #define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg))
394 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET)
407 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));
556 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
569 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
576 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
582 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
609 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
848 reg = cpsw_read_4(sc, CPSW_SS_IDVER);
1171 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
1301 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
1368 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL);
1463 r = cpsw_read_4(sc, reg);
1493 r = cpsw_read_4(sc->swsc, sc->phyaccess);
1536 mac_control = cpsw_read_4(sc->swsc, reg);
1823 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc)
2091 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED);
2093 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS);
2121 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan)));
2123 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan)));
2143 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan)));
2145 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan)));
2166 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0));
2176 cpsw_read_4(sc, MDIOLINKINTMASKED));
2250 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)));
2252 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)));
2303 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0);
2304 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1);
2305 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2);
2538 r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
2556 r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
2574 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg);
2604 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
2814 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port));
2817 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
2843 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));