Lines Matching refs:timer
93 } timer[VHPET_NUM_TIMERS];
110 cap &= ~HPET_CAP_COUNT_SIZE; /* 32-bit timer */
130 if ((vhpet->timer[n].cap_config & msi_enable) == msi_enable)
140 * If the timer is configured to use MSI then treat it as if the
141 * timer is not connected to the ioapic.
146 return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ROUTE) >> 9);
182 KASSERT(pin != 0, ("vhpet timer %d irq incorrectly routed", n));
192 return ((vhpet->timer[n].cap_config & HPET_TCNF_TYPE) != 0);
199 return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ENB) != 0);
207 "timer %d is using MSI", n));
209 if ((vhpet->timer[n].cap_config & HPET_TCNF_INT_TYPE) == 0)
220 /* If interrupts are not enabled for this timer then just return. */
233 lapic_intr_msi(vhpet->vm, vhpet->timer[n].msireg >> 32,
234 vhpet->timer[n].msireg & 0xffffffff);
257 KASSERT(vhpet->timer[n].comprate != 0, ("hpet t%d is not periodic", n));
259 compval = vhpet->timer[n].compval;
260 comprate = vhpet->timer[n].comprate;
275 vhpet->timer[n].compval = compnext;
291 callout = &vhpet->timer[n].callout;
321 callout_stop(&vhpet->timer[n].callout);
325 * had a chance to execute yet then trigger the timer interrupt
326 * here. Failing to do so will result in a missed timer interrupt
330 if (vhpet->timer[n].callout_sbt < now) {
332 "stopping timer", n);
342 if (vhpet->timer[n].comprate != 0)
353 delta = (vhpet->timer[n].compval - counter) * vhpet->freq_sbt;
355 vhpet->timer[n].callout_sbt = now + delta;
356 callout_reset_sbt(&vhpet->timer[n].callout, vhpet->timer[n].callout_sbt,
357 precision, vhpet_handler, &vhpet->timer[n].arg, C_ABSOLUTE);
406 panic("vhpet timer %d isr should not be asserted", n);
409 oldval = vhpet->timer[n].cap_config;
419 vhpet->timer[n].cap_config = newval;
427 allowed_irqs = vhpet->timer[n].cap_config >> 32;
433 vhpet->timer[n].cap_config &= ~HPET_TCNF_INT_ROUTE;
437 vhpet->timer[n].comprate = 0;
440 * If the timer's ISR bit is set then clear it in the following cases:
445 * This is to ensure that this timer's level triggered interrupt does
449 KASSERT(old_pin != 0, ("timer %d isr asserted to ioapic pin %d",
573 old_compval = vhpet->timer[i].compval;
574 old_comprate = vhpet->timer[i].comprate;
582 val64 = vhpet->timer[i].comprate;
584 vhpet->timer[i].comprate = val64;
585 if ((vhpet->timer[i].cap_config &
587 vhpet->timer[i].compval = val64;
590 KASSERT(vhpet->timer[i].comprate == 0,
591 ("vhpet one-shot timer %d has invalid "
592 "rate %u", i, vhpet->timer[i].comprate));
593 val64 = vhpet->timer[i].compval;
595 vhpet->timer[i].compval = val64;
597 vhpet->timer[i].cap_config &= ~HPET_TCNF_VAL_SET;
599 if (vhpet->timer[i].compval != old_compval ||
600 vhpet->timer[i].comprate != old_comprate) {
612 update_register(&vhpet->timer[i].msireg, data, mask);
673 data = vhpet->timer[i].cap_config;
679 data = vhpet->timer[i].compval;
685 data = vhpet->timer[i].msireg;
728 * Initialize HPET timer hardware state.
731 vhpet->timer[i].cap_config = allowed_irqs << 32;
732 vhpet->timer[i].cap_config |= HPET_TCAP_PER_INT;
733 vhpet->timer[i].cap_config |= HPET_TCAP_FSB_INT_DEL;
735 vhpet->timer[i].compval = 0xffffffff;
736 callout_init(&vhpet->timer[i].callout, 1);
738 arg = &vhpet->timer[i].arg;
752 callout_drain(&vhpet->timer[i].callout);