Lines Matching refs:v2i64
873 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
890 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
902 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
919 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
920 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
926 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
947 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
952 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
959 // Custom lower v2i64 and v2f64 selects.
961 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1030 // In the customized shift lowering, the legal v4i32/v2i64 cases
1032 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1060 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1101 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1110 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
1112 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
1113 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
1133 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1141 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1328 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1336 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1362 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1409 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1505 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1670 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1678 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1687 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1692 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1714 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1720 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1871 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1872 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1873 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1878 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1883 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1897 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
2437 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2729 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
3957 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3958 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
8590 // For size optimization, also splat v2f64 and v2i64, and for size opt
9635 case MVT::v2i64:
9642 // SSE41 can compare v2i64 - select between indices 0 and 1.
10071 // Create a new build vector and cast to v2i64/v2f64.
10074 // Broadcast from v2i64/v2f64 and cast to final VT.
10860 if ((Subtarget.hasSSE41() || VT == MVT::v2i64 || VT == MVT::v2f64) &&
10961 // t18: v2i64 = bitcast t51
11261 case MVT::v2i64:
12228 MVT::v2i64, DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
12237 MVT::v2i64, DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
12241 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
12415 V = DAG.getBitcast(MVT::v2i64, V);
12416 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
13198 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
13199 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
13204 if (SDValue Broadcast = lowerShuffleAsBroadcast(DL, MVT::v2i64, V1, V2,
13216 MVT::v2i64,
13230 if (SDValue Shift = lowerShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask,
13237 DL, MVT::v2i64, V1, V2, Mask, Zeroable, Subtarget, DAG))
13243 DL, MVT::v2i64, V2, V1, InverseMask, Zeroable, Subtarget, DAG))
13250 if (SDValue Blend = lowerShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
13255 if (SDValue V = lowerShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
13262 if (SDValue Rotate = lowerShuffleAsRotate(DL, MVT::v2i64, V1, V2, Mask,
13266 if (SDValue Rotate = lowerShuffleAsByteRotate(DL, MVT::v2i64, V1, V2, Mask,
13274 return lowerShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2, Mask,
13283 return DAG.getBitcast(MVT::v2i64,
14691 case MVT::v2i64:
17186 ExtVT = MVT::v2i64;
17955 assert(OpVT.is128BitVector() && OpVT.isInteger() && OpVT != MVT::v2i64 &&
18695 assert((Src.getSimpleValueType() == MVT::v2i64 ||
18800 if (SrcVT == MVT::v2i64 || SrcVT == MVT::v4i64)
18965 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Op.getOperand(OpNo));
19028 ISD::OR, dl, MVT::v2i64,
19029 DAG.getBitcast(MVT::v2i64, Load),
19030 DAG.getBitcast(MVT::v2i64,
19101 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i64, N0);
19104 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::v2i64, ZExtIn,
19105 DAG.getBitcast(MVT::v2i64, VBias));
19287 case MVT::v2i64:
19614 // Use vpmovzdq for 4 lower elements v4i32 -> v2i64.
19615 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
19986 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
19988 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
20011 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
20146 if ((VT == MVT::v2i64 || VT == MVT::v4i64) &&
20176 if (VT == MVT::v2i64 && SrcVT == MVT::v2f32) {
20655 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
21648 if (VT == MVT::v2i64) {
21681 SB = DAG.getConstant(0x8000000080000000ULL, dl, MVT::v2i64);
21683 SB = DAG.getConstant(0x0000000080000000ULL, dl, MVT::v2i64);
21685 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op0, SB);
21686 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op1, SB);
22103 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
22518 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT;
22540 if (VT == MVT::v2i64) {
22592 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
23396 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v2i64, ShAmt);
23406 MVT::v2i64, ShAmt);
23420 MVT::v2i64, ShAmt);
25823 if ((VT == MVT::v2i64 || VT == MVT::v4i64) && Subtarget.hasSSE41()) {
25959 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64,
25960 DAG.getBitcast(MVT::v2i64, A),
25961 DAG.getBitcast(MVT::v2i64, B));
25963 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64,
25964 DAG.getBitcast(MVT::v2i64, Aodds),
25965 DAG.getBitcast(MVT::v2i64, Bodds));
25976 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
26291 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()), Callee,
26316 (VT != MVT::v2i64 && VT != MVT::v4i64));
26344 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
26357 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
26374 if (VT == MVT::v2i64)
26386 if (VT == MVT::v2i64)
26410 if (((!Subtarget.hasXOP() && VT == MVT::v2i64) ||
26540 if (VT == MVT::v2i64 && Amt.getOpcode() == ISD::BITCAST &&
26650 if (Subtarget.hasXOP() && (VT == MVT::v2i64 || VT == MVT::v4i32 ||
26664 if (VT == MVT::v2i64 && Opc != ISD::SRA) {
26676 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) &&
27273 // to v2i64 results at a time. The upper 32-bits contain the wrapped bits
27280 SDValue Res02 = DAG.getNode(X86ISD::PMULUDQ, DL, MVT::v2i64,
27281 DAG.getBitcast(MVT::v2i64, R),
27282 DAG.getBitcast(MVT::v2i64, Scale));
27283 SDValue Res13 = DAG.getNode(X86ISD::PMULUDQ, DL, MVT::v2i64,
27284 DAG.getBitcast(MVT::v2i64, R13),
27285 DAG.getBitcast(MVT::v2i64, Scale13));
27681 Src = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Src);
27684 MVT V2X64VT = DstVT == MVT::f64 ? MVT::v2f64 : MVT::v2i64;
27714 // chunks, thus directly computes the pop count for v2i64 and v4i64.
27726 // two v2i64 vectors which concatenated are the 4 population counts. We can
28084 SDValue SclToVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
28265 // If the index is v2i64 and we have VLX we can use xmm for data and index.
28266 if (Index.getValueType() == MVT::v2i64 && Subtarget.hasVLX()) {
28711 // Use a v2i64 if possible.
28715 if (isTypeLegal(MVT::v2i64) && !NoImplicitFloatOps) {
28717 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, N->getOperand(0));
28718 Wide = DAG.getNode(ISD::CTPOP, dl, MVT::v2i64, Wide);
28945 // to v2i64.
28948 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Lo);
28951 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Hi);
29163 if (Subtarget.hasDQI() && Subtarget.hasVLX() && SrcVT == MVT::v2i64) {
29177 if (SrcVT == MVT::v2i64 && !IsSigned && Subtarget.is64Bit() &&
29184 SDValue IsNeg = DAG.getSetCC(dl, MVT::v2i64, Src, Zero, ISD::SETLT);
29237 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, Src);
29240 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
29241 DAG.getBitcast(MVT::v2i64, VBias));
29400 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
29513 if (Index.getValueType() != MVT::v2i64)
30023 // XOP has v16i8/v8i16/v4i32/v2i64 variable vector shifts.
33852 (MaskVT == MVT::v2f64 || MaskVT == MVT::v2i64 || MaskVT == MVT::v4f64 ||
35302 // Look for a v2i64/v2f64 VZEXT_MOVL of a node that already produces zeros
35306 (VT == MVT::v2f64 || VT == MVT::v2i64) &&
35322 In.getOperand(0).getValueType() == MVT::v2i64)
35331 In.getOperand(1).getValueType() == MVT::v2i64)
36272 SExtVT = MVT::v2i64;
36421 V = DAG.getBitcast(MVT::v2i64, V);
36638 DAG.getBitcast(MVT::v2i64, N00));
36647 DAG.getBitcast(MVT::v2i64, Res));
37164 if ((SrcVT == MVT::v4i32 || SrcVT == MVT::v2i64) &&
37331 Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx,
37358 Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx,
40915 case MVT::v2i64: if (!Subtarget.hasSSE2()) return SDValue(); break;
41677 : (TLI.isTypeLegal(MVT::i64) ? MVT::v2i64 : MVT::v4i32);
43864 SDValue BCCmp = DAG.getBitcast(OpSize == 256 ? MVT::v4i64 : MVT::v2i64,
44045 // Only do this before legalize types since v2i64 could become v2i32.
44349 assert(InVT == MVT::v2i64 && "Unexpected VT!");
44909 // the PSADBW will be zero. If we promote/ narrow vectors, truncate the v2i64
45718 // extract (and v4i64 X, (not (concat Y1, Y2))), n -> andnp v2i64 X(n), Y1
45853 // Reduce v2i64 to v4i32 if we don't need the upper bits.
45855 if (VT == MVT::v2i64 && Src.getOpcode() == ISD::ANY_EXTEND &&
45894 if (N->getValueType(0) == MVT::v2i64 && LHS.hasOneUse() &&
45901 LHS = DAG.getBitcast(MVT::v2i64, LHS);
45902 return DAG.getNode(N->getOpcode(), dl, MVT::v2i64, LHS, RHS);
45904 if (N->getValueType(0) == MVT::v2i64 && RHS.hasOneUse() &&
45911 RHS = DAG.getBitcast(MVT::v2i64, RHS);
45912 return DAG.getNode(N->getOpcode(), dl, MVT::v2i64, LHS, RHS);
46992 case MVT::v2i64:
47050 case MVT::v2i64: