Lines Matching refs:Vec
5603 SDValue Vec;
5605 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
5607 Vec = DAG.getConstantFP(+0.0, dl, VT);
5611 Vec = DAG.getConstant(0, dl, VT);
5614 Vec = DAG.getConstant(0, dl, MVT::getVectorVT(MVT::i32, Num32BitElts));
5616 return DAG.getBitcast(VT, Vec);
5619 static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
5621 EVT VT = Vec.getValueType();
5636 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
5638 Vec->ops().slice(IdxVal, ElemsPerChunk));
5641 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
5650 static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
5652 assert((Vec.getValueType().is256BitVector() ||
5653 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
5654 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
5658 static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
5660 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
5661 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
5664 static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5670 if (Vec.isUndef())
5672 EVT VT = Vec.getValueType();
5685 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
5694 static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5696 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
5697 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
5702 static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements,
5705 assert(Vec.getValueSizeInBits() < VT.getSizeInBits() &&
5706 Vec.getValueType().getScalarType() == VT.getScalarType() &&
5710 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec,
5716 static SDValue widenSubVector(SDValue Vec, bool ZeroNewElements,
5719 assert(Vec.getValueSizeInBits() < WideSizeInBits &&
5720 (WideSizeInBits % Vec.getScalarValueSizeInBits()) == 0 &&
5722 unsigned WideNumElts = WideSizeInBits / Vec.getScalarValueSizeInBits();
5723 MVT SVT = Vec.getSimpleValueType().getScalarType();
5725 return widenSubVector(VT, Vec, ZeroNewElements, Subtarget, DAG, dl);
5815 SDValue Vec = Op.getOperand(0);
5824 return Vec;
5827 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
5842 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) {
5860 // Zero lower bits of the Vec
5862 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec,
5864 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5865 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5870 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5877 if (Vec.isUndef()) {
5884 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
5904 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx);
5905 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5907 Vec, ZeroIdx);
5910 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5911 Undef, Vec, ZeroIdx);
5914 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits);
5915 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits);
5917 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5926 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
5937 Vec = DAG.getNode(ISD::AND, dl, WideOpVT, Vec, VMask0);
5942 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5956 SDValue Low = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec,
5963 SDValue High = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec,
5969 Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Low, High);
5970 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec);
5997 SDValue Vec = DAG.getConstant(Ones, dl, MVT::getVectorVT(MVT::i32, NumElts));
5998 return DAG.getBitcast(VT, Vec);
7638 SDValue Vec = N->getOperand(0);
7646 return getShuffleScalarElt(Vec.getNode(), Index, DAG, Depth + 1);
10256 SDValue Vec = NumZero ? getZeroVector(ResVT, Subtarget, DAG, dl)
10265 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec,
10270 return Vec;
10324 SDValue Vec = Zeros ? DAG.getConstant(0, dl, ResVT) : DAG.getUNDEF(ResVT);
10326 return Vec;
10330 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec,
10349 SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT,
10352 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1),
17579 SDValue Vec = Op.getOperand(0);
17580 SDLoc dl(Vec);
17581 MVT VecVT = Vec.getSimpleValueType();
17596 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, ExtVecVT, Vec);
17610 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT,
17611 DAG.getUNDEF(WideVecVT), Vec,
17616 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideVecVT, Vec,
17619 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
17627 SDValue Vec = Op.getOperand(0);
17628 MVT VecVT = Vec.getSimpleValueType();
17674 Vec = extract128BitVector(Vec, IdxVal, DAG, dl);
17683 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
17698 DAG.getBitcast(MVT::v4i32, Vec), Idx));
17713 if (VT.getSizeInBits() == 8 && Op->isOnlyUserOf(Vec.getNode())) {
17718 DAG.getBitcast(MVT::v4i32, Vec),
17729 DAG.getBitcast(MVT::v8i16, Vec),
17744 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask);
17745 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
17760 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask);
17761 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
17773 SDValue Vec = Op.getOperand(0);
17776 MVT VecVT = Vec.getSimpleValueType();
17785 DAG.getNode(ISD::SIGN_EXTEND, dl, ExtVecVT, Vec),
17793 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT, Vec, EltInVec,
17983 SDValue Vec = Op.getOperand(0);
17993 MVT VecVT = Vec.getSimpleValueType();
18000 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT,
18001 DAG.getUNDEF(WideVecVT), Vec,
18006 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideVecVT, Vec,
18009 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, Op.getValueType(), Vec,
35991 SDValue Vec = Op.getOperand(0);
35993 MVT VecVT = Vec.getSimpleValueType();
36008 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
36013 if (SimplifyDemandedBits(Vec, DemandedVecBits, DemandedVecElts,
36018 Vec, DemandedVecBits, DemandedVecElts, TLO.DAG, Depth + 1))
36029 SDValue Vec = Op.getOperand(0);
36032 MVT VecVT = Vec.getSimpleValueType();
36037 return TLO.CombineTo(Op, Vec);
36042 if (SimplifyDemandedBits(Vec, OriginalDemandedBits, DemandedVecElts,
36134 SDValue Vec = Op.getOperand(0);
36136 MVT VecVT = Vec.getSimpleValueType();
36139 return Vec;
37190 SDValue Vec = ExtElt->getOperand(0);
37193 EVT VecVT = Vec.getValueType();
37197 if (!Vec.hasOneUse() || !isNullConstant(Index) || VecVT.getScalarType() != VT)
37202 if (Vec.getOpcode() == ISD::SETCC && VT == MVT::i1) {
37203 EVT OpVT = Vec.getOperand(0).getValueType().getScalarType();
37210 Vec.getOperand(0), Index);
37212 Vec.getOperand(1), Index);
37213 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2));
37225 if (Vec.getOpcode() == ISD::VSELECT &&
37226 Vec.getOperand(0).getOpcode() == ISD::SETCC &&
37227 Vec.getOperand(0).getValueType().getScalarType() == MVT::i1 &&
37228 Vec.getOperand(0).getOperand(0).getValueType() == VecVT) {
37232 Vec.getOperand(0).getValueType().getScalarType(),
37233 Vec.getOperand(0), Index);
37235 Vec.getOperand(1), Index);
37237 Vec.getOperand(2), Index);
37244 switch (Vec.getOpcode()) {
37274 for (SDValue Op : Vec->ops())
37276 return DAG.getNode(Vec.getOpcode(), DL, VT, ExtOps);
43404 SDValue Vec;
43419 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);
43420 Vec = DAG.getBitcast(VT, Vec);
43429 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl);
43432 Vec = DAG.getVectorShuffle(VT, DL, Vec, Vec, ShuffleMask);
43442 Vec = DAG.getNode(ISD::AND, DL, VT, Vec, BitMask);
43446 Vec = DAG.getSetCC(DL, CCVT, Vec, BitMask, ISD::SETEQ);
43447 Vec = DAG.getSExtOrTrunc(Vec, DL, VT);
43452 return Vec;
43453 return DAG.getNode(ISD::SRL, DL, VT, Vec,
43570 SDValue Vec = V.getOperand(0);
43571 if (TLI.isNegatibleForFree(Vec, DAG, LegalOperations, CodeSize) == 2) {
43573 TLI.getNegatedExpression(Vec, DAG, LegalOperations, CodeSize);
45517 SDValue Vec = N->getOperand(0);
45523 if (Vec.isUndef() && SubVec.isUndef())
45527 if ((Vec.isUndef() || ISD::isBuildVectorAllZeros(Vec.getNode())) &&
45531 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
45568 (IdxVal != 0 || !Vec.isUndef())) {
45581 return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask);
45605 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST)
45610 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&